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改进如下：
- M+ o1 @5 N7 a
g) P/ G1 ~1 k3 U& o. _/ b. zHOTFIX VERSION: 015
( [5 S: t' y) s7 w+ w========================================================================================================
% J) O* n1 H3 Q7 h, iCCRID PRODUCT PRODUCTLEVEL2 TITLE5 m# {" ?/ P7 E' I- u7 g
========================================================================================================
% m1 [& G0 Y2 w1 T: f2 R+ z$ w264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip
( I5 V% |- v& l4 y609206 APD OTHER parallel command fails to run on mcm files
/ S7 a* z9 w6 u: T# i; P" d646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time% \1 a4 s" }' w4 P @: d
650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames+ P# o4 q7 a( N* F9 }' O% g
665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal6 F" U" u' Q5 r
666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import% u/ B$ \- |6 u5 y
669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n d1 i/ x3 F7 l
669769 PSPICE DEHDL Edit Model on page border causes crash0 B. \+ D; W6 @) x( a0 |
671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.: N' J! D7 O3 w# M: N& k7 B
672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl( V y& t- o) w! R3 ` }) r0 s
672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke% ?, M; a$ ~# ]- N# Q# z
672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa
7 S. s2 x' A" c+ C676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets
8 W0 F6 S- j+ C. m, e; h: l$ N677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets2 L$ t/ o9 n" m
677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.
/ w; Q+ X* k3 N; ~2 N3 y7 k# {8 b678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license) o* k! Z% \( G$ u h! A
678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM1 s9 t9 i; U" X/ q5 J
678794 SCM PACKAGER Unable to package subdesign
+ H+ A3 r U! _6 p. Q: S0 d678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.22 j+ U$ Q) t( {" o9 t6 D) a
678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced
3 H/ E& Y7 H9 \3 D679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns# _3 b& U" Y6 r! a+ E& t& w3 _
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i1 J! W P/ E' j+ y: Z
679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo
4 p1 S+ l3 i/ h8 B" H$ j4 G2 i" U679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.2 O; b; B" a' s9 d2 g% H- L
679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st" T2 G# Y }3 d8 b8 t
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri- W: E% t. x0 h# Z8 H3 m. d: ]
681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase
0 f( |4 O, p; S4 L/ r681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if
3 q: x0 D2 {1 o. S9 G682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte
" I$ K" _ e" [5 c+ n683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
3 J- b* L( a$ ^' T# U683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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