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本帖最后由 partime 于 2016-8-10 20:06 编辑 o% h x# g" c: v, B: j
6 O3 G: L' `" C! u' }7 ^: B不知道有没有人上传分享,我刚下载上传过来,现分享!
( z9 f8 k5 t: N6 k. g% x链接在下面,回复可见。顶起来,让更多的人看到!还有CCR,可以看看都修复了什么内容。+ Y0 [+ r; G Y, F
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; P/ u- \: O+ C9 H$ K4 W6 uCCRID PRODUCT PRODUCTLEVEL2 TITLE
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$ j3 J' Y; _$ A/ x- h& a 1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result$ d0 q4 U p' o& X2 J/ F2 l# J9 j
1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066; y' ?, I# [& o% g# h, k7 D
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once0 D0 _7 ~+ a7 |( ?6 @7 v2 M0 }2 B& w
1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
! `6 e* z4 `( {+ I" W% A 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
- |2 E' g" n7 ^4 y3 r I3 s0 i 1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
' m6 i: g N( A 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
6 V* d7 y, w4 k+ T" c1 I% ? 1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties( \! H9 |! z- {8 x \2 ?7 V
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed* v- j; q* R' x6 @- G
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
& C# h+ G( i7 e0 O 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component% i! [5 w; M Q! z8 ^1 k0 g) Z8 G
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior: v6 q0 E, b5 p8 I3 G
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design0 @5 X' J* d7 a& y* ?
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM# |: u% k. m4 K3 b1 S
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified6 {. d2 A% D* p2 O; ^
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
* k. `) `- i6 n. b5 Y 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
5 r6 N0 J* ~, \. ]! X, Z0 t2 V; i w2 o 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
4 O% c0 H3 u; d% X$ Z 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
1 m [# T- B! _7 M 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas2 O6 z% m. x( F+ D! q/ y: H
1598629 F2B PACKAGERXL Export Physical crashes
8 B$ i( D/ C/ B1 q; X 1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
* s" u9 Y7 p) R. F& e) x 1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
2 g$ Z9 y4 ^' l$ y( p8 U4 a 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
/ l: q) l, z& c! O 1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
7 | F) H+ T$ Y/ R5 T) D8 `( v 1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.6 H* l, K4 _) m0 A4 }* P
1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses4 k5 j. ]* M x* A4 H2 q1 V, M
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
. W, {. s2 P2 E' R+ y 1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command
8 z/ }0 N S( B8 L% W; ^9 P7 w- W 1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
8 O7 l- C" i+ s: i! y7 D 1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
' u: W1 S v. q5 x* _) c 1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard/ S+ A6 n- f. e8 i
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