AltiumDesigner15.0.7出来了！你会更新么？

HighGe

/ R7 n8 l& k6 @- r才看到网友说AD15出来了，然后刷微博就看到了这个。。。
% N' B2 z0 u! O$ T" @5 j; m

' a1 j* N3 h: {0 i  q

AltiumDesigner15.0.7出来了！
! Y) Z4 e) v* }: Y" l4 S我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，
或者说是，你是在修Bug么？？
貌似AD14就一直是Bug不断，这次AD15估计也一样，不过，
貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？
或者说，你会更新到AltiumDesigner15版本么？

. X7 H) ~' A$ yRelease Notes for Altium Designer Version 15.0
7 z7 K8 K; ]5 g! C& Z7 P2 C2 r) K) [Modified by Nikolay Ponomarenko on 17-Nov-2014
Key feature highlights
8 J1 l( e3 D/ V0 i' V5 wHigh Speed Design with xSignals
$ ^4 R( |' B* ^6 z/ SSolder Mask Expansion Enhancements
Accurate Route Length Calculation
& c, T# H4 ?$ f: PPolygon Enhancements
OLE Object Support in PCB Documents
Support for Rectangular Pad Holes
) b" W4 i; m* O2 N& u8 A/ J5 XSeparate 2D & 3D View Orientations
1 Y/ _: G- k3 x, TIPC-2581 Support
/ [$ X8 B3 t+ R) rGerber X2 Support
& o* K! g7 I1 T" _3 j7 hIDX Support
Exporting to IDF in Unicode Format
True Variants Enhancements
! x  c0 |9 D  [3 P2 f9 z6 u3 ]& `1 DOutput Job Editor Enhancements
, l+ N- i8 r* w" O$ m$ mUpgraded Duplicate UID Correction
( F+ }- L# q% U: J6 Q6 j  }System and Performance Enhancements
Vault Connection Enhancements
Ability to Control Parameter Visibility for Vault Components
Parameter List Templates
! K; e7 F: b) X6 O4 T+ X- e: ^Parameter-based Name Templates
Vivado toolchain improvements
Intuitive Import and Export
( U0 h3 u/ J; x' `  B% e: H$ rVersion 15.0.7
1 Q* m6 }/ L& ^6 ]! o4 lBuild: 36915 Date:17 November 2014
1015 Support for high DPI screens using oversized fonts has been reviewed and improved.
- J3 K1 E% I) t3 n1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,
. F# `- T! y3 `5 fwhen layers are shuffled out of default order.
) J3 @0 e8 ?: T; U$ X* R  l1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes.
( X8 @( z. a& [1 l7 x! E2 e1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,
this no longer occurs.
6 y6 y+ V7 w& H( q( S" i& `( w1408 IDF export now includes an option to export in Unicode format.
- ~* R- u1 O3 B# s1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain
8 C6 `' J7 O: X6 ]/ F4 f" ?, b* ]outputs not generating correctly, this has been fixed.
. d9 Q9 Y: U$ p9 F6 ?+ W! x  l2613 A Vault Content Cart can now target regular folders.
2 F$ m" g0 [2 \, p$ Z' F, b9 i2816 It is now possible to define a CmpLib Component Naming scheme using a template with
. B' K  P3 |- S( a4 Dvalues from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.
2817
# \0 B- P0 j' y6 C, i. G  c8 zThe CmpLib editor now supports the addition of new parameters via customizable parameter
list templates. Click the Required Models/Parameters Add button to access the templates
(samples are stored in the \Templates folder).
% w- r$ I# Z, Q' g1 ^2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages
panel. Existing duplicate UIDs are also automatically resolved during document loading.
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel.
) F* f; C  a' Y3 K4 _6 E3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is
8 W' N: v& J6 e3 genabled.
1 \, |9 c5 t, }+ s. _/ q3008
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not
- _- \1 ~2 W: W& p9 O: H5 sall Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable
! `# \* i  t# g# Xright-click commands & shortcuts (select the container first).
) }, h7 S1 r, v8 U& N8 k3026 Import and Export options are now directly accessible via the Files menu. Save As commands
0 S3 R1 @8 G7 Q6 _8 \) d$ Qare now used exclusively for Altium file formats. (BC:1812, BC:2731 partial)
# K1 B( l+ ~5 m" O# O6 P" C3033 Gerber X2 is now available as an output format. It supports output generation via the PCB
editor Fabrication Outputs menu, or via an OutputJob.
3035
1 ^4 Y3 Q. g6 h; \  U& A  q& uIPC-2581B is now available as an output format. Install the extension and generate output via
& N1 }7 I  O" b; Qthe PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from
http://www.ipc2581.com/index.php/ipc-2581-files
' s- p0 B9 L" j$ I3081 The Vaults panel now supports changing the column visibility and order. These changes,
along with panel-section resize actions are retained between sessions.
: C- z6 O! q& N( J8 p5 _* @3143 Timeout errors after releasing project documents to a Vault have been fixed.
3188 OutputJobs now support using a slash character in the Output Container Name.
3189
7 w( M% {* W& g6 }It is now possible to pre-configure the display state of Vault component parameters, via the
0 M; u3 I' w. O% `Vault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog
$ S* s5 Q* l" R. r' r(add a Vault as a Library).
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the
screen.
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the
likelihood of a netlist change.
3227 Schematic dragging has been further developed to improve object handling and the quality of
, |: n6 U0 s0 s5 w3 Nthe result, and reduce the likelihood of a netlist change.
3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse
& X* H2 X: F( ~button down as you click, until the vertex disappears.
3251 Releasing projects to the vault with file-locking being enabled works correctly now
1 l# Z' j- x3 ~8 n" s3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C
and Ctrl+V.
+ _2 Q+ s; V  r  z+ T4 ?3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be
cleared, the BOM saved, closed and re-opened, and the filters re-defined.
3338 Multi-net routing no longer creates a clearance violation at corners when the Converge
shortcut (C) is pressed.
3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink
) _% `  Q, A0 [4 C7 `6 y5 ^now opens the target web page correctly.
3357 Teardrop removal speed has been improved.
3381 Second click to select an individual segment in a schematic wire now works correctly.
3412 The issue with not being able to close documents having "=" character in their name has
% Z! \& D9 V$ w) {+ M' _been resolved
3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net
objects, including vias.
3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs.
0 c8 |" s. l0 p( ]# K! h3425 Update from Libraries now correctly preserves existing location and orientation of parameter
strings.
3437 2D and 3D PCB view orientations are now completely separate, each retains the previous
# u- ^! ^0 D* h1 Z/ s1 U& Borientation and zoom when switching between the views.
, K, O4 U& V5 ^: \0 N+ [3441
8 _8 _/ B( D( m5 h. e! H. qPin-pairs have been added to the PCB editor, delivering the ability to define the path and
constraints for a signal to travel between a source and destination, through termination
components and y-splits.
3442 The import of complex arc shapes from AutoCAD has been improved.
3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into
a PCB document (Place В» Object from File).
, `0 `. G9 U0 |2 Y3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA
# [0 O3 y2 C  E6 G( s& ^- Place and Route preference settings.
3457 Split plane editing could occasionally cause an exception, this no longer occurs.
3459
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire
, E1 P! G- l  Y0 h' _: z; `segment is automatically added between every pin and the wire being dragged. This fix
restores previous schematic editing behavior.
3477 Schematic library editor, the Parameter Manager now supports editing parameters across
* F1 U  Z" F! G' fmultiple selected components.
& W; c8 o4 N/ W( E3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting
7 c. t) F( n! c! x( N9 R! f+ R& Aedges) in the schematic editor.
- o4 h. s" |0 p3 i6 e3495 PCB component fanout now functions correctly when there is an unpoured polygon under the
component.
6 B9 b5 f! W# b" W/ f3497 Click and drag to move a group of selected objects now be functions correctly.
  z+ {+ p6 P) H" _: I* W1 J3498 An exception that occurred during import of specific DxDesigner projects has been resolved.
3514 PCB Step model import has been enhanced with better support for curved shapes.
3521 Fileless editing of an external SIM model no longer generates an AV.
3528 AVS 1.1 is now supported by Altium Designer 14.3.
: u# _* l, b7 e" S3529 Component pads placed on a signal layer other than top or bottom could not be edited in
( O/ I, y  ~! L% e4 |) Ocertain layer-stack configurations, this no longer occurs.
: {4 K% o" ?3 M5 r5 @3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list.
3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.
% C5 i, L6 [: ~2 ^- B' }, A3551 Schematic auto-junctions now size correctly regardless of the wire width.
3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed
correctly in the Components mode of the PCB Panel.
2 a# Q# o' Y/ ^/ R3560 It is now possible to connect to an SVN repository with a user name containing the @
" ?! C% F* K) ?5 a% Fcharacter.
3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.
3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.
' `4 W- r+ J4 l! a3568 The Vaults panel now shows the Note data from the correct Lifecycle state.
3576 PDF generated by running OutputJob can be opened directly from OutputJob document
3577 Simulation model pin mapping now works correctly in the CmpLib editor.
3 b; P, [. q8 I1 B! }6 h# V* a$ S3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this
has been resolved.
. B3 F6 J9 o* l3592 The path tracing routines used for creating a polygon from selected primitives have been
improved, to better handle small objects and multiple paths.
3598 From-To panel now shows length taking via heights into account
* a, ^3 ]4 s7 P* A4 X2 D3611 The schematic Place Wire command now correctly retains the corner mode used in the
. z( x5 T/ f8 \previous wire placement.
3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues
9 u: l5 B/ N, m7 ^2 Y9 F$ K3633 Updating Altium Designer from an NIS no longer requires a current Portal connection.
: U3 S8 Q# K8 C3 _4 m% L5 [* F. ]3634 "Access denied" error when installing an update from NIS has been resolved
. [5 ?) m1 y2 L' L; B3640 Support for rectangular-shaped pad holes has been added
3664 PCB exception while re-building a net to an arc center point in a specific design no longer
6 j- q) o& ]) b$ b4 n9 Toccurs.
3 d9 b! h6 p8 L( b$ r/ _, }' s3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped
% X1 k7 g0 a' \8 V7 a4 a2 I3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)
' _9 S5 _. T) ]! J; g3692 Pads with rotated square holes no longer show copper still being present after running the
/ _* B7 e6 D7 ]# ^' x1 ~Remove Unused Pad Shape command.
3695 GOST specific documents can now be generated in BOM Report outputs
: T/ ?) s2 X; N$ w3707 "No model link found for component" error no longer occurs while editing old cmplib files
3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.
3721 Occasional exceptions during a print preview no longer occur.
3722 Under certain conditions changes made in the Variant Management dialog could cause an
8 T% {7 g6 M+ I  q( R# l3 }3 ^exception, this no longer occurs.
. o& O& P! p8 L: n! h3729 The Variant Management dialog now immediately reflects changes to components, such as
clearing or choosing an Alternate Part, improving usability.
5 [2 X3 r8 s2 U  U, [% b) b3732 The Edit action is now available when right-clicking in the Search results panel in the
/ u: J4 B5 u) c4 r2 \: `: R+ b1 r% iVaultExplorer
3736 Fixed error while releasing Vault revisions with extra long file and path names
, h. R: E  g( Z3737 Changes to Comment and Description are no longer lost during component release from the
CmpLib editor
; G6 s1 n3 y1 }/ r- a3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel
3 F; r: Z* v. b/ z% _* [3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads
" e5 g9 m. O" g$ t( ^; P& ]0 k3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from
the schematic.
3774 Under certain conditions, schematic compile masks did not exclude components or net
5 D; g$ A: Z6 A" ^' u5 ^# Kobjects underneath them, this has been resolved.
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option
# w' G* I  G6 k& q% nenabled was very slow, this has been optimized.
* @; @) @- u6 g6 t3779 Improved performance of selection and zooming in Schematic in comparison with 14.3
3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical
, V1 O% @& ~+ F3 Rrepresentation out of sync with the tabular layer detail region, this has been resolved.
3787 The "rint as a single job" option in Output Job File documents now properly combines the
* N; R) y' v- {' n8 Cseparate documents to a single print output
3789
. {; v% v. n1 n9 ~2 B7 iPCB re-annotation on a variant design with not-fitted parts could result in the varied parts
& X* }1 u0 b9 A) {# \1 Vbecoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses
3 j, h/ ?% b6 }& `/ y( p0 |alternate parts with different footprints is not yet supported.
) s1 o0 p6 T4 T3 V- n! J3792 STEP models from Inventor 2014 are now loaded without errors
/ M) C' E: d; P! W* G+ z3800 Variant PCB drawing options have been updated to make it easier to understand how Not
+ v, J+ j. D5 Y: b, ]2 ^Fitted components are displayed.
3809 It is now possible to specify different values for solder mask expansions for top and bottom
0 @& ]8 g0 f5 B7 h6 [) y  ]0 Vlayers
' q/ H/ _3 f0 k$ U. c: O& A3834 Empty surface constructs are now suppressed in ODB++ fabrication output.
3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E
. Q! o+ r+ w5 c$ Y4 o2 |" ?  Fpin counts, allowing packages with any even number of pins to be created.
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter
0 U* W: ^5 ?# ]/ h) ~8 pthan the rest, this no longer occurs.
& a% m( N  M8 J6 r3 U3841 Reset All command added to the Variant Manager, use this to restore all parameters to
/ Z' N( B- S# R- w) ~alternate or base component values.
3844 The issue resulting in "I/O error 103" error message when some of the project files are
3 A: J& O* z$ p, p6 U4 }0 Tread-only has been resolved
2 G% f: P9 e) M5 ^4 s2 N9 ?* j3845 The speed of updating from libraries or a database has been improved for designs that
7 ?' j2 F( q) _2 `7 s3 q0 hinclude variants using alternate parts.
* u; c0 y2 H1 k; D3849 In certain circumstances a component would still be shown as varied after resetting
+ D$ ^- A9 {% Eparameter variations, this has been resolved.
3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified
concept)
3875 The Vaults panel right-click menus now display correctly when Display scaling is being used.
3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this
$ }( }6 j3 ?" D8 F) I" `+ u; [  H. uno longer occurs.
3888 Crash reports can now be send from behind a proxy
" R; N; I' l, u. k3889 Simulation Waveform viewer print preview issue has been fixed.
- P, N, w7 U+ o) b0 y3900 Class generation settings are now stored for device sheets (BC:3840)
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on
designs with a large number of classes.
3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the
" f, r0 V3 l' T8 a& O! y: ^* t4 b# ]embedded boards had drill holes, this has been resolved.
3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw
quickly and also correctly display the fill color.
4005 Variant designs that include alternate parts with different footprints can now be re-annotated
in the PCB editor.
% @. V2 L) i/ Z- X) @! V4016 PCB DRC now supports stacked alternate parts in a variant-based design.
4049 Signal length column was added to Nets panel (this length is being calculated using more
precise xSignal engine)
' Y+ ^4 f" Q, }$ J4062 All extensions within a group can now be installed in a single action.
+ u% o4 n" d" z6 j1 \1 v4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer
occurs.
4076 Modified Polygon rule support check for shelved polygons
4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for
all possible layer configurations.
2 k7 \% c, a$ L2 H4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of
Display Style entries when Windows display scaling is being used.
4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the
command, this no longer happens.
% ?  v* S% f8 |- [: h+ a4111 With a specific combination of preferences, placing a component from the schematic libraries
panel could cause Altium Designer to crash, this no longer occurs.
4121 After configuring components for pin swapping, it is no longer necessary for the designer to
manually recompile the design to make those swap configurations available.
4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper
rule check configurations.
% ?$ z* S  M3 S3 K4215 When a polygon is shelved, connections created by the polygon are maintained internally so
the connection lines will not be displayed.
7 a' i2 e" f1 Q+ R- z4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later
- O0 {1 D6 D/ S/ `# m( QSource URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0

+ r4 q# o$ i7 w0 @! ]

Maxim

以前是一个偏执狂，一有更新就下载；
4 d% ?7 Y! z/ P现在我依然在用ad sumer 9；
* B6 b+ U: \+ p3 o' s9 |* G7 U- ?本来更新的目的是消除已有的Bug，现在的更新是消掉10个Bug，带来100个Bug！

xuser

回复看看！

lw3530

目前在用9.4版本 14.3.13正在下载.... protel系列用过99、2004、08、09.3、09.4和短暂试用过10.几版本的忘记了

lw3530

用AD除了对封装数量较多的库修改保存比较卡不满意外，还有就是偶尔软件会崩溃。等最新版本出来了再试试，希望体积不要太大！

lw3530

安装试用了下AD15，第一感觉就是吃资源确实厉害，PCB里缩放已经感觉到有延迟了，跑AD9相当顺畅...看来我的机器是跑不起AD15了

jamesytl

加泪滴后，保存到低版本，泪滴自动消掉

yanggo

主要自己使用稳定就不要随便更新了。不尝鲜了，等你们。

好人好梦

用的ADsummer09，用得很好呀？干嘛还要升级，只要不出什么故障，用着顺手，管他的，更新的软件占内存越来越大，所以也不想更新

joeling

看看是否實用...

jamesytl

09有SUMMER和WINTER两个版本，哪个好
" ]( }8 c9 ?  Y& B1 t; k( V  e6 Q

sikixu

哪里可以下载？