! G% R- M; E3 W3 |4 K0 V {+ d% s) _2 pAltiumDesigner15.0.7出来了！ ) ]* {# ?7 u0 Y2 A我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，- r6 x8 ^( a7 w& Z
或者说是，你是在修Bug么？？3 ^) w" A6 h# n- f! u4 n7 t! o1 v
貌似AD14就一直是Bug不断，这次AD15估计也一样，不过， 5 \. H3 G% M; j& `6 H1 _貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。7 a; y$ I/ k! q/ M5 q% K
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？, m' ^; G# B7 J x* h9 d) ^- W
或者说，你会更新到AltiumDesigner15版本么？ 0 C5 }7 H# y2 v# U& I" Y 0 y2 Q$ u; v w3 fRelease Notes for Altium Designer Version 15.0 # h) u2 Q, t$ C; MModified by Nikolay Ponomarenko on 17-Nov-2014' i$ o3 e5 Z% x+ u" R# U Key feature highlights 1 {+ T2 j" t( g6 h5 p1 CHigh Speed Design with xSignals 3 c' {$ l) u- A) S7 H+ VSolder Mask Expansion Enhancements 6 @7 [6 V* j4 e3 b+ k) o: O& WAccurate Route Length Calculation6 ]' h5 P/ [* J* y6 X; ] Polygon Enhancements O9 p7 B6 L1 jOLE Object Support in PCB Documents& ~) {2 o }# Y Support for Rectangular Pad Holes2 k4 g$ m, j0 d- e5 u7 g4 E Separate 2D & 3D View Orientations) _% o9 V- M7 @. t7 l' k IPC-2581 Support - E! V+ x$ r. V) DGerber X2 Support ! t$ W: A/ z8 ?IDX Support: r4 k" m- N8 b1 d3 u2 \2 d Exporting to IDF in Unicode Format8 J" n: S7 t& f/ B% Y( M" z- n- W* { True Variants Enhancements5 c2 q9 \9 A4 h: @% c8 j. [ Output Job Editor Enhancements % e; ~, `% t( s5 N# y" X! P! qUpgraded Duplicate UID Correction / K8 C! [& B' z7 w8 b! z7 _System and Performance Enhancements+ s$ q2 D4 ]/ J! j, e9 }) y Vault Connection Enhancements 6 ~5 `2 e6 c/ [: X% J) EAbility to Control Parameter Visibility for Vault Components* Q6 t, t: a3 t; a, Y7 H/ u Parameter List Templates / K- ~- i) A! P# M! `1 kParameter-based Name Templates1 ^2 b) V1 g& j- L9 @# P e4 ?2 s: u: y+ y Vivado toolchain improvements % }( r9 G9 ^9 x# ~Intuitive Import and Export " o- ?1 D& ~& C" R6 o2 i$ |Version 15.0.7 6 A+ `+ A, m- Y" @: E5 ~8 C: JBuild: 36915 Date:17 November 2014 w7 @( @! F$ M( }+ V' U1015 Support for high DPI screens using oversized fonts has been reviewed and improved. 4 G# p% {. C6 X* N4 M, x. f" i1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes, 8 j& r/ ~3 r r1 {when layers are shuffled out of default order. & R' Z/ {% A1 F& `/ X1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes. , `* M* N6 [6 B1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,/ R. }$ O+ G9 S( E$ J
this no longer occurs. : ?% h* D$ ]- C" y! {' H, n! j1408 IDF export now includes an option to export in Unicode format.; f. o( B$ V% G& Z
1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain( U4 [) b2 [7 E
outputs not generating correctly, this has been fixed. ) j2 V* ^# m3 T8 p2613 A Vault Content Cart can now target regular folders. 2 K: x5 I2 D% j. T8 _2816 It is now possible to define a CmpLib Component Naming scheme using a template with- K8 m& L% u( D5 E# R1 R
values from any parameter, for example CMP-[Value]-[PackageReference]-{0001}. # t% o* x; Y& j2 q8 i r3 L/ ~2817' Z) ~* i/ W" w- m6 A
The CmpLib editor now supports the addition of new parameters via customizable parameter2 P" E3 S9 v$ F8 S; ^$ i
list templates. Click the Required Models/Parameters Add button to access the templates; i$ s( N* E/ N4 k% ^# k( Q2 ^( b
(samples are stored in the \Templates folder).9 z8 P+ D* A% s8 M2 n
2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages9 a F8 O0 a. t: Y7 Y0 ~% B2 w6 {/ v3 n( M
panel. Existing duplicate UIDs are also automatically resolved during document loading.0 z: d# ~/ t) k) {' G
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel. + c9 L! {2 h* i# `! g- S+ t$ s# y3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is 6 E: o/ r. U- U/ genabled. - \8 n! Y" `/ C' k1 b3008 9 R j! L, ?8 h* ]4 O! i0 B0 iOutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not 6 I1 R2 r1 f$ M0 l/ Oall Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable 7 B. _" x; ~5 h: |) M! Y7 ?2 V+ `right-click commands & shortcuts (select the container first).! i8 F( d0 |/ _" Q; W4 N0 {
3026 Import and Export options are now directly accessible via the Files menu. Save As commands 3 \2 A8 y/ v! n3 ^0 Hare now used exclusively for Altium file formats. (BC:1812, BC:2731 partial) 1 R5 H/ ]/ w. A( P8 H3033 Gerber X2 is now available as an output format. It supports output generation via the PCB 7 k+ \: h) j( Leditor Fabrication Outputs menu, or via an OutputJob. ! x: T' O7 V) a9 h3035 0 j$ p8 G9 m/ d/ LIPC-2581B is now available as an output format. Install the extension and generate output via) x5 `* X8 g4 h& t
the PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from ! s0 O. c' x* v- O4 Q8 I: jhttp://www.ipc2581.com/index.php/ipc-2581-files% t6 ?% K) R! I4 n* ~4 p1 [: F
3081 The Vaults panel now supports changing the column visibility and order. These changes,! n5 |0 |+ h* _3 ]
along with panel-section resize actions are retained between sessions. : _+ L9 X/ W- G1 A: ~3143 Timeout errors after releasing project documents to a Vault have been fixed. ! d& V5 ?+ @, C, I) L3188 OutputJobs now support using a slash character in the Output Container Name.$ D$ i9 Z# n- \) I
31895 l: z8 o9 V# S
It is now possible to pre-configure the display state of Vault component parameters, via the8 @2 o- j# Z: G3 }8 \) `$ b. q! A
Vault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog) @# `4 c* o9 e' z- a4 F
(add a Vault as a Library).# |" T- I0 ?; G9 \/ w* P0 M. @
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the+ k% o3 i9 d" N/ l4 J0 ]
screen.. H( |3 R- f9 r4 Y5 L& W( Z' \
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the1 j) f: {/ Y, s; L( V: x+ W8 d: ?
likelihood of a netlist change.' T9 Y: u) e- m% K$ o
3227 Schematic dragging has been further developed to improve object handling and the quality of 3 o5 f- E3 p/ kthe result, and reduce the likelihood of a netlist change. ! f2 u+ T% ~8 |4 b3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse : ^$ c6 [! j8 H! m) nbutton down as you click, until the vertex disappears. " ?9 k! C: T+ }. {) g) ]# _; p) d3251 Releasing projects to the vault with file-locking being enabled works correctly now 6 P" ?% d( ]2 ~9 F3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C6 a7 \; L5 T* g( M1 z! w
and Ctrl+V.3 d% ~! t5 I" ~: E! c
3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be ( k8 N$ T1 S4 }2 Fcleared, the BOM saved, closed and re-opened, and the filters re-defined.$ X9 S% g9 [6 C
3338 Multi-net routing no longer creates a clearance violation at corners when the Converge ' E) m6 S5 c6 f/ \shortcut (C) is pressed. 9 Z6 a/ T' E/ b" X% h( r4 a3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink4 l, ~1 Q2 v( f$ o. @2 t
now opens the target web page correctly.8 ^- m7 [' z0 G1 L
3357 Teardrop removal speed has been improved. 4 S& l5 R, H4 \3 }3381 Second click to select an individual segment in a schematic wire now works correctly. $ z4 @) W3 A0 B' N- q3412 The issue with not being able to close documents having "=" character in their name has ; y2 F+ v7 H8 U5 x4 fbeen resolved6 z. a$ ^7 c1 s( { F
3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net6 C' Y( V) M5 s. u5 V
objects, including vias. & @0 q+ q* V3 y! p( R2 u2 X3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs.! F- t8 I1 T. A- F2 S
3425 Update from Libraries now correctly preserves existing location and orientation of parameter 0 d+ m. K- C7 Astrings. 9 d9 c- S$ {3 r' r7 V8 t3437 2D and 3D PCB view orientations are now completely separate, each retains the previous2 q- y/ q0 H- x
orientation and zoom when switching between the views. $ z6 }! ?- X& i6 C! K. t) ~8 q34411 J) i# ~) t( o$ s+ `- Q
Pin-pairs have been added to the PCB editor, delivering the ability to define the path and& g6 V5 a, f" L- M4 u2 a% c" J1 ^
constraints for a signal to travel between a source and destination, through termination G8 d a+ c$ U- @! Ocomponents and y-splits.2 q1 z9 D: M8 L: K) ]8 B6 b6 m
3442 The import of complex arc shapes from AutoCAD has been improved.! k E6 H5 t- i( ?
3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into; O: P$ ` J+ v' V/ W3 T9 {
a PCB document (Place В» Object from File). % y$ C2 R% H+ w4 M3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA % N, N, g, h+ j/ {: k2 ^2 z- Place and Route preference settings./ q$ F* f2 H8 y
3457 Split plane editing could occasionally cause an exception, this no longer occurs. . ~, S: { ^; X1 K [3459& A+ A; V3 ]' R3 x( M/ ~& k( ]
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire ! g4 R7 X/ R" i3 ^+ @0 O7 S) }segment is automatically added between every pin and the wire being dragged. This fix$ ~2 X7 l* _8 \" E0 _2 C- r, M
restores previous schematic editing behavior. ; p1 e9 Z4 [/ l N' d5 y6 c4 h' W7 f3477 Schematic library editor, the Parameter Manager now supports editing parameters across4 V4 F! m5 Q6 b u$ A. U2 \
multiple selected components.- l: H+ {/ _# Y8 V1 ~$ |% i. c
3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting $ h. {- d; x: W: G$ Z. eedges) in the schematic editor.0 `6 T6 }& R' j* E
3495 PCB component fanout now functions correctly when there is an unpoured polygon under the1 P( l5 `* I: u" p2 _
component.; s7 K0 P q6 d; A% Z& N/ I. V
3497 Click and drag to move a group of selected objects now be functions correctly.6 p, f* Q3 o' d, X- O
3498 An exception that occurred during import of specific DxDesigner projects has been resolved. $ ~7 O! H3 ]9 C) |" w3514 PCB Step model import has been enhanced with better support for curved shapes. ' z& N- b$ y Y0 P+ U3521 Fileless editing of an external SIM model no longer generates an AV.7 [/ K/ q# Q3 h5 e
3528 AVS 1.1 is now supported by Altium Designer 14.3. ) w; A* x: Q8 O" g8 C3529 Component pads placed on a signal layer other than top or bottom could not be edited in U4 R8 K* i+ q* N- a3 A
certain layer-stack configurations, this no longer occurs., P+ L1 R2 F$ v
3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list.: W9 Y" L! j+ C( \7 _9 J" s
3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.- V1 I8 p7 V& u
3551 Schematic auto-junctions now size correctly regardless of the wire width.2 ^- ]& e3 t% `8 ^' L" N3 ^/ b3 h. e
3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed; s9 T% z0 A. l+ D2 |. i
correctly in the Components mode of the PCB Panel.; ?2 O# @# x+ b) K5 N$ j$ c
3560 It is now possible to connect to an SVN repository with a user name containing the @ 1 v( i6 |4 B+ N3 w& B% bcharacter. . Y- J: G4 h# C$ m k9 [% v- v3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.1 X1 y! B7 t, T; B
3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color. ( i9 }4 |! e- o' ]3568 The Vaults panel now shows the Note data from the correct Lifecycle state. # D4 }2 ]: k$ x' z2 u; o3576 PDF generated by running OutputJob can be opened directly from OutputJob document. @" X2 h. L4 q7 ]! T4 m
3577 Simulation model pin mapping now works correctly in the CmpLib editor.5 Y7 w5 U, C1 K
3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this0 {2 N* W' a( Q) k6 b( n. U
has been resolved. 1 {+ k2 `. S1 @. h- K3592 The path tracing routines used for creating a polygon from selected primitives have been & _/ m( D H/ W6 ^- P; M0 G$ g+ ^improved, to better handle small objects and multiple paths. 9 n0 T- y, y5 r. j3598 From-To panel now shows length taking via heights into account ) ]( I% [- ?, H) x P ?! l3611 The schematic Place Wire command now correctly retains the corner mode used in the + F" e' w5 d* Z; l$ K, V" [- [- | wprevious wire placement. * J- ~* U7 ~, v5 v3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues 5 S* i4 t' x; S) u3633 Updating Altium Designer from an NIS no longer requires a current Portal connection. $ u5 |5 w$ n4 K3634 "Access denied" error when installing an update from NIS has been resolved% \0 X) d0 @0 k* P5 g3 |/ J1 n
3640 Support for rectangular-shaped pad holes has been added 6 j2 Z+ @$ A" u- w7 C/ I3664 PCB exception while re-building a net to an arc center point in a specific design no longer( r& A% ]& x4 ?; g& B5 y
occurs. 5 N# y5 `4 O2 }+ Q( Z3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped / m* D. w2 S, g8 L/ T; |1 F- R3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664) u0 E5 E9 V3 M/ ?
3692 Pads with rotated square holes no longer show copper still being present after running the2 n1 a2 T' a* x
Remove Unused Pad Shape command. 8 a5 D$ W/ l ]) q# [2 v+ M3695 GOST specific documents can now be generated in BOM Report outputs ' j" A1 w7 T9 v* E% Z5 [3707 "No model link found for component" error no longer occurs while editing old cmplib files # A( |6 g- G6 L' I- M5 G n; c3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.- Z5 a6 o }& d1 u
3721 Occasional exceptions during a print preview no longer occur. * j- Z) p5 u* x. W3722 Under certain conditions changes made in the Variant Management dialog could cause an $ S0 p1 L1 V% A ]6 A4 Cexception, this no longer occurs.' S1 h; ~/ Q h7 ^6 F9 x
3729 The Variant Management dialog now immediately reflects changes to components, such as5 i0 J- [8 U b! {
clearing or choosing an Alternate Part, improving usability.( E2 {/ b4 s+ t; p
3732 The Edit action is now available when right-clicking in the Search results panel in the ' _! r. k( _1 S3 b; _! o7 ?VaultExplorer 2 [* d" `/ k$ h% I3736 Fixed error while releasing Vault revisions with extra long file and path names 0 U1 p# Y0 f2 T0 k/ H! }3737 Changes to Comment and Description are no longer lost during component release from the2 v- j a9 @6 p9 ]# N$ _7 g
CmpLib editor ( v% l0 N4 `5 H5 R3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel ) J5 ?; N% W3 ]3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads J6 L; j! l" F Z3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from 0 z0 j/ G c5 [9 F" I* wthe schematic. 4 r3 ]$ V/ J8 k( v Q0 g& t3774 Under certain conditions, schematic compile masks did not exclude components or net2 z% U2 u9 y5 ^; a7 r
objects underneath them, this has been resolved.$ g5 n2 v4 i0 A, m( ?
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option ! D4 U) m1 @# Tenabled was very slow, this has been optimized." t4 Q8 t$ B( b- v8 O# ?' c& K+ m
3779 Improved performance of selection and zooming in Schematic in comparison with 14.3 ; C8 v! @5 t4 s+ Q j; r& B1 _: u3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical4 e$ f7 ^6 O9 x6 q" i
representation out of sync with the tabular layer detail region, this has been resolved. 7 N3 {8 U9 w* Y9 a. l M3787 The "rint as a single job" option in Output Job File documents now properly combines the$ @! Q- B- V. y* N9 Y+ b/ b: D
separate documents to a single print output& k: ?& _6 \9 x% J" c; v2 q, q; q7 S
3789% `' h+ k. k! ]3 `; T
PCB re-annotation on a variant design with not-fitted parts could result in the varied parts' m) c( r1 C% x" ]0 Y) i7 i/ n
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses 9 Y. R$ }0 ]. Q ~0 Jalternate parts with different footprints is not yet supported., P! b' K1 B3 k9 o; l$ I9 X
3792 STEP models from Inventor 2014 are now loaded without errors - {: ?: {) F1 [6 y3800 Variant PCB drawing options have been updated to make it easier to understand how Not 6 _6 E8 m. G% S3 o0 NFitted components are displayed. 7 e8 Z/ J4 ` [) [6 L8 z3809 It is now possible to specify different values for solder mask expansions for top and bottom% Y% P9 U- a+ R3 K0 G* P
layers 6 @1 n; O+ x4 U+ m2 w" L- v3834 Empty surface constructs are now suppressed in ODB++ fabrication output.# A7 I" a* B/ c9 L# P
3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E ! c& f- X C z/ y2 J: ` J. Spin counts, allowing packages with any even number of pins to be created.) D' ^8 f6 Z! [
3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter ; w; ~2 ~% K# ?& I* t( N* X" Wthan the rest, this no longer occurs.5 ^" m2 Y! P; w, B. b
3841 Reset All command added to the Variant Manager, use this to restore all parameters to- t$ E' w' d& @- O* i
alternate or base component values.2 f% R$ x8 j3 ]* U$ \* q( W
3844 The issue resulting in "I/O error 103" error message when some of the project files are7 h$ j4 L, i" t$ F8 _1 F
read-only has been resolved3 g# Y ^2 c# `3 ^% J
3845 The speed of updating from libraries or a database has been improved for designs that ) @3 t- W( U- |5 p* Winclude variants using alternate parts.% V+ i5 h; h8 w3 D- ?& k J
3849 In certain circumstances a component would still be shown as varied after resetting: d. @4 X$ Q' ?) @: v# M' P
parameter variations, this has been resolved. , p) G# l8 U6 z3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified& z2 s6 y1 Z# x4 I g( t
concept)7 ` V! e) W& R7 m
3875 The Vaults panel right-click menus now display correctly when Display scaling is being used. _! m# E9 K' W8 Y% i) Q
3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this8 u7 Z+ t6 P& T2 p; W4 m$ i8 T# S
no longer occurs.3 p G, j! p( X8 H* ]* b2 c( {
3888 Crash reports can now be send from behind a proxy+ w2 t m+ X+ m' S
3889 Simulation Waveform viewer print preview issue has been fixed.- F1 Z4 P/ e* N' G# t H
3900 Class generation settings are now stored for device sheets (BC:3840)6 ^4 E; X& f1 |& J1 u- D8 ^* W% |9 z& |
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on; q9 Q" E# |: E( {' c! w+ [
designs with a large number of classes. " U% X4 R7 K/ t- U1 S; S5 ~3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the # |- l3 ^0 c4 F+ {& hembedded boards had drill holes, this has been resolved. 8 h) k9 l- ~. W) j$ C3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw' S& Q" u: V/ t: ]4 Y4 m1 |
quickly and also correctly display the fill color. $ P& S4 g% I. w1 }/ N0 k1 x4 o4005 Variant designs that include alternate parts with different footprints can now be re-annotated ' P+ |* d) Z o+ Kin the PCB editor.1 d) R6 B" Z0 x. I! w0 b
4016 PCB DRC now supports stacked alternate parts in a variant-based design. 4 q, @& g; v/ \, n0 ]0 A4049 Signal length column was added to Nets panel (this length is being calculated using more 8 U/ \ q, }) p$ [; V! X1 s& j( qprecise xSignal engine) ! r; X9 J( U! `" p4062 All extensions within a group can now be installed in a single action./ p8 ?- G4 s: Z. c5 e
4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer 0 T- m. t8 r+ m9 m4 eoccurs.; B5 o; o5 {! Q e! N
4076 Modified Polygon rule support check for shelved polygons4 T" g2 B+ ~9 r
4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for M$ o, d/ B ~* k0 `( w- _
all possible layer configurations. 4 |2 `8 A$ d3 |+ P* [7 U4 d4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of$ ?& ]7 |9 N* i
Display Style entries when Windows display scaling is being used.: h% v4 M' _$ V- z" T: K
4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the. X- S$ S. X0 n2 g& o8 M$ n6 g
command, this no longer happens.+ G3 s5 N. V3 S. i# n+ G) [" {, Z
4111 With a specific combination of preferences, placing a component from the schematic libraries 4 O, b! _) T% x7 o2 P' P2 U0 @panel could cause Altium Designer to crash, this no longer occurs.+ [' W, G" P" u/ r {$ U" }
4121 After configuring components for pin swapping, it is no longer necessary for the designer to / R4 y! P, E% W0 xmanually recompile the design to make those swap configurations available. " H! u& k8 W% q& [8 [4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file.# \& m3 C7 B/ j @+ h4 X9 z
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper7 `% J/ Z3 w3 w9 j. l
rule check configurations.1 M1 q/ {# o, S4 v* {
4215 When a polygon is shelved, connections created by the polygon are maintained internally so 1 C. i3 F. z% Nthe connection lines will not be displayed. $ {: i, Q, {" J. l% a1 P2 O9 P4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later' ~1 Y" C: {7 Y+ j" x) m Source URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.02 W# f5 H. p- n) G3 z+ P4 F
7 k y* m% q) {9 d
- Y, q7 h! i+ s9 V1 A) z! c 作者: Maxim 时间: 2014-11-21 21:42
以前是一个偏执狂，一有更新就下载；; [$ v* Q4 B% {. } [( f
现在我依然在用ad sumer 9； # I" d5 P5 K1 v3 y- k! e' d. i本来更新的目的是消除已有的Bug，现在的更新是消掉10个Bug，带来100个Bug！作者: xuser 时间: 2014-11-26 10:22
回复看看！作者: lw3530 时间: 2014-11-26 12:47
目前在用9.4版本 14.3.13正在下载.... protel系列用过99、2004、08、09.3、09.4和短暂试用过10.几版本的忘记了作者: lw3530 时间: 2014-11-26 12:50
用AD除了对封装数量较多的库修改保存比较卡不满意外，还有就是偶尔软件会崩溃。等最新版本出来了再试试，希望体积不要太大！作者: lw3530 时间: 2014-11-26 22:34
安装试用了下AD15，第一感觉就是吃资源确实厉害，PCB里缩放已经感觉到有延迟了，跑AD9相当顺畅...看来我的机器是跑不起AD15了作者: jamesytl 时间: 2014-11-27 12:08
加泪滴后，保存到低版本，泪滴自动消掉作者: yanggo 时间: 2014-11-27 14:45
主要自己使用稳定就不要随便更新了。不尝鲜了，等你们。作者: 好人好梦 时间: 2014-11-27 16:22
用的ADsummer09，用得很好呀？干嘛还要升级，只要不出什么故障，用着顺手，管他的，更新的软件占内存越来越大，所以也不想更新作者: joeling 时间: 2015-2-25 23:23
看看是否實用...作者: jamesytl 时间: 2015-2-27 14:43
09有SUMMER和WINTER两个版本，哪个好5 d: u) v$ t0 u9 i' C 作者: sikixu 时间: 2016-1-19 16:26
哪里可以下载？
才看到网友说AD15出来了，然后刷微博就看到了这个。。。
rint as a single job" option in Output Job File documents now properly combines the$ @! Q- B- V. y* N9 Y+ b/ b: D