创建Netlist出现错误,请帮忙看一下

lxwuming

我从orCAD to Allegro时,出现错误.
Nettev 如下,请帮忙看看哪地方出了问题..
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Cadence Design Systems, Inc. netrev 15.7 Tue Aug 19 15:49:19 2008
* p6 [) u) K" |' i) {(C) Copyright 2002 Cadence Design Systems, Inc.
& X& H7 C9 ~1 ?: t9 o------ Directives ------
RIPUP_ETCH FALSE;
7 Y" W7 Y$ H# ]RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
' @8 B" N, b/ ?' y  y1 cSCHEMATIC_DIRECTORY 'd:\project\project\orcad\allegro';
9 ~( Y: M" F# W: w6 \' o, C4 RBOARD_DIRECTORY '';
OLD_BOARD_NAME 'halfadd.brd';
NEW_BOARD_NAME 'halfadd.brd';
CmdLine: netrev.exe -5 -y 1 -n -i d:\project\project\orcad\allegro d:\project\project\orcad\allegro\halfadd.brd d:\project\project\orcad\allegro\halfadd.brd
------ Preparing to read pst files ------
Starting to read d:/project/project/orcad/allegro/pstchip.dat
% @+ @, \( W# T  c2 u2 v$ e   Finished reading d:/project/project/orcad/allegro/pstchip.dat (00:00:00.00)
# Q: R- B' Y6 {8 H3 y+ m+ Q8 GStarting to read d:/project/project/orcad/allegro/pstxprt.dat
0 N; @+ A' E8 I7 v1 _! v7 M2 Q& B8 c   Finished reading d:/project/project/orcad/allegro/pstxprt.dat (00:00:00.01)
Starting to read d:/project/project/orcad/allegro/pstxnet.dat
   Finished reading d:/project/project/orcad/allegro/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------

#1   WARNING(304) Device/Symbol check warning detected.
Symbol 'DIP14' for device '74LS04_DIP14_74LS04' not found in PSMPATH or must be "dbdoctor"ed.
    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.
9 t, h4 U2 S" t* f; O) [  R8 Q#2   WARNING(304) Device/Symbol check warning detected.
Symbol 'DIP14' for device '74LS08_DIP14_74LS08' not found in PSMPATH or must be "dbdoctor"ed.
    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.
5 E' g# [# [7 |6 j% ?- ]4 p#3   WARNING(304) Device/Symbol check warning detected.
# ~& z% z. c, _* E& u% }Symbol 'DIP14' for device '74LS32_DIP14_74LS32' not found in PSMPATH or must be "dbdoctor"ed.
    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.
5 J2 H6 \9 p: [8 x7 U------ Library Paths ------
2 G' J) K. Y3 z# `& M7 V" g% Y. BMODULEPATH =  .
           F:/Cadence/SPB_15.7/share/local/pcb/modules
PSMPATH =  .
1 m7 @. E. N" v1 {% M+ z+ Q           symbols
           ..
/ L8 D7 Z3 _% j# d3 Z2 Z           ../symbols
           F:/Cadence/SPB_15.7/share/local/pcb/symbols
           F:/Cadence/SPB_15.7/share/pcb/pcb_lib/symbols
- d! \* B" u6 i+ h8 S. a           F:/Cadence/SPB_15.7/share/pcb/allegrolib/symbols
PADPATH =  .
           symbols
           ..
           ../symbols
           F:/Cadence/SPB_15.7/share/local/pcb/padstacks
           F:/Cadence/SPB_15.7/share/pcb/pcb_lib/symbols
/ m( G, B3 o! q* D! o) W4 r           F:/Cadence/SPB_15.7/share/pcb/allegrolib/symbols

------ Summary Statistics ------
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3 K' i# }2 A. D+ f  `netrev run on Aug 19 15:49:19 2008
   DESIGN NAME : 'HALFADD'
   PACKAGING ON May 28 2006 22:05:31
   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
5 d" C) N" {5 g! S$ q6 B! ^   CROSS_REFERENCE OFF
! }& ]2 p8 i4 H8 X# H. s   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
7 e. T0 Y2 P* O( y2 D( }9 M8 l   MAX_ERRORS 500
   MERGE_MINIMUM 5
5 {0 V7 i( x! I   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
; Q) c  p! _; e, v# \6 A# h   REPLACE_CHECK OFF
5 n( V7 E1 o7 y" D: C6 E% F   SINGLE_NODE_NETS ON
1 P9 @  ~' W2 q/ b6 K+ X  A% x   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON
' l$ h3 {" ~( X9 T No error detected
$ j1 d2 ?  D% \3 Q No oversight detected
$ s4 l4 Y" L) l) Q7 R; R$ ^  3 warnings detected
% ~: }" I# T$ Ocpu time      0:00:14
5 i( Q/ Q. L0 F7 a( pelapsed time  0:00:00

wzwang2000

恩，楼上正解，

sunhui_scut

我今天也遇到这样的问题了，已经解决了。你把DIP14.dra、DIP14.psm和相应的焊盘文件放到封装目录下就ok了。要是没有这样的文件你就必须自己做封装了。

genys

楼主,您的这个问题怎么解决的啊?我也遇到同样的问题

lihuizju

最好是这样，不过如果不直接从CIS里将Netlist导入到Allegro中的话，即只生成Netlist是不会要求有相应封装的。但是一旦需要导入到Allegro中的话，那就必须要有相应的封装。
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[ 本帖最后由 lihuizju 于 2008-8-20 10:57 编辑 ]

lxwuming

你的意思是,我在创建Netlist前,要在Allegro中做好原理图中各零件的封装?

sutee7907

封装没有找到吧，应该有个封装对应的PSM文件。