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Cadence SPB OrCAD 16.60.016 Hotfix | 853 mb
8 L: [. H% R5 E- ]: {7 r+ u DATE: 09-27-2013 HOTFIX VERSION: 016: {1 X* h' M7 a# R. C4 R. k+ C
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===================================================================================================================================
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CCRID PRODUCT PRODUCTLEVEL2 TITLE# `- ?2 g0 N1 n i$ c2 m) K
0 r9 ]+ Y" \ A===================================================================================================================================
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6 s) H0 t; `& U$ e4 m9 D0 m548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
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1076579 CAPTURE GENERAL Display value only if value exists$ y! j6 n/ i; `
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1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
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: w, r1 r j1 E) s6 w1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility! {! `, U" U1 C8 U" y7 j
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1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
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* I5 p1 J% ?+ D( z1 ?7 K- r" d1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.7 I* N' a# ~9 w; q
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1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape3 i* ?- R. v6 e6 o/ P) F% Z1 r8 z8 M
3 H0 @: y0 r6 p. u: ?2 ~7 Q0 P1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
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4 |" w4 e% l) p; ?1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
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. Y& N# l% L9 m1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
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. o6 R$ h' c' E* y1 b4 p/ |; U8 X M1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.& u/ {9 ?4 G' ^3 ?
9 H) B9 W. I& A& _4 ]1123364 FSP GUI Clicking on column header should sort the column.
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0 t7 y& u, t/ B4 J1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.
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' K$ J7 T! m+ A9 q% ~* ~1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.. @! M' ^4 b1 R+ P% x$ Y5 H9 r/ i
' V; W% t2 L1 D$ m# z6 y f1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.* v$ G1 X8 ~& V( F4 A5 ~: S8 m2 G h
: V0 o1 b9 y! D r2 \1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set, v. _/ D- N! o0 u
* ^1 ?6 b7 D; E7 l+ P1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.% T$ V4 \ g; @- V+ A7 h7 p* ]
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1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.
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1142894 FSP GUI Ability to RMB on a header and select `Hide Column?
5 C% s/ W* J+ w+ t6 {( S1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
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1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings?in FSP
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1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
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/ P3 I. z+ U. @" d" \1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
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1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator! O: c T- q3 y& V0 S
1 `9 H5 K5 t4 b c% v2 ?1145286 CONCEPT_HDL CORE Directive required for switching off the console6 Z) n3 E- \" G- B) z, V
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1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.2 ?* V' l& I& ?: W
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1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
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1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
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1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.- n+ i# r" U3 R% `% h3 P; x% S" Z
6 u6 _; i2 r1 D1 Q8 x# l) N$ k) v5 L" E1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg- J Q: G4 Q% \& A. i
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1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname0 o8 ^ F h' {- a5 m- o: R
/ Z4 s1 I! a! K5 d4 U' L% V1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export0 W+ y n3 \- w) r# _
4 J. f8 B# o8 H) @4 {% y1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.
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1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form2 \ m& R, j6 a0 ]
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1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties." t- I% z9 ~$ ?# {% H) e
$ g7 x& T* N7 p1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
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1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?
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" s9 H( Q( E# [. H1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack# H) }# h: D: m, j0 b! V% W, U
2 b5 N$ |/ S3 I+ k% Z, b1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.- F: u G8 E6 ~7 d' D- ~0 G
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1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
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/ k2 z* Z+ F# _, B1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out
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1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle3 M) c& Y0 S- W! u/ f
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1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
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# A$ D7 L3 \1 k+ h) |+ n1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
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' _6 Q# F- Z' ^- Y% U! d1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
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& a' _# f6 G9 p4 x% r& D6 o) m! o1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
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% Z+ U& [$ d, [7 f1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation
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1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines/ K' K& ?- V9 R& o- Z: |' i2 w; H
@3 b) s/ W: W- \9 I ]! k9 K1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
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1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape
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3 z9 P0 m: s; @; X% r1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
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1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.0 |1 A% n. Q# Z- E2 F6 H& I# Y
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1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6' A) f: `, G1 [5 E, i3 A/ G
! O, ~$ T4 t' U0 ^3 {1162629 FSP PROCESS "Load Process Option" under Run does not work properly
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( b. r r( Q1 R1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
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9 d7 G A+ O7 V% }9 Z1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database2 D. q' ]/ g9 ^+ r! C
5 U* J6 B( M' v1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.. C9 U) `/ w y
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1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace
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1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin4 @5 ^; }7 q; Y0 [& l
. g' P6 K( [2 m1 T8 `/ f( y6 M1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?+ p$ ^8 E3 w5 `
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1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
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1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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! v* p" R0 e0 [ k1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.' a H/ ^) B# j, D2 e1 j$ F
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1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.& l* l) F M' @& i4 b
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1165561 CAPTURE DRC File > Check and Save clears waived DRCs
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0 D3 O+ ~0 H$ C/ l& s8 F8 L5 _$ X1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window) \" n6 h3 J ~
! _: _0 y9 r2 E8 }4 X1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
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1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked4 c" f" Q+ p9 [
% P/ P+ a7 A) Q0 D3 {$ l& G; C1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
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- K0 K% d& ]9 f1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle; f* |8 ~+ }# F& S) m
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1166074 GRE CORE GRE crashes during planning phases, `$ q$ A* M7 k6 g9 b0 I
( T* W8 \9 T% [+ Y: R: b; e) {1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed' v, ^6 b) {& n9 Z1 q7 ?7 q. ?
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1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
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( f- ^' ]: F4 S2 r7 i/ \1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move+ J( ^9 _ u+ ~7 R) {
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1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue% U. M$ J# ?( I; N# ^
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1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash V9 V( q, f# Q+ [: F" E, a
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1167887 F2B OTHER Improve message on symbol to schematic generation
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1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate.0 [9 m! E) y. f; V' |# h7 m' P
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1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
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1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045., h0 }6 Y. p0 d& p/ `
. W) U c; Y3 N3 v0 ]* L1 v1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk/ [$ z5 t( W' b" Q
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1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check0 b6 d/ F3 w+ h- d4 c
/ a' b% d/ a2 B4 P, }, Y1 v8 H1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
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1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
0 ]+ }* E5 ~) {$ T& K0 Y% c6 l/ h. p; Z" K
1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts* x: i; a' o- C/ Z1 {
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1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule
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1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file/ j, u4 J6 \8 n8 W
0 m7 \& @. {9 y, V! F* j1 Q) R1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
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, y9 O$ v/ K% i' j& h! I1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
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- H+ _4 K8 S! y" D9 D1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing% s2 ?- _8 W5 T
$ G ]/ k! T( {1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
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4 g$ Z% A) Y& r G" |5 c1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
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1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
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1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm% w' v3 q, v* Q0 B
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1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific! r2 G3 k& r4 F6 F' f9 ~' P
. J; k( Z; k& J1 x0 K7 J; s1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically/ r9 s" @8 a6 c: g/ y
& L/ ~/ u, Z/ q1 `* b1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules1 k5 u8 Z! Y2 g# V
) P7 z* d# j4 M! L3 m. [1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause.. ^, V4 A/ C# A+ a
7 V$ |* P4 a( t, b1 e: a. M
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl8 X: R% e% y0 V3 _$ ^+ k% M
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1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.' O# P3 K* W( h2 H. s) k+ P
* A) L# M$ _/ h3 D1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height/ X" p: h; c p, E3 A1 S
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1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer7 `8 @4 \" d6 T5 I$ o4 j
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1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
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+ }* B9 n& k7 |2 i' h; T% {1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
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1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
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1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas./ P; a. Y* g) {7 n/ y
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1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
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1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing9 F& M' p2 L6 A
$ T& K: H8 H5 a( R) M( B [# u$ B1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin) `0 w0 {0 e: x
) t" Z1 }3 k- |& u2 D1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps1 E* ^8 m# N8 B
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1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box4 o$ F7 Y4 M0 i0 c5 v
# q8 c! e! A2 r/ |1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
0 J& o9 X [- v; n5 v# Y0 t2 k( A& s" \. ` d3 j+ H
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!5 T2 g' m3 K2 Y+ R' @/ X
0 ^ C. S" i3 m# k+ f) L
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
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5 A2 p0 k; y9 z9 [1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash
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1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
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1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block2 I! Z4 D3 t% p) r
0 v6 o4 Q& g) v( L/ n# L
1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
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B$ q6 h c# g3 m( c# [$ L5 G1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
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8 U: t( V* C) G8 p8 H, m1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.' i3 j% y% |' i. a" u9 ^
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1 \; \. H. y7 Z9 y i# k' xCadence SPB OrCAD 16.60.016 Hotfix3 |' v0 y/ H- h7 A
3 ?; P2 [1 a# z4 [1 H2 Z" [+ MDownload uploaded! t4 f- ?: c( y( U0 j& s
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9 _: \ ^; `" m3 u4 F# ]% r
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发表于 2013-10-5 20:59
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