Cadence SPB16.6下载(Hotfix013已发布更新)

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Cadence SPB16.6下载(Hotfix013已发布)

* w. t, n# m! l2 vCadence SPB16.6已经推出，需要的朋友可以点击下面的链接下载：
http://dl.vmall.com/c0ych9k8m3
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* g" o1 P1 o& }1 fDATE: 07-26-2013  HOTFIX VERSION: 013
0 V+ u9 z; S" C% O6 S, N# z===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
: z5 \, w5 s& H  i" q# X- D===================================================================================================================================
, H8 v* K) k6 x; X8 e) n' b111368 CAPTURE        CORRUPT_DESIGN   Capture - will not produce allegro netlistwith 10.0
" ?5 ~! p. I5 u  D' x3 q134439 PD-COMPILE     USERDATA         caCell terminals should be top-levelterminals
8 i  r1 P3 w( P& h! g& S( D( h186074  CIS            EXPLORER         refresh symbols from lib requires youto close CIS
, U4 H9 A  W. n' Y$ Y4 E583221 CAPTURE        SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock
5 s' v5 `% g, k" f591140 CONCEPT_HDL    OTHER            Scale overall output size inPublishPDF from command line
801901 CONCEPT_HDL    CORE             Concept Menus use the same key"R" for the Wire and RF-PCB menus
1 V* J& _: `, @2 W# P813614  APD            DRC_CONSTRAINTS  With Fillets present the "cline toshape" spacing is wrong.
881796 ALLEGRO_EDITOR GRAPHICS        Enhancement request for Panning with Middle Mouse Button
887191 CONCEPT_HDL    CORE             Cannot add/edit the locked property
911292 CONCEPT_HDL    CORE             Property command on editing symbolattaches property to ORIGIN immediately
987766  APD            SHAPE            Void all command gets result as novoids being generated on specific env.
1001395 SIP_LAYOUT    ASSY_RULE_CHECK  Shape Minimumvoid check reports lots of DRCs which are not necessary to check out.
% Y* }% f7 Z9 l/ }+ N5 i1030696 ALLEGRO_EDITOR INTERACTIV       Enh - Allow another behavior of PANmovement using middle mouse in Allegro
# c! P; l  h$ s5 h1043856 ADW           TDA              Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user
1046440 ADW           PCBCACHE         ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project
9 w0 ~2 Q# P1 I- m* m5 b5 y1077552 F2B           PACKAGERXL       Diff Pairs get removed when packing withbackannotation turned on
" {8 j4 u. H7 a1079538 F2B           PACKAGERXL       Ability to blockall 縮ingle noded nets� to the board while packaging.
1086362 ALLEGRO_EDITOR SHAPE            Enhancement request to autovoid a viaif shape cannot cover the center of the via.
1087958 PSPICE        MODELEDITOR      Is there anylimitation for pin name definition?
1 E6 B( c" `$ W, w; Q7 m& o1087967 CIS           UPDATE_PART_STAT Update part status window shows incorrect differences
. k( V7 N' K3 }  }. m, B: t1090693 ADW           LRM              LRMauto_load_instances does not gray out Load instances Button
1 m' T) s0 z( b4 r8 A, [# O7 A1097246 CONCEPT_HDL   CORE             ConceptHDL -assign hotkeys to alpha-numerical keys
3 ~0 C' m6 F# U* w& W) h1099773 CONCEPT_HDL   CORE             DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option
1100945 SCM           SCHGEN           SCM generatedDE-HDL has $PN placement issue
1100951 PSPICE        SIMULATOR        Increasing theresolution of fourier transform results in out file
$ G0 R+ J& _/ L; D7 @1103117 RF_PCB        FE_IFF_IMPORT    Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit
1105473 PSPICE        PROBE            Getting errormessages while running bias point analysis.
1106116 FLOWS         PROJMGR          view_pcb settingchange was cleared by switching Flows in projmgr.
1106298 ALLEGRO_EDITOR INTERACTIV       Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options.
1106626 CONCEPT_HDL   CORE             Concept HDL crashes when saving pages
1107086 ALLEGRO_EDITOR INTERACTIV       manual void with arc's goes in wrongdirection during arc creation
9 p" \6 N, A4 j' _7 Z7 B* I1107172 CONCEPT_HDL   OTHER            Project ManagerPackager does not report errors on missing symbol
" d2 P  i7 r4 h, m3 |- Y  f: c1108193 CONCEPT_HDL   CORE             Using theleft/right keys do not move the cursor within the text you're editing
1 f- T; K  q( E6 D8 V1108603 PCB_LIBRARIAN VERIFICATION     PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm
1109024 CIS            OTHER            OrCad performance issue from Asus.
# r0 |4 v$ i6 B6 W% W1109109 CAPTURE       NETLIST_ALLEGRO  B1: Netlistmissing pins when Pack_short property pins connected
, M# \7 ]/ c& z$ t# I- O- \1109466 ALLEGRO_EDITOR ARTWORK          Artwork create some strange gerberlines for fillet.
1109647 SIP_LAYOUT    DEGASSING        Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.
( a* F( a; E* R3 n0 c. @% X( s1109926 CONCEPT_HDL   CORE             viewing a designdisables console window
) r1 x# @, c+ G3 D  F5 u9 R) f2 Z1 z) A1110194 SIP_LAYOUT    WIREBOND         If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds.
1112357 SIP_LAYOUT    WIREBOND         wirebond commandcrashes the application
* @2 w/ n9 S! p2 F$ x8 O1112395 CONCEPT_HDL   CORE             縗BASE\G� for global signal is not obeyedafter upreving the design to 1650.
1112658 CAPTURE       PROPERTY_EDITOR  Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance
1112662 CAPTURE       PROJECT_MANAGER  Capture crashesafter moving the library file and then doing Edit> Cut
1113177 PCB_LIBRARIAN CORE             Pin Shapes arenot getting imported properly
1113380 ALLEGRO_EDITOR INTERACTIV       Change layer to - option for packagetype .dra is not available in 16.6 release
1113656 SIP_LAYOUT    WIREBOND         Enable Changecharacteristic to work without unfixing its Tack point.
- S# c+ l2 \! `9 ~) Y1113838 SIP_LAYOUT    DIE_ABSTRACT_IF  probe pinsdefined in XDA die abstract file are added with wrong location
1 S- F; i5 p4 e! S6 h$ @1113991 CAPTURE       GENERAL          Save Project Asis not working if destination is a linux machine
- z' b# v2 l! |9 q, g+ A1114073 APD           DRC_CONSTRAINTS  Shape voidingdifferently if there are Fillets present in the design.
1114241 CAPTURE       SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic
7 N8 V% l5 J% k0 M5 B1114442 PSPICE        PROBE            Getting Internalerror - Overflow Convert with marching waveform on
1114630 CONCEPT_HDL   ARCHIVER         Archcore failsbecause the project directory on Linux has a space in the name
1114689 CONCEPT_HDL   CORE             Unknown projectdirective : text_editor
1114928 F2B           PACKAGERXL       縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A
4 }* M/ |+ K* w# R, o1116886 CONCEPT_HDL   CORE             Crefer hyperlinksdo not work fine when user use double digits partitions for page Border.
) v: p  ~! k3 J; `" g1118088 ALLEGRO_EDITOR EDIT_ETCH        Should Plan accurate and Optimize beremoved in 16.6?
1118734 APD           EDIT_ETCH        Multiline routingwith Clines on Null Net cannot route in downward direction
  ~7 ]5 S. I5 ~$ e6 |3 V1118756 ALLEGRO_EDITOR SHAPE            Shape clearance parameter oversizevalues getting applied to Keepouts
3 ~: b6 S1 v- Y( n0 e7 m7 l1119606 CONCEPT_HDL   MARKERS          Filtering two ormore words in Filter dialog box
1119707 CONCEPT_HDL   CORE             Genview does not use site colors when gen schfrom block symbol
1119711 F2B           DESIGNSYNC       DesignDifferences show Net Differences wrongly
4 H9 I* m3 @( d  y& Q1120659 CAPTURE       PROJECT_MANAGER  "Saveproject as" does not support some of Nordic characters.
1120660 CONCEPT_HDL   CORE             Save hierarchysaves pages for deleted blocks.
. }& o2 [6 ~- t: }- r* r6 g1120817 SIP_LAYOUT    SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode
0 C# l, |! c" [1120985 PSPICE        MODELEDITOR      Unable to importattached IBIS model
1121171 CONCEPT_HDL   CREFER           PNN and correctproperty values not annotated on the Cref flat schematic
( B! }7 p6 Q* Y/ E' C9 m1121353 ALLEGRO_EDITOR INTERACTIV       Local env setting will change aftersaving and reopening.
7 x3 u& k* `8 @. h1121382 ALLEGRO_EDITOR INTERACTIV       Undo command is limited to two for thisdesign
* Z. a* K2 @+ q4 @0 D2 w1121540 F2B           PACKAGERXL       pxl.chg keepsdeleting and adding changes on subsequent packager runs
1121558 ALLEGRO_EDITOR MODULES          Unrouted net and unrouted connectionwhen module is placed of completely routed board file.
1121585 ALLEGRO_EDITOR OTHER            Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result.
1121651 CAPTURE       SCHEMATIC_EDITOR "PCB editor select" menu option is missing
4 [9 {6 ?4 O- R1 B! M" ^1122136 SIP_LAYOUT    PLACEMENT        Moving acomponent results in the components outline going to bottom side of the design.
1122340 CAPTURE       NETLIST_ALLEGRO  Cross probe ofnet within a bus makes Capture to hang.
1122489 CONCEPT_HDL   OTHER            Save _Hierarchycausing baseline to brd files
1122781 CONCEPT_HDL   CORE             cfg_package isgenerated for component cell automatically
8 y  B8 c# I, i) M4 r4 a1122909 CONCEPT_HDL   CORE             changing versionreplicates data of first TOC on 2nd one
1123150 CONCEPT_HDL   CORE             property on yaxis in symbol view was moved by visibility change to None.
/ [6 C( |- f  _1123176 ALLEGRO_EDITOR UI_FORMS         Negative values for pop-up location isnot retained with multiple monitors (more than 2)
% z! F/ w7 L& Y) x9 b3 ~% I1123815 ALLEGRO_EDITOR GRAPHICS         Embedded netname changes to a differentnetname
1124369 ALLEGRO_EDITOR INTERACTIV       Sliding a shape using iy coordinate doesnot work indepedent of grid.
1124544 CONCEPT_HDL   CORE             About SearchHistory of find with SPB16.5
1 t/ `& i* V+ }. u$ y1124570 APD           IMPORT_DATA      When importingStream adding the option to change the point
* U. u1 d1 f. G7 ?7 s1125201 CONCEPT_HDL   CORE             Connectivityedits in NEW block not saved( lost) if block is created using block add
+ W  i6 f# p% y( }7 F1125314 ALLEGRO_EDITOR INTERACTIV       Enved crash during setting of library paths inuser preference
; A6 ~/ d; k9 f1125366 CONCEPT_HDL   CORE             DE-HDL crachesduring Import Physical if CM is open on Linux
1125628 CONCEPT_HDL   CORE             Crash on doingsave hierarchy
3 ?! K' u6 r2 X) q% g1 ]9 ^1130555 APD           WIREBOND         Wirebond Import should connect to pinsof the die specified on the UI.
1131030 PSPICE        ENVIRONMENT      Unregistered iconof Simulation setting in taskbar
1131083 ALLEGRO_EDITOR INTERACTIV       Bug: 16.6 crash in changing the mode inFind filter window
1131226 ALLEGRO_EDITOR PLACEMENT        When Angle is set in design parameterswhile placement component is rotated but outline is not.
1131567 CONCEPT_HDL   OTHER            Lower case valuesfor VHDL_MODE make genview use pin location to determen direction.
+ |/ ~' K3 ?+ `, B: ~1131699 PSPICE        PROBE            Probe windowcrash on trying to view simulation message
1132457 CONCEPT_HDL   CORE             The schematicnever fully invokes and has connectivity errors.
1 `4 E' F7 ]  x; Y4 Z1132575 CONCEPT_HDL   CORE             2 pin_name weredisplayed and overlapped by spin command.
1132698 ALLEGRO_EDITOR EDIT_ETCH        Slide Via with Segment option with newSlide command
1132964 ALLEGRO_EDITOR SHAPE            Same net "B&B via toshape" errors created when adding shape
1133677 CONCEPT_HDL   CORE             Cant delete norreset LOCATION prop in context of top
1133791 CONCEPT_HDL   CORE             Cant do textjustification on a single selected NOTE in Windows mode.
% |% k/ A9 r4 f1134761 CONCEPT_HDL   CORE             Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property
1135118 ALLEGRO_EDITOR INTERACTIV       Mirror and other editing commands aremissing for testpoint label text in general edit mode.
1136420 CAPTURE       GENERAL          Registrationissue when CDSROOT has a space in its path
1136808 PSPICE        STABILITY        Pspice crashmarker server has quite unexpectedly
/ p2 t# E+ Y9 P& k- @1136840 CAPTURE       SCHEMATICS       Enh: Alignment oftext placed on schematic page
1138586 ADW           MIGRATION        design migrationdoes not create complete ptf file for hierarchical designs
! m4 V# f4 R! j& a1139376 CONCEPT_HDL   CORE             setting wirecolor to default creates new wire with higher thickness
1140819 APD           GRAPHICS         Bbvia does notretain temp highlight color on all layers when selected.
. \! ]* q! I2 ?) `" J3 A" B+ y1141300 CONCEPT_HDL   CORE             DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped
1 v4 r7 _2 J4 D* c; U1141723 ADW           PURGE            purge commandcrashes with an MFC application failure message
; ~1 J& `# H" b$ m1143448 CAPTURE       GENERAL          About copy &paste to Powerpoint from CIS
. }& o+ [; P/ r/ t5 Q1 A* g: y1143670 SIP_LAYOUT    OTHER            Cross Probingbetween SiP and DEHDL not working in 16.6 release
1143902 ALLEGRO_EDITOR DATABASE         when the shape is rotated 45 degreesthe void is moved.
1144990 PCB_LIBRARIAN CORE             PDV expand &collapse vector pins resizes symbol outline to maximum height
1145112 CONCEPT_HDL   CORE             Warning message:Connectivity MIGHT have changed
7 y, m4 i$ ^9 S8 z4 Q2 M9 f+ W! k1145253 CONCEPT_HDL   CORE             Component Browseradds properties in upper case
) L- u: f% ~" i; g! k& q# M1146386 ALLEGRO_EDITOR INTERACTIV       Place Replicate Create add Static shapewith Fillet shape
' a* _6 S$ z/ {3 i% F% t1146728 F2B           PACKAGERXL       DCF with upperand lower case values on parts causes pxl to fail
1146783 ALLEGRO_EDITOR INTERFACES       Highlighted component is missing fromexported IPF file.
1147326 CONCEPT_HDL   CORE             HDL crashes whentrying to reimport a block
+ n6 \3 m9 w: k1148337 CAPTURE       ANNOTATE         Checking "refdes control" isnot giving the proper annotation result
- G3 f5 ~5 C1 y% q+ A* R1148633 SIP_LAYOUT    INTERACTIVE      Add "%"to the optical shrink option in the co-design die and compose symbol placementforms
6 y8 x: {* x0 R8 `! x# n/ [7 O1149778 CAPTURE       SCHEMATICS       Rotation of pspice marker before placementis not appropriate
4 _0 t- S5 y) B) A1149987 PCB_LIBRARIAN PTF_EDITOR       Save As pushingthe part name suffix into vendor_part_number value
1151748 ALLEGRO_EDITOR OTHER            If the pad and cline are the samewidth don't report a missing Dynamic Fillet.
1 \3 T3 [( U# s8 k6 ^! I' z4 l4 t1152206 CONCEPT_HDL   CORE             ROOM Propertyvalue changes when saving another Page
7 x% S0 [  e$ P4 c5 J! N1152755 CONCEPT_HDL   COPY_PROJECT     Copy projecthangs if library or design name has an underscore
7 [# |! Y8 |: E" ?' ]; N1152769 PSPICE        ENCRYPTION       Unable to simulate Encrypted Models in16.6
1153308 ALLEGRO_EDITOR DRC_CONSTR       Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date
1153893 F2B           DESIGNVARI       16.6 VariantEditor not supporting - in name
# g: H- E$ A- t" X& D' ~1154185 SIG_INTEGRITY SIGNOISE         Signoise didn'tdo the Rise edge time adjustment.
1154860 ALLEGRO_EDITOR MANUFACT         Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend
1155167 ALLEGRO_EDITOR EDIT_ETCH        Via structure placed in Create Fanouthas incorrect rotation.
5 M9 A& R2 d/ g, q" C1155728 CONCEPT_HDL   CORE             Unable to uprevpackaged 16.3 design in 16.5 due to memory
1155855 SCM           SCHGEN           A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode
1156274 ALLEGRO_EDITOR INTERFACES       Exported Step file from Allegro is wrong
- ?- y4 F4 C: O" y. c8 i1156316 CONSTRAINT_MGR OTHER            Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager
5 b" T2 n6 N- _7 p2 K+ f1156351 CONCEPT_HDL   CONSTRAINT_MGR   Loose members inPhysical Net Class between DEHDL and Allegro
$ S8 B+ \# {7 j& d& q3 m* ~* k1156547 ALLEGRO_EDITOR DRC_CONSTR       Etch Turn under SMD pin rule checkthrough pin Etch makes confused.
. I$ Y+ w. V5 A' p2 G) K1156779 CONSTRAINT_MGR OTHER            Electrical Cset References in CM notworking correctly
) x( S9 Y& d( R1 a0 J1157167 ALLEGRO_EDITOR SKILL            axlPolyFromDB with ?line2poly isbroken
1158042 ALLEGRO_EDITOR DFA              DFA_DLG writes the dra file namein uppercase.
$ ~8 X$ `! a1 l4 ~! X1158718 CONCEPT_HDL   CHECKPLUS        Customer couldnot get $PN property values on logical rule of CheckPlus16.6.
1158970 ALLEGRO_EDITOR SCHEM_FTB        Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file
% o: B+ g" U$ m1 s/ a2 Q1158989 ALLEGRO_EDITOR INTERFACES       pdf_out -l creates a PDF
1159285 APD           DXF_IF           DXF_OUT fails;some figures are not exported
% M, z. P7 U% J8 p1159432 ALLEGRO_EDITOR SHOW_ELEM        http:// in the Show Element in 166 donot have HTML link to open the Website
1159483 PCB_LIBRARIAN SETUP            part developercrashing with
1159516 ALLEGRO_EDITOR EDIT_ETCH        Unable to slide cline segment with newslide.
* l+ X' M& ?+ \% Q* i4 z6 Y, s: h1159959 ALLEGRO_EDITOR GRAPHICS         3D viewer displays clines arcsincorrectly
( v8 c; {: x% W3 j) p. k1160004 SCM           UI               The RMB->Pastedoes not insert signal names.
5 c5 v7 L2 y, w& R- n6 U1160410 ALLEGRO_EDITOR DATABASE         Lock databse with View Lock option ismisleading
; }8 w, A) k* B2 w1 E/ n1160529 SCM           SCHGEN           Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure
6 m) ~( {  N" L1 _. ~+ W1160537 SPIF          OTHER            Cannot start PCBRouter
7 Z7 m( L' t9 P2 i! x1161363 ALLEGRO_EDITOR SYMBOL           Getting error SPMHGE-73 when tryingto mirror symbol
1161781 CONSTRAINT_MGR CONCEPT_HDL      SigXp crash when selecting ECset indesign
) W( d9 ^$ I9 g% O1161896 ALLEGRO_EDITOR DRAFTING         Tolerance value added for Dimensionsis not working correctly (HF11-12)
1162193 SIP_LAYOUT    DIE_ABSTRACT_IF  shapes in diafile not linked to the die after edit co-design die
; q* G. `( `0 V7 B1162754 APD           VIA_STRUCTURE    Replace Via Structurecommand selecting dummy nets.

每一天都不同

感谢分享

陈志军

好

q343408315

怎么屏蔽了
1 D# `- A. i" H( L

2000

楼主辛苦了！ 谢谢

txqtomton

楼主辛苦了！ 谢谢