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http://pan.baidu.com/share/link?shareid=437717&uk=3826038294
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DATE: 05-24-2013 HOTFIX VERSION: 010( ~' x h) @! q. ^
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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7 [7 @; C; g- m. S# A$ }( C1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
- C' p6 ~" e' ~: C, ~# W* T" h; v" k1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border% m& t4 j% |3 H- O
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
& C) L) T$ B* ~- C2 v* t1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
4 K( }- j2 A/ s2 K6 q; e7 \# Y1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.61 s; ?1 H5 R; S( Z1 k
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border/ \0 k y' |5 n# I; ~
1131775 ADW LRM LRM error with local libs & TDA6 n f& J4 h6 b
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
& l& } k6 O9 |3 }' B- e) i1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo8 b) J' p9 z5 L
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.5 S) p+ {' F3 ^+ Z7 g5 E7 |
1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur: _ V0 J- O4 C
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?
+ ~5 _2 w$ p+ m& b3 ~* X- r1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer." Z1 E( M* P* m& _
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor
/ l: L3 y/ l1 n% H5 Z( F1 P1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
8 L# l* ?" s" Z4 H1 i9 N f1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
5 |! @% m2 w! q! b& D1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
9 U. ~1 k% L: W% ~1 [1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash- y( T9 k- }: W: x
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
6 {1 J9 H9 T& Q) ?! X/ C1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering9 f" w& p; U# a' i {$ ]* I0 t% Y
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor1 P- m; ~" p0 n: k; d. T. i
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发表于 2013-5-25 09:24
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