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本人Layout之后分割好地和电源层,灌铜时出现这些错误: g0 S$ F' Z; |& F- i) {
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0 a. ~7 ^4 d$ Z/ x& T. OTHERMAL RELIEF ERRORS REPORT -- FPGA2.pcb -- Fri Jan 11 21:44:01 2013
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B+ I$ e, J3 i$ v# H) ^) y Drilled pads with Nondrilled pads with2 o0 n: t& a+ f' x: B* {% v
less than 50% thermal extensions less than 50% thermal extensions
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# B3 z% _, i: v, ?4 u' yReport of Thermal Spokes Generator.4 ^+ k' _5 }4 P, `5 @
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On GND3:! n5 l; S: n6 `7 D4 ?7 T
(2506, 775) # = 0: P% A( x5 `" b6 F, s/ w6 q4 e
(807, 454) # = 0
8 a/ K: w4 ^0 n+ \) ?9 u& l7 g* u! M (3125, 750) # = 0
% D' @" i9 t$ e' I (418, 189) # = 0
( V! r1 `1 T" K1 Z: t (2199, 749) # = 0
* m& B* f, o; M/ w (1178, 648) # = 0
2 j1 L. |' r6 T9 B (1295, 800) # = 0
: O6 w* N* c6 y/ X( s (1256, 839) # = 00 Z! M3 M. D3 m
(1763, 878) # = 0
. V8 f2 b: Z4 c" \5 t/ [ (1646, 878) # = 0
+ q2 | F: t9 D' h4 N o4 e (1295, 878) # = 0( D* M' h# d5 c
(1295, 917) # = 0; d; H8 J% J6 Z1 V
(1256, 956) # = 0
. F# G' h: s: i) q/ b (1685, 1034) # = 0: t5 I% Q- B5 J+ e- H
(1295, 1034) # = 0! H! }) L2 }8 S4 s; O( P" e
(1646, 1073) # = 0
' c, Y% t: C5 s1 [/ i+ A* E (1295, 1151) # = 0
& f' w7 \ I% ], F! H% q (1490, 1231) # = 0
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9 {& P1 N& w' L$ O% `8 u! GTotal Drilled pads: 18 Total Nondrilled pads: 0# H7 ]* w/ u; O) [, p
! k9 L. E! f- e4 V: }+ V4 r" MReport of Violating Thermal Spokes Remover.
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0 |/ c" E2 c) WOn GND3:
' O) z; t' b) `- ~# y (1373, 1151) # = 0 Q9 p' W+ A8 o" J; J0 W
(1490, 1151) # = 0
# p" Q2 `$ Y$ J2 s2 B& N8 a6 k (1529, 1151) # = 0
; \4 Y5 I/ x6 W8 s. {2 M7 M (1568, 1151) # = 0" U; v+ ?* y( u, |( C
(1373, 1307) # = 0. T7 [6 m7 K$ a/ T
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(2086, 1220) # = 0
) K9 Y5 m) i+ E) S- _' U (2334, 760) # = 00 w l/ n- B2 M) p
(1178, 683) # = 06 o! _0 E& @4 {6 o! h3 E' @
(1139, 683) # = 08 ~; `. }- |* b$ @( k9 C
(1728, 882) # = 04 |3 B( D4 M$ F- _3 M
(1143, 761) # = 1
8 g- i" [8 t/ O. r7 o- C. Y3 i (1218, 1181) # = 0( t: |2 S. V d; C* y+ p4 u. f! t& M
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Total Drilled pads: 12 Total Nondrilled pads: 00 T: @9 n8 p, o& S6 q9 l- z& S
不知道 这是什么问题,如何解决? |
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