|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
; v0 K% H% b" [) ?DATE: 02-17-2012 HOTFIX VERSION: 016# p5 Y3 s8 w2 `8 j) ]% h
===================================================================================================================================0 ?% Y+ W# R( F/ F( I
CCRID PRODUCT PRODUCTLEVEL2 TITLE) N+ ~$ z! T/ z- @8 i* t2 _
===================================================================================================================================
: T1 T! K; N9 ]840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV' y& F$ }% E- N: Q# a
873075 PSPICE PROBE Decibel of FFT results are incorrect.. N4 c5 ? Q. U( _; o" I$ x
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
2 v! g# i m8 @2 X6 v1 k943003 SCM REPORTS The dsreportgen command fails with network located project
( t3 R5 s, {$ ~2 q961530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command
6 t3 }" [7 n u6 K( x8 H962157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
0 S8 l J8 v, i. Z962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend5 S2 j. G' s5 ?9 A/ n
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
, P4 \' T3 S8 `& g968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
8 k8 r+ m* @+ ^969450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes8 J8 n) S. E {* }1 d
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~" y: b- K* y% E! `# {
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.$ n& ^! U5 r: I' k" j
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
& K8 m0 @3 I$ i" g5 ?2 w4 z973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
+ r/ ^/ s& u" X, ]. f1 V1 x, c973859 PSPICE ENCRYPTION Pspice crashes with encrypted model7 i" V/ d; {) a* p3 p+ |4 }
973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
- V+ k. Z$ Z8 j( @7 y. A6 w% r974540 CONCEPT_HDL CORE Graphics updates are real slow* _' i+ x+ V2 ]3 Y
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
6 k1 h- W# Y2 @) J974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.0 _8 K6 p: g: d. z+ _, v
974945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working& d/ f8 D, n) R, W- o8 ]7 a
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology& c5 c* x" d+ S4 u
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5" U& C( S: g# X/ X) y* q! N
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)# J/ a5 f! f8 B% A g& f, G4 N' X7 `: D
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
! i9 R d* {9 J( R* X/ [975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
+ W3 z' F% \ E976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
0 v, @+ A* I' F2 ?$ G5 G$ B976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views/ Q9 ~7 z* s8 r9 d
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
+ x) w+ |8 H2 @4 o$ A' Q976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
p* V! T8 M9 o. }9 n; m976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC3 A" @! i7 U& @+ X* p7 B! R- \
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value& M5 z8 [0 F( y3 `7 t5 R: `
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
: v0 A; S' t1 h& b7 v& U h976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.$ l5 t5 G% X/ U) h( T
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
u+ }) a. s6 c5 l977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro# L$ b% X% n% x+ K! B: v
978652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.
9 o* m& X m: ? d8 a1 w978744 APD DEGASSING Some shapes will not DeGas on this design
& n$ R6 z, y' a, k! K9 l9 j) \979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection. H$ i- Z3 Z3 N' @; n
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 156 K$ j& }7 e8 h: ~: {# h3 [
3 M/ v+ i3 Q5 l& W1 D5 h- KDATE: 02-03-2012 HOTFIX VERSION: 0157 n( X; a" ]+ S4 X
===================================================================================================================================; s4 e: a2 ^ S4 b3 ~) x9 y
CCRID PRODUCT PRODUCTLEVEL2 TITLE' F4 f7 u* L3 }9 L
===================================================================================================================================6 }4 ]( @7 v" X8 k5 y3 M
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
& Y5 t. H r/ c; w921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension1 a& o2 m8 O# X' V( ]$ u8 y
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design
* g5 p0 ?0 |" L; D954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
" \# y/ ~2 |& V1 o961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version- M! p9 n- U. k( C
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
2 i7 P# q( e& N. s& N' s: R967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
% I: m7 C3 g" I7 k: p968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
4 Q8 M! a4 m. m969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.54 K8 J p! H5 B# z0 @
970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance1 N# B* x. N+ M7 p4 X9 H
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
3 x% z- }" `! d" |8 g/ z970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.; O: T4 Y# p, u
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
5 R/ R( j. m* R8 j1 Q, r8 L2 L970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
6 U' W! f9 C: w/ K5 P$ d! e971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
) o2 k1 C$ V' T7 A# J+ J4 i971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances8 }% c" h! B* `% v# f9 s9 @' {
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
, a% ^+ T7 J3 t5 @3 o P. ~972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT) Q- b$ h! o4 H& j/ {* e
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package. o! Z7 o3 W4 A6 ?
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized9 c' D- f& a& K9 D9 F" z, B
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value2 N2 K9 x8 }4 E9 X, w6 _
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
/ Q* ]* M! @+ ]5 p$ I973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net! R8 P2 M$ |$ g* g0 i! G. Y! R
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
' V5 M9 j4 q0 t* h4 C# v+ `974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.4 c' N. \* G! j; `% G
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working, d, y R# i2 ^# y" A) T, L ?( ]9 {
976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
, Q: G& o; B: ]: D2 S5 S1 r
( ~3 z3 p) Y, vDATE: 01-20-2012 HOTFIX VERSION: 014
+ ^: g1 V; [# Y/ g===================================================================================================================================) \2 z; O, p/ e, W% p
CCRID PRODUCT PRODUCTLEVEL2 TITLE4 h) W7 c z. [! }2 _4 F" g
===================================================================================================================================: g, S0 j$ r2 l4 V2 b* [
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
- s ?, f6 ~* P( ?0 D6 z6 b941020 SIP_LAYOUT OTHER Soldermask enhancement3 f2 n0 h* i; a) _! K
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?+ u2 b. G2 S( b8 ]- f
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable
- ^# {3 P4 ^4 u( I; h; E1 `& W954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic; z" M1 e- b+ c
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs9 h4 X' q; J5 r. K$ B9 V# }, l+ a
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
# R Q/ z; }& Z8 M958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
# x5 i" D+ J* x8 W. t; F4 ?959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
V6 ~! ]: |+ Q% E( S" {4 {2 }959940 APD AUTOVOID Void all command gets result as no voids being generated.
/ Q' T; U7 L8 X7 b+ u960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message
' {* R4 y/ N! z5 R# z961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI/ @; z) P( f9 |6 T; v9 `2 A5 f
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
3 n4 j' D: F" G1 ]9 ?961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
+ @, [7 R4 P- \9 G* A2 K1 n961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.# z2 X9 Z- `0 f
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
/ P& ^( p# @' d3 t3 ?/ C9 u0 ]961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
0 }' P. |8 f! k2 l962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine3 t. K l- p: y( j
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
) F6 ^# P" \& o( f- N963232 CAPTURE MACRO Macros not being played in Windows7
+ G* X$ h- L' w$ I) R( X. @963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
3 f' z: a4 J$ a: {* Y: a+ [' O! U: Z963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux4 I/ T- g# s5 M5 t$ \+ [
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
" ? W7 Z5 M7 Q: W963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length3 H# o; r9 H/ U$ ~' D8 S
964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
( a6 @0 v; E, M E3 j5 ?964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs+ `: k) y- u7 L S5 S& \* c
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
\: y; w/ W# |/ g4 c S966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
+ \) t6 Y0 B* X4 A( M( `966416 F2B PACKAGERXL Cannot package this design1 G [" q, _: R7 Z2 e; R
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks) e% Y; k7 E; M5 G- o
966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
; R- ^: z9 R. k) n( F8 g966795 ADW ROLLBACK rollback utility does not honor -product option from command line
" s; q5 \ P( R* P" o967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.
. ]8 x- G( d6 i) G" w967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing9 e) F0 O) L* T8 A6 C
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
/ a3 G m7 q( y$ M967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.2 I& ~5 }- I" Q/ h t( G9 q" }
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL- X9 G" n! O3 x$ [- M" u
968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.# F8 x6 k* | P! p. D
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
2 @: f' T) T4 ?& b# ~1 a! E968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
& a4 X3 v! K3 |, T- d: B/ Z969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
* J. {2 s( ~7 p; C! ~& z& ~# T; p; _' g0 [ u! b' \- Q7 K* L! M
DATE: 12-16-2011 HOTFIX VERSION: 013
: t3 D) q- I& W( q O===================================================================================================================================
! m9 G6 p$ ]1 w" vCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 R# G2 ]5 H+ Z- Y===================================================================================================================================
8 |/ a6 E1 |% v: E875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
_7 o H7 X! H" k# j7 [# L/ Q927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design- i) t- M9 S! s$ G9 J
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
2 j @& s) I' \941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
0 G$ O6 I; v1 f5 r& @/ W# a! p945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
0 h2 y+ e1 Q, A( l946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat3 v* y/ c; t0 ~9 G, G% D
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.
9 |, r# v# O3 F& ?950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function" j6 O! e) e( H p% |
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.: u# e+ q# K9 G$ e" k& o+ I. c, j4 \
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
& ^: ?: d6 v5 W+ z* j953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
4 y* Q) p5 a5 G1 ?# A953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�8 J: v* z1 Z5 H4 m8 X: t
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup., {& c8 O$ ]/ H
954498 SCM B2F SCM crashes when importing physical
2 h I% `. d6 f* d0 Q" r954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
7 `; [" T1 Q$ L' S: y954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.31 J& D D" U# H! m: E6 j
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view- F0 a5 ]+ T% i" Q
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.' s5 o8 K: K# Z" V ?) f" I2 Z+ y
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window9 e6 O) B0 x; R5 U* o; `
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
: g, J% G3 C& G3 P955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
! J4 I |' P4 R9 ?955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL7 [) j$ c8 k3 L# O! A6 `& B
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
$ \& v4 B% g I) ^. e+ }955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
% f% O! n8 J: H2 e+ |+ |955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
! B9 B3 U( X* P8 h5 {; r; S956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
8 w: F( l& G. H, s$ ?- H3 }956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file+ N5 X3 e( r: P. E8 {% ?7 e% x
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box./ ^- v! m! G5 C2 P5 \/ c
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
, E. p1 ~) Q; W956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined
( t3 U3 s6 b: C% k956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
: S4 v0 @5 r- x. ^* u! N956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component- A! J* G% M! I2 N, ~$ A4 ]
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly
& G8 z, }. R% U0 H# ]956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
' h! {* ^: p7 M& p- B F956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results
7 E" q Z6 A7 ~0 d956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty. N, q- O: b' q; N: C8 b; Q
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
2 }2 N1 w2 e9 _; j/ O- }957137 APD DXF_IF DXF out command dose not work correctly.
' Q9 q' |0 }; k$ T5 b957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
6 ^5 ?! |& K# W1 a5 k8 W" R9 m5 X957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment." l9 z' D/ y. ]* c; N
957267 CONCEPT_HDL INFRA Packager Error after Import Design- v" N. ]) G5 w8 X+ L' P" S2 l4 `
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file. l* ~" Q6 [* _3 i I; H4 K
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
( |. U5 Q" X/ h8 K. j! y$ [2 T958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design `1 l& W. A8 ]1 @1 B+ J; h6 T
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.7 ^: V) w! L+ k+ n# N% j: U, }
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs7 K; _8 q( q- z4 u
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.52 d, k1 C, m. \; ~) G: J+ x
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
( o4 C! _; L- L: v+ A959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs! }9 N. O* ^. C8 M5 J! Y
959253 CONCEPT_HDL INFRA Design will not open4 C) `% d* g' G/ F. o
959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side6 e' v' J" V, F. e: E" E
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.& d* Q2 P$ E- a: _1 I9 P. D6 i- P
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred. U6 \' S' R0 ^9 ]- E' B1 r# A
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.3 D8 e, U! q$ c" D! D
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.9 z2 V, L7 {+ @$ h; G3 g+ v
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter/ u0 U- O) `2 W, ]
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
6 }# P" A8 H n1 K% s0 r961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
; |2 N) i0 D3 I0 x* P& T3 C" {962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers/ ?, b5 V0 |& f+ P" \' M. d
1 y5 c4 i0 `4 I& E; C3 T& g9 s; F# _DATE: 11-30-2011 HOTFIX VERSION: 0127 B( X1 d7 O! V; K6 N$ f6 [1 U+ D2 j
===================================================================================================================================: |) e% z3 d# j3 `3 u/ @
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 l5 Q1 F, h, S0 y===================================================================================================================================8 h g! f8 \4 [# ~9 s; I
959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats p$ m( q6 S7 r, p2 J4 y
5 X5 y, N* j2 e6 b) J# ]% v! m7 uDATE: 11-18-2011 HOTFIX VERSION: 011) R* y& B* H% J8 r/ V4 B0 i
===================================================================================================================================
. _5 T2 I" d$ {; YCCRID PRODUCT PRODUCTLEVEL2 TITLE9 M: y7 v4 J( B5 R
===================================================================================================================================
. w* Q- W; ~" ^735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
4 X* x: j N4 r3 X7 O894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?# W. D6 {2 c$ y
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
) E( S0 l m& c" F909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?' F# f K- F+ R( n( w7 e& G7 p
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.9 t* u# y; H/ Q. ^' @
919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
' b, w6 M, Q2 e# C, d% p0 U921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined
; a0 `/ p8 J8 X, b3 \+ X( G925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.$ p& p* B0 r% m7 s/ b1 V2 t
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
+ N4 K: Z! n- m+ A) o' L H$ t7 n927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
& G! A) E. Z) d934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.* S3 x F; I( i m) A; v# G
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic1 \3 [( O' F4 L/ H5 P T
937165 SCM SCHGEN Can't generate Schematic
% a) i7 S8 k& l9 ]! r$ o937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search/ c7 [' j) B( X5 V9 W: y
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails$ J" f+ X4 [$ x9 q& x' U
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License8 _+ Q7 c* I9 g, X& c
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup2 O' h! O9 L: O. H7 D" A% u( Y* x5 R
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
) W J) t( |, H* G% p* ^) U940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad9 Y7 W7 U/ y% q1 [/ }- }
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
7 G3 H" ]9 O: w940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq1 J& V! p4 E* m) u9 ]
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
* z( m" U, F+ ?* w7 [( ~941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.5 A3 O) T j. T& k/ w+ { v( u
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script+ o! a5 B% O7 _/ d% o B
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?$ L+ ?4 Q7 h( n7 b$ Q
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
7 u8 |+ u6 d1 Y1 d942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel) r# H1 ]& o8 W f9 u
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
: M% \' B/ u/ n$ J942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon n' L' c( [0 K- O! w* g
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.# N5 L$ [8 ^8 ` E" Z% {
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
. M( H: H& R) c943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.; {7 y. ?7 I+ h4 l0 P
943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup8 R- e8 X" P: U) b& i0 r! v
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently) j0 v7 G( g* K# x
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
5 f5 C2 _7 u, t0 B6 m/ \944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines4 L W5 K* }8 [2 g! d: s" }
945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints5 u, T/ S# E: \$ W
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
2 ]) ~% ?& r# C4 d7 l946350 F2B DESIGNVARI Variant Editor rename function removes all components V9 `$ G4 c @3 B. E
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?0 O) `" ^. m; V+ i! N" J
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form
; v% H. z6 D2 c; U% X* F946458 SCM SCHGEN Schematic generator adding an unnecessary page
8 V" m4 L, ]% y( H0 a+ l0 `947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC4 [" g% W/ r, P3 A( \
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.! n1 N7 E' c# b3 ^& t$ v
948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM( T/ T; V, I: ?. U$ L$ k- k! G
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.) J& p! j4 [; z' k, a. _% t% F
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
, t/ C! N7 ]3 O951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original0 b9 B% d& p: }( P' L3 D
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?( ~& g! H' j4 J( z
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
* L3 k* l: _- o* @$ P951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
' \( c$ K, T2 x952057 SCM PACKAGER Export Physical does not works correctly from SCM
/ _# Y/ q2 B3 i6 E: i$ w* g* n952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor. h; k3 ]: e) o; m1 J
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
" |% |0 e* D. z) J. w953018 APD REPORTS Shape affects Package Report result.3 A" S% z6 u' g: x5 K) j/ u1 ^
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.* P8 @7 x7 \9 M: z! S. E; ` \
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
6 \, U. d9 ^7 D% t& z5 M953918 GRE CORE GRE cannot route second and third row of pad in die symbol.# |# \9 t! {) A
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
1 y+ C( }" M( U& v954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
' O. H7 ?, d' V) S9 t4 R- P) E" F( b' _: c& }" m& g
DATE: 11-7-2011 HOTFIX VERSION: 010# F- H1 Z1 g8 ~# `" `0 [
===================================================================================================================================* X) F! k; y) X* D) a C6 }4 I$ i
CCRID PRODUCT PRODUCTLEVEL2 TITLE
" i2 @& P1 K; Q===================================================================================================================================' O s$ _ h4 w/ U$ {
658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
+ B3 _/ x% z; T) @: P- k! p. t928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer* _! l1 G7 P: k1 V9 X) ^. m) M+ N
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile3 y0 _: \! q; o9 o. m; Q" x( s6 V: Y6 \( q
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
8 K- X4 M* T f) l938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
8 k S$ W9 h3 ~# d4 S' {9 N' q0 A938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer* }- ^. @, Y* O7 n+ s) {6 S
940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete
. |0 M9 c) Q. F6 Y: _8 s941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!$ c# Y; u: Z$ m/ }% y1 P
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning) h# [6 E2 ]/ \. N
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
! i& m' H, B1 n/ d942914 SIG_INTEGRITY OTHER ZAxis delay calculation
' q7 L; b/ {5 j943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash7 I. W1 @% X, i; k: I
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die0 e! J' u0 O' `& n2 T- c7 k
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
4 {' T# B; j& D! Q945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
: s! c* ?, I) @5 { r2 S946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions7 Q1 o. r0 { T6 M% | k# U
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
3 L0 v3 W2 `; g/ s$ w946819 SIP_LAYOUT DEGASSING Shape degass command
4 z t9 y( L( F2 J) d1 Z946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up' p2 q) p/ c* n% z$ \0 E/ {
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
. {9 Y* S$ q9 C' N" F8 ] a947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file5 X/ V6 ?) v. c, P, z$ K2 x" L) B
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic" Z+ E7 t/ _0 ~
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
7 j2 |7 P0 n" i5 V951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol2 ?$ z2 @$ `) u: i( e; _
" ]; x2 m" w B+ ~8 J7 EDATE: 10-26-2011 HOTFIX VERSION: 0092 _! C8 y# o- G/ Q
===================================================================================================================================1 ?7 J n2 }& g& f
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 F; k: z" k1 G+ R+ ]; S8 b
===================================================================================================================================* Z$ |+ ]) Z% |$ U# {
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet
" ^& ]' {2 z- X! ]945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference% D8 e5 h& T. }2 z6 S
, K3 x& g0 s4 y, G9 z0 SDATE: 10-21-2011 HOTFIX VERSION: 008
4 c# r2 Z! O/ R! {3 g=================================================================================================================================== M- `1 s7 N% k& @- I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ `' @" e7 z; A8 `===================================================================================================================================; {+ W0 I& X& p" u! u
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
3 W) W# x. Z' c3 o923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
# F% I- m& L- E+ `! {5 N926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
; `7 V E. J9 u+ V. X/ r929348 F2B BOM Warning 007: Invalid output file path name
% H. I4 V, W, M+ W& s, B3 U6 g929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error1 d8 f1 A- B- `0 C1 ~
930783 CONCEPT_HDL CORE Painting with groups with default colors
) J/ b" L, v+ r) |5 F O936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
9 M$ y$ y. b+ {938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
! C1 R- L1 f! L# H3 L938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
: {% t4 u( i* B/ _* ~% ^6 o938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
# m$ t0 ?9 |. |4 w939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window0 H k7 z# H2 P# u6 `. o. ?
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design." ?3 i7 g3 }8 i: B
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
$ q: @ K/ J4 Y L. b, F: c2 h939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.. R5 y0 \5 u @: Q1 L* q
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
# @ \# I) A$ H) E939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.& F% F: p; ^7 `* p$ _
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'0 J5 f$ ~$ m5 U1 Z% |6 x
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost, D4 @9 M' |2 a1 R2 F
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
$ T& ~8 {1 c% P! J6 ~+ q941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
# z+ L9 D* A- T4 Z7 D, y942210 SCM OTHER Is the Project File argument is being correctly passed?
: F) f' n+ i$ y9 u/ f3 ]942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
2 P- t$ b1 h" Q# w2 M) p942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible E* l2 `/ `- Q @
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
D: P+ ~$ ^& H3 x4 Y, |. _6 j) J1 c$ S
DATE: 10-21-2011 HOTFIX VERSION: 0073 Q8 q6 ]( w, S% I
===================================================================================================================================# H" [/ \! J& a$ h
CCRID PRODUCT PRODUCTLEVEL2 TITLE- S3 \- q# A3 X* W5 z
===================================================================================================================================
1 }. _0 h. u, r* K3 @8 k6 h9 a; i* [841096 APD WIREBOND Function required which to check wire not in die pad center.
% V, o& T$ }' f6 n* |7 }& Y. b903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
' m0 ~) b9 O e8 U$ { o5 [906692 ADW LRM LRM window is always in front when opening a project
; x& @$ ^) v- \5 x912942 APD WIREBOND constraint driven wire bonding
1 X) Q" t2 M. I912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems2 V- b' l5 e" ]
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design
7 r7 j0 i) ?4 ^4 y917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
; T% K) ^9 X5 }; i" n2 A, Q; r' Z923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure
$ I2 i C/ L% ^+ \927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
$ K3 O1 Z" b5 L8 |927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
2 D" i* Q8 x5 M. {930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one& X* U* x5 w+ L* I4 }2 s7 B+ }
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
' c, v& \3 n6 c2 ~. Q" t0 [930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
8 \; C) |6 Q, {1 t) j930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
( n( ~7 z8 ~: I, }930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.; ]& F: n1 a" ~
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
5 L" k. y7 B( R4 A4 R- H931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.3 M9 q& g- G2 J
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
2 } ^( j: B& p* }932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear& k# ] x' L3 i, \! B# x* _4 e) o
932292 ADW LRM LRM crashes during Update operation on a customer design
+ W* `8 g+ C7 B4 N5 C4 f932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
4 Y; _! W& i: n7 i) p" [$ `932704 APD DEGASSING Shape > Degass never finishes on large GND plane
+ Y, B. o+ Z9 l. V' L932871 APD GRAPHICS could not see cursor as infinite$ z1 ]2 ]/ B% u: U5 ~0 w# M
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
; J! ~$ o1 h6 }+ ^932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
7 I) r) L3 \7 r! H+ U, ]933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members4 b8 _* i' k: A; ~
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
& o" r( l0 A A, J, g933214 APD ARTWORK Film area report is larger when fillets are removed
9 ]2 ^, J% W8 a% }2 l7 T# E+ O: _# l933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.& `5 O' B# Z6 \/ V4 ?. i. ^
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
0 \) z) b5 v0 ` d% X8 \+ p1 V933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
# d9 g/ O9 f) k6 t" R+ i934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
* F; x4 g* P5 |- O' k: q934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
% K) k+ h! t& d; h5 e' U934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
) e0 U- N M$ {: U7 a! D7 A) b3 c" w H934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.0 x% z5 j% c: L6 x3 |
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
6 a% P) S% ~1 B9 M) f6 ?934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
x: `! ]# ]7 E+ l" z: v934909 SCM UI Require support for running script on loading a design in SCM) b/ a# N' M1 \2 K1 I
935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.4 N7 ]6 J# I k. G! ] e
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3. U! M) S5 |% [& D# M4 P# I
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash
4 A1 M. a# a4 c7 R. T936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol! S2 o3 y% c9 }: b
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.9 l2 W P0 ~, f2 F$ W/ `7 \
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
0 j1 j3 O+ {8 M7 L936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
$ {( g& p: N$ W0 a2 }( Y936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol' O! Z& n, d1 f4 v
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
' M: z% k- A. A; x% t; ? l937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
' }& ^# Y8 R: q& X% F% F B/ K937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About+ X) ]/ ?. j4 Q- z+ t
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.* z% d9 u2 h' w- y1 ~. n
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
. n0 j3 y- I$ K/ ~4 `: A938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.( _' Q1 X5 j* K6 Y1 k- X' o
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
5 q* b' L6 V+ c& R# U" ]: p1 E# `- p g' Z& u' G
DATE: 09-16-2011 HOTFIX VERSION: 006
, `) u# `" h; \===================================================================================================================================
2 n! N( a9 q; z5 y! N6 y, _CCRID PRODUCT PRODUCTLEVEL2 TITLE0 q) s: _! W* [# b2 [
===================================================================================================================================$ k1 [# h/ z5 N
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.6 n9 D( N: } P3 A6 h8 \. p
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
3 {$ z1 b+ I8 K% ]9 x8 S& F919822 TDA CORE Cannot configure LDAP to only list the login name* W& N6 Q. S- @" k5 o
922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
% g) V; w; j; u, Y# |1 z) T924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
_2 H' N# ~6 B4 r924448 F2B DESIGNVARI Design does not complete variant annotation' ~- r" `: r/ u+ @
925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB& C% H' [9 S* Q* R
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report4 x& ^' b9 t2 |# }/ w
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
8 Y* \) [( t0 s2 u4 B927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line9 p8 [, q9 C' Q6 c# O; y6 b8 g
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets* [9 h! j" U* c1 l
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
7 v6 r0 B, x: S+ B! |927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl# }) Z+ X2 G( R! h* N+ H
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
; s& F5 }3 b: Y' Q6 n927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
3 O }/ g* ?4 Y9 S0 K) c, f927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.: n8 g4 L2 l3 P& A+ X0 P% p/ T
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
5 U9 |8 I, ^. E+ G, W/ I928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
% A' N# `! Y6 K# T; `5 {. _0 P8 D0 a928738 PSPICE PROBE Y-axis grid settings for multiple plots
2 m5 k) q6 F! h# n0 F928748 PSPICE PROBE Cursor width settings not saved$ k% V5 F5 c& S! ~" O3 ?
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
7 `% W3 S: Z$ b+ m; Q* d1 s928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
0 }1 ^" E- P1 \" t4 X: p928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe. w/ X7 ~% S7 }
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file- [5 `" l n* `2 R& o6 k
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP4 h* c; r3 ]7 @; _& q- X! R
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error
4 W; _; a. J6 ?8 N' x930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape; N* i8 ~9 ^: ? B0 Q
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
A( B! m9 i( ~% X! r* a8 j930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
4 H, e/ c; {# C- \! O! g930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file., a6 B; C- D9 C% h: a
930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
" H4 L/ w7 L# J. ^% I. ]% w5 B930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name* R, F7 N* x& b% w R9 Z
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
( }1 {8 c1 L6 a( n# c930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
[9 r5 J D9 E+ u; s& U9 t) ^% F/ K931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
% b- [* l- q7 N, D0 p" ]931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version- H9 \& p L: y
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.* ^, }% o9 {" U. m% R( H, ~9 u+ U
2 _4 X5 {1 |8 C/ B; ^# U hDATE: 08-31-2011 HOTFIX VERSION: 005) O. r$ ^+ s& r' n
===================================================================================================================================+ N/ u7 J( P: l" V1 B9 n
CCRID PRODUCT PRODUCTLEVEL2 TITLE
. |! a' [/ g5 Q: p! {8 f===================================================================================================================================
) q4 Z/ L2 I# I, Z825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
& Z7 ^1 G& Y4 ^* V837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
+ w* E) Z( l7 P1 d3 Q' ^891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode" M. T! V" z+ e
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.
3 U ?1 |% ]9 o* a) u: L# g914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.5 p# L5 Q" P$ ]) V' M2 ]" z- f, ^" ?
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs. g+ q4 I+ n# P7 W( X- T' D
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
3 m$ q7 {8 t: s) D, B ^915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
$ J2 h) P% y3 d- ^3 c915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
\! X: }6 v/ q0 C( G8 Q915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
' D# C g: j* v% j/ W4 U1 T916321 CAPTURE GEN_BOM letter limitation in include file
7 U* @3 h- l" J& K; k& @916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
3 t9 f+ V0 V: V2 d+ v. b3 \920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.3 M' k/ }3 g, c- k; i
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
% c' s# }. }+ a* g921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set. O/ D T' m% n( B
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.+ [1 A( l# O7 [/ h8 ]
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S0025 w; Z; H$ O2 I9 q: F8 | E, c
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions, `- l$ `$ U$ v7 h, L, ~1 m& Q
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly( _3 v1 S* K( {+ U
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
# T) Q- n, h/ n7 [922117 PSPICE PROBE Label colors are not correct in Probe7 G! n) H# U$ {- O8 c- M8 F
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
7 n0 B: q( z% w, ^9 T923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002% m& K9 Z) n, q! W3 A( z
923286 CAPTURE DRC DRC markers not reported for undefined RefDes) F3 J2 R v! W: C
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5# _$ d8 N/ m- j) e' p: X2 K' y2 C
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top7 K( m# L5 k: b( O6 C/ H# G" L
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
/ b( U5 m" i1 @0 X6 C, D- j. r923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.
8 G( A* [0 t5 ~6 D7 e923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design, Y' q' v& s5 ]. u! Z0 N
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
* Y9 C& o9 Z( `0 }; Z7 D923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error: y$ F- U7 F3 |1 u8 Q+ o
924458 SCM OTHER Project > Export > Schematics crashes
% N4 {6 C9 N% b6 @924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
% K7 t4 w9 S }+ ]3 o925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect2 u7 u o' w& S+ U
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
8 l. ?2 T7 M( w" ]6 `7 F/ }+ {925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
$ g D& w' G. V3 |' I925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.# X9 P( H% \- m/ d
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
1 \- v5 d" \+ y4 ?; x; E# Z9 G925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS* t8 k. I8 s3 e. h- c2 p8 |% k- ^- d
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data% d- R2 t+ [) |3 l N4 A
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
% _# Q# P0 ~1 o; s# k2 m926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.0 ~( B" F& ?' X8 N7 Q3 Q6 B
926503 CAPTURE GENERAL Memory leak Capture/Pspice! C0 I* ^" b t3 z/ d# m% z5 H
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
/ k$ o! C! L/ h# U926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.4 y4 v1 x, q4 F% g- L
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical
( X. B% a& I0 H5 `3 ^' C ?927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''( j. Y1 Z K& T# O4 Q7 a+ {
3 Q- w' Q7 V) J' r1 ~% f
DATE: 08-19-2011 HOTFIX VERSION: 004
/ G2 y3 V- k3 D* g===================================================================================================================================7 L1 \* v) A2 W$ _
CCRID PRODUCT PRODUCTLEVEL2 TITLE: V- o; \5 e, j* e3 h
===================================================================================================================================' p% |- a2 P/ ]' p# ~
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
- [9 B8 s; K" J# v2 u7 W6 T851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window." R( S- h8 `; p9 X- l9 X
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments; @. p2 Q# d! n; P
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
9 \! l; t! W! A$ H: x% A8 k7 r877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form
' E8 F6 Q& j& S# N( J( J0 V894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window
& I" ^0 e% u. c% E0 V4 j9 c- F895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
* W# I8 A! b2 g* G. y895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement, m6 N' }; J/ K1 g# J
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.$ {% P( ?$ V- `# ?+ N
905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.; x) c* i# v# f% ]
909469 SCM TABLE ASA crashes when opening project" P5 A Y4 M# k0 S _& E, q
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap
- ?# R$ B9 p7 ~; m! J4 a911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
8 u9 N. P+ f! Y5 n$ Z9 S911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
8 I% M0 M1 M1 |( |915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability( ]; j* h' R0 @. M
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP
/ r l5 b" a; y3 p& Q916062 CAPTURE GENERAL Auto Wire Crashes Capture7 q9 N& V- J, M5 m0 y
916820 F2B OTHER RF create netlist with problem
8 E$ _) S1 U' m2 O# h- V: j3 E" }+ d917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only. ` o4 k0 f0 e ?
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file
& p! J6 q( d/ o$ m. P) u919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working
% X' ^. M2 |+ `) R+ H2 q% S919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL1 J9 F' q! n3 B2 _
919976 APD DATABASE Update Padstack to design crashed APD.: Z4 t" _' ?- ~4 @0 S
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition4 u# Y4 m$ f V" i! a; \
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run2 ^# X: I: J7 h- d
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork' t4 C* B3 y3 Q2 y. r, g4 |6 i8 {
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
* d9 P4 R) Q: t3 [4 x+ ~920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
+ E' b: j/ y1 J5 {- C920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
! k8 o' L! V, h+ [! n8 }' q921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
& {0 r" ]3 I) ~. W( a( p4 @" G# d0 k922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
5 P9 n* T! }# h1 A922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
! S0 Z! S( I( G5 H9 E+ T922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
" n' @( H# ?4 f. W9 X922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.6 f9 D6 \( A8 B, ~6 u H
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.# f1 Z; [$ |6 \. r. ]9 f
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf, c! C! I& D; P5 D% k/ s" v. t! \
% ], A; T/ o* }DATE: 08-4-2011 HOTFIX VERSION: 0036 b0 d; ]6 L8 `! v7 K
===================================================================================================================================4 I) W! P* H$ C3 y+ Q/ O& z" ^
CCRID PRODUCT PRODUCTLEVEL2 TITLE
5 k. @: f9 b. G- W% n===================================================================================================================================) T6 @, {' L$ V% |4 q
787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
- ]( C% K! T( g. w, M903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
$ A9 z/ E9 U) t2 L( C# W904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
. H5 D; p! g0 L; A' N# K+ c7 N904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result( t. C$ m, G5 n' B0 C& E8 n# d9 m
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged, w4 ?& p! {" G g
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed." E3 Q" c' J$ B) c2 V! |. Y+ Y! B
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
L% G* U8 h1 p* B909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.1 |8 d. P. V5 ]+ g' B6 E7 P
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
& W4 [; X4 n! |( C1 y910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
7 Y, g# s, K, R( R) P8 r' T9 C1 h911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
1 v) A/ ]& D( d4 }7 o" m- \" t912343 APD OTHER APD crash on trying to modify the padstack, j M4 X. c# ?) p
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys( p; {9 [. `, M- m1 Z! [+ s( E
912853 APD OTHER Fillets lost when open in 16.3.3 I1 _& V5 ~; H! ~4 H" X- {
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.4 ~2 b* ~6 k: }1 B
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
/ E- @& l* R9 a! V# x9 j7 N914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
2 O# Y( C/ p2 W914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
' u- h3 N, ?6 ^914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design
& m- M5 j0 n7 f" _& y5 m914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape2 L) F9 f2 m- Y$ F! G6 S
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.6 o' Q( a$ S( ]
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
9 S1 L+ R U9 H) y( [914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.6 G- c$ b" w5 L4 w$ w
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling
1 `3 W5 A3 n% y( x915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3* o' ]( m; {& ]6 e9 ^8 k
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
4 s1 w5 ?3 s, _8 H4 B7 ^- a915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol: j' u6 V4 D' p+ y5 E' q
916154 SCM NETLISTER scm crashes when exporting physical database to allegro) O" F; D. z7 n5 J% ]
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
6 d, {! `' r+ x( z' i916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
' e4 ^+ o# I( i916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report+ n1 a! D/ t1 f' _ c' v6 ~3 m
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
1 I6 j! S- e0 X \916889 CAPTURE NETGROUPS How to change unnamed net group name?
; \% K6 ]5 `# I/ y2 `917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film& m/ i0 f- J, _* X
917434 APD OTHER Stream out GDSII has more pads in output data.
3 {. |2 T6 y$ u/ p- n5 M5 ^$ i917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
. i/ ^+ Q9 D8 F918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
2 P9 Q# A3 I: l+ j* k918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
" L0 I' i: z( c, x2 c% n5 W) I
DATE: 07-24-2011 HOTFIX VERSION: 002
& S; @3 Z6 j% B6 y5 T===================================================================================================================================
, K1 e9 A, E0 x! x( [% z: HCCRID PRODUCT PRODUCTLEVEL2 TITLE- L6 s$ I% n4 a' T& S$ S! H: l
===================================================================================================================================/ W9 l9 E7 S# e& E
527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
Q6 S& T, X7 L5 U$ `; J583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
/ S) O4 `& T; y: K" _, R592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.) \, _' a! w% e8 f. x% e
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
* C& p# ]. e) u2 F9 g' l" z k773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
' J, U" d0 V% x1 N+ p+ s! a774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.4 S% r. G0 i# E, Z7 D2 F1 J/ H6 ~
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs8 [0 O, f/ w: Q Q Y( g- B% _
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".: D8 ~8 k# y0 {% Z8 S
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
& L: y: O N; S6 B6 S/ I821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format. p0 K- y: s" h( t, i: I5 }
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself+ j6 @0 \8 q. E, v9 I- R
842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.6 I. V2 Q3 d) R: u
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
! _, s" E1 d: _0 V; [! L860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
0 H, E* E4 S; b8 x% {8 L# [+ V867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"; D6 k9 F& T* y7 u- a
868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets8 M0 t6 z( a+ K) W5 q' y
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
- j$ r. V- v5 N4 N0 K: g" g( ~891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
1 ^2 r2 s: X# x( V2 p# Q7 o893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.' w* M6 G8 M& y
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.0 j& @- H) x* |4 |. L2 W2 W
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
. k" k3 b! z# N1 Y# x895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs t# x: y4 i- @; C/ s
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
0 C @2 ^) W' u3 N- a `897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
" Y: d0 q$ F2 g5 e8 B- D1 I) |898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
2 v0 `% D7 a6 ? x1 P( I# K899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
/ I3 c: ? f' A7 [900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5/ p+ i0 i$ ~! a& V4 h% E2 X
901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.
8 T1 O1 Y L3 m( W% e& ~2 T) S! F901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
/ a2 n1 y/ c9 q% D8 Q( y; O902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
8 k& z: G& P3 F! M% g9 d& P5 c- b+ {902349 CAPTURE LIBRARY Capture crashes while closing library6 K6 c2 e5 ~ o
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3. n5 F9 W% N6 P6 {9 {
902841 CAPTURE GENERAL Capture Start page does not show
$ n+ N: U' m0 U, q) }6 `# A902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5+ B" l" P4 h) t) M: E" B" @
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
0 l9 R) c) a" H& P7 h% T903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?; l4 T1 P6 c% J: L) ]$ j
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition
" W. R! J, M" n1 u0 a1 X4 F R, J903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
5 {* Y# k ^5 p4 z904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable3 U) S/ z$ H* h! Q
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE; H$ J- ~/ K4 ^; V
904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
: H' W+ L5 i, T7 |1 D904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
P& `% f* d# t- c8 c t* p904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
. l. ~4 J4 U! d% \/ p3 t! Q( o. l904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3; i: L" ]# C$ f$ `% ^& @
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM8 `: A6 y9 R+ j
905314 F2B PACKAGERXL Import physical causes csb corruption" p2 b: Z/ ]$ S( ?- x9 F% A
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
2 U, f; |2 _( K0 q5 P5 V: S905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
* T% ~* e! {/ a: q) W- y* ~# H905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues( _0 g7 i4 K8 O( d' s( m5 o+ V
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid( z, c! j" M; C; c
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
" J( L8 o& p) Z2 M- G906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
5 F! F6 r! ]% ~906182 APD EXPORT_DATA Modify Board Level Component Output format
/ A1 S- E! W' t* U6 k- Z906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element8 z/ |6 ^% c( L8 Y$ X9 N( t) `, I# f
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.- n" d; a' `: y; v3 p. G& h
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.. |: `" u; a7 ^% |4 R9 a
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
% U4 F# o. G* [; A906673 F2B PACKAGERXL Ignore the signal model validity check during packaging
9 ~8 p' S1 A1 e+ Y( U8 `+ F906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
% E- J& G( X! M/ _: g4 N/ r906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation0 a* ~; f. n! q* _
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
0 {9 e& L6 C6 g- L4 N# c- I4 z907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used2 f l% Y! k/ `& o
907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display4 `4 l) q( A) ~
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
! k, t: A; ~' s0 k; \907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
! Q5 s/ ~5 n$ W5 j! S3 L907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31: p* c& @7 p7 ^0 K: Q) U3 F' y) {; \
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly! V: ]0 V6 i) J3 }3 k4 X
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional* Z& Q0 U3 E; j8 M* K# Z) u
907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5* ^$ b3 Y7 y" {! e) s8 d
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.9 g4 ]) `% n }+ [# K
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name' o" F) S% a5 T! o
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
. E2 k8 u" n2 j! W: R908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
9 Y: ^- c! D& l. J: h$ {3 I3 \# |908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
5 j& v/ P! J, A4 }1 Z+ w3 ]! J908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place5 T8 V/ ] L# O5 @
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays, M5 V& z1 u& G R+ U
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes* v9 H) V% I4 }5 g; \. q1 {0 ]; x
908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
/ N! D H( ~1 W6 R- U908849 CAPTURE ANNOTATE Getting crash while annotating the attached design: W6 _. F+ U" P* R: t( W( U
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature5 f, v0 w' }4 x9 F
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN" Z& ~, T; B3 ~6 V
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem./ w$ c( a6 f" p0 x
909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux8 ^- w: Z7 N5 y, W0 U' X' R; C
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
( c F; E2 o2 y909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning2 [- ?( \6 E% |8 q) {7 z
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack; b r$ n: E& A/ I% c" @
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
5 U* [- {; ~, `0 h* H2 D, y& o910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
% m" n5 M) d! T. n4 F; w# b2 s910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
. H0 o+ F+ [1 N5 B910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
! ~. a& ~( k! q$ j' l7 |" w2 t0 l910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
& [! N- M" a' _ t2 s: B/ ^910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.8 G m$ J6 L% U0 W
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
9 k4 H+ v* M6 M# u+ X. v911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given" M3 B: m7 c/ f
911631 CONCEPT_HDL CORE DEHDL crashes when opening a design3 D. b0 t! m3 z0 ?6 h
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
2 m5 w* A% L% `" ~1 y3 P& q912459 F2B BOM BOMHDL crashes before getting to a menu
5 c+ _" R9 Y. n# l3 I+ I913359 APD MANUFACTURING Package Report shows incorrect data
. e0 P" Z n4 B1 {. T' t4 @
4 \) c; _, q6 eDATE: 06-24-2011 HOTFIX VERSION: 001
# Z) J: e {# T% \4 s===================================================================================================================================" g# F: {* ~) q9 g
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& I: E* f5 K. V===================================================================================================================================
1 `; u. E- |7 B3 s& Q1 z8 V/ b7 t293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
5 C& ~3 N* l7 W9 }1 H, z+ z4 d" V298289 CIS EXPLORER CIS querry gives wrong results
% Z- O3 n/ J) F( A! M# v366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
1 h8 _ d0 D$ {5 r4 X432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
* D+ _6 \1 Q2 k5 W1 v443447 APD SHAPE Shapes not following the acute angle trim control setting.
^9 V4 H" l7 N% k" M- V5 A Z/ }1 w3 ?473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam3 F0 e6 ]8 v ^* U0 I( S
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy4 y3 e& J) t& a1 R
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.# L" l0 @0 i4 w3 f$ c3 A8 `) e
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart7 `$ B4 Q' t# _% B# x
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled9 F6 q+ o" [% `' u. G. H
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
6 A z8 z& F% _3 S644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
' @2 J( q3 D. t645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board! z0 Q* L* J1 L1 O
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly., o3 o" `4 p7 T! G. X2 a
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
3 n3 L8 j @5 w" y l2 H/ K770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
% E2 i6 \) @0 N8 X% {792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets. l) `7 A/ Z0 }0 y9 l6 U
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write" s& M0 f' Q5 F5 m" j3 Z" y
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part" V7 a9 D$ j7 d' ^* V
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
) V) d6 ?5 ~. A+ \* Y5 w% o2 V* P1 Y809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs
' q" P. a; B$ I816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch( k3 t7 p% G }2 t" `; y
830053 CAPTURE STABILITY DXF export fails if schematic folder name as /% e4 j X3 M4 {
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.5 m9 e2 Y. ^/ {) d; X! [
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL3 [# E4 i) u H0 Y7 `8 k
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
1 k- k7 ~' b- g4 ~0 H837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version2 q+ \7 o! k7 D( d6 z' l# S0 l
844074 APD SPECCTRA_IF Export Router fails with memory errors.
% O: t+ ^/ a1 N, ^% p+ I851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
. v% l4 Z- b; h; G# H/ r" a( `* h852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?3 J( v, l- Y. M ?
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
. y' j& E1 m8 `9 f+ W7 p9 ~859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs9 S* f! s: v& m
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.( S0 F8 Z3 i" z$ g% Q
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line5 }- J; k% k5 B
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF/ f4 U; ~: u" W9 u* A
868618 SCM IMPORTS Block re-import does not update the docsch and sch view" l* i1 j/ ? H: O+ B
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
3 X/ M B7 s9 _+ n4 p874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.: F& _, [( ?& @5 R6 g: I
874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
' r; r5 H$ h5 n" B" }2 d( X874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file
2 u. D/ X" }; Q/ d% q875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1: P' [2 i4 E! L
876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
; r6 d: }1 J+ m& P2 k8 i879361 SCM UI SCM crashes when opening project) t5 }8 @6 a2 e5 _
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.% L1 |+ U3 E5 B6 [' }
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
" F: H) X. K; D' I0 g S4 ]0 d881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape6 x: x0 j: o7 X/ J
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets) f7 M; _5 L3 M9 t) E9 m) n
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier% i$ ]% G4 e) c1 e
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
! R) w0 j$ F; m {% X9 G# j882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement' \" \/ B4 T, }( h
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component4 Y5 N8 {' q- f; z* {/ ?
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
$ O: ]0 J y6 W883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
" S# i( N. l {+ e. i g$ i885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.$ Z, u, \. q' D; s! y T# r8 t
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
' U3 V/ J' z1 D' ^- S" g8 R885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations( E) T( M/ ^! ^2 l
886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid: @( b. [: q3 s- ^/ k. G
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
u! T, n* O: a9 \1 s, b& E# W887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.( Q6 d' z. L: c7 z
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message/ a" F* X: ^/ B& P9 c; y
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
+ X0 x9 |+ X$ X) h( S- y888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
% U b/ v& d0 B# Y! \5 g888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic3 \# I/ ~8 P& ^, l- [9 U/ g
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
7 }" a; c* e, r2 k3 z888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.8 `* l. i4 A4 i, n$ x* l1 g1 @* T6 ~
888945 CONCEPT_HDL OTHER unplaced component after placing module: y+ p U: L- L$ |
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.9 E7 L/ N6 |. h; s F: c
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.31 p, k/ o; q6 E. ]
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
$ D6 n! l1 J8 T7 M* g889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
7 e! n, ^* x' |889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
% Z6 ]2 A3 L: _( R891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file
. R3 C& E2 m2 I, a1 z/ Z891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance1 i+ K3 W. B/ Z
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
+ C3 N# ^. D |% G892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not., ?9 i( w2 o) y
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?- o# ^1 t: h. Q5 a6 d! h
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness0 |% B2 `( A3 k1 {7 H
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode- L# m! g3 ?' j( A* G
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations* G5 _& U& G1 R& S1 V: o# x" O
892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR- W# ^1 |+ L# Z
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
: s( h8 J+ F/ e2 _7 @893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.* T8 ]0 U5 ~5 ?! v. V0 }0 p
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
- e m" J. D( c+ ^3 C893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.9 t1 U8 F: ]4 C
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation3 V; ~$ }. e3 d; U
894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
( k8 o+ T$ N8 S' R* J4 i894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.% F3 c6 \. |) P/ U% [/ A5 v: j
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal./ E( a' y0 ^" X6 ]) h
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON6 n7 g& R7 X* C2 {
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
; H9 B; X6 N+ t1 h. n8 u; V* @895757 APD ARTWORK Import Gerber command could not be imported Gerber data) w# r- N; B( D" j6 C" R
895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
! T. I- p4 I- N( [$ B- {896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
6 Z" n4 K; H- f. E3 \896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture" C j0 k& n% Z9 K8 u+ e. A
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
* F7 g9 M6 r. B- u3 ^% @" {897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
: r( X8 v* ~& B. M8 Q f8 r, q897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design./ S0 Q8 E$ p* t2 e
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
/ w; Q& U, }0 W899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof( m, a- l' s P
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file., c+ H2 n' d. c6 G k% l& p% J
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
, E9 C8 y2 Q% Z$ D# p% P( ~& O900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
7 k" X& g k4 E% h900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.4 G2 m4 h. {; {4 L( u5 t" X& `8 W0 s; r
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
, l7 ^* x% h1 m6 [% C901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong! s# o$ ^- T! k& d' e
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page2 u9 N% Q$ z6 R& X( Y7 g' ^3 i: n# t4 f" Y
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic' m) P* f8 K9 u
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
1 o1 D6 @- _% h% z1 k$ g" g3 B902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
! M' Y4 d: {1 G5 V Y3 z3 x902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization, y" ]$ U6 r4 @& L5 d
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components6 i/ ]2 F+ o$ O7 q
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes
) S7 e- O9 F6 b9 |902909 APD WIREBOND die to die wirebond crash
" O2 q0 Y u2 c; k* L( T% V902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body1 F; O/ u' ] e/ Z& q' D7 C1 K1 {
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline$ i# j6 a- {2 I, ^. _- G
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
' N# G# V" e8 u' t" x" E! Q0 @9 Q904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2012-2-21 14:58
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
1
