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本帖最后由 yulizi 于 2011-12-22 11:18 编辑
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http://kuai.xunlei.com/d/DGOHIFKLICUP) z0 t! t; Z; J# ^. t5 G
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DATE: 12-16-2011 HOTFIX VERSION: 013+ \% s5 w _8 |, ]8 Q) v
===================================================================================================================================+ P6 _* a9 R: c1 n- u. b$ m
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ M$ F& d+ [4 t4 z2 S. l- N" G===================================================================================================================================. Q a! ^7 e$ F' n/ [0 [5 {' I
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.4 ^7 K) L% I% q J. E0 u9 j
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design' k8 C- G. e7 a4 [# ~
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT3 M( ?- X5 n% Y) U" H" y* P
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
; @+ r( M3 _. ?" q3 j; G) O9 P6 p945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command* N' ?& k5 p1 J5 b; y0 y# u
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
7 N: o8 ?8 o8 b: Z% r: x) t946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus.8 A8 m' C' a4 W! ^& b: R
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
! [' H, j* J' e) v, _/ K$ }& }953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.3 P C6 v8 X* v7 z3 j7 R$ P' o3 @
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block& B2 a5 W; _6 O
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
) [* H1 C6 a4 k5 n y7 d$ M$ a* D953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?5 u0 R: Y" E C' }
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.( [7 J* R( r0 O. g6 b
954498 SCM B2F SCM crashes when importing physical+ i3 F e- K# b' m" z" @8 [3 a
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
6 E+ Y! r/ Y2 s6 O" t954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3, {3 O, D2 N, l0 N3 h9 h2 q
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
+ X& v, p6 y4 ] j1 A0 u955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.# _% Y1 q3 `# e8 S+ M5 ?0 \
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
' s" z6 a* ]2 {, o$ A955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
6 S" r7 x* p* k' |2 ^; A5 C6 n3 k955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
9 |/ h3 N/ k1 V% ~ ~955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
4 K# ^1 y L. t. h& g. i" w) ^955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly4 o- E j2 g6 n6 X* x
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
i) Q3 f/ F- b, H. W3 Z3 L955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void) A; Y7 e) I& l% K7 Y
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
( w) ]# l$ i( u956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
2 t6 D4 ~: u- _" [6 F" ^% b: ~956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
2 j# j! V# C. T" f9 q* m7 V956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found9 W& I8 B5 C- [' M3 C+ K
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined4 n4 A) t+ i1 i5 p! T% |/ t2 p
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board) g$ V2 r1 N a# X) O0 @+ `
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
0 Q& h# m6 P2 K! w5 v2 O4 r/ v956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly# O; e5 d* G1 ~- \ |( Z
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
# D- z4 H0 h' Q. P3 |5 p/ j956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results( t5 S7 q- ]. G% G0 J6 Q5 I
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty; o# ~ ]4 B/ A, ^
957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist
1 \4 t8 ]8 s! q0 ~/ L1 H& s/ m" I, B957137 APD DXF_IF DXF out command dose not work correctly.
: x: H1 O- H: A' M0 `957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.3 t0 a' x; o. t L
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.
# ]2 {; k7 {* N6 ?7 R+ |( P5 L% j8 T957267 CONCEPT_HDL INFRA Packager Error after Import Design/ g$ Y' f+ F$ D1 h/ q. @
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file! s( v: P" J% Z" b. p7 X- X
958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files." U: ]! T, f* z1 t, m0 y* k
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design4 x: F2 O" i% }# g
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
7 g# g( n9 B, Q0 _ j6 \958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs! N! u7 r) x8 V& h; y. R5 ~
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5- }9 o! {' Q, u( K! d" I' t
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline4 K% D6 v& y0 h. t- X" ~$ s
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs4 n5 T/ f' e5 r2 H
959253 CONCEPT_HDL INFRA Design will not open
! J% y0 u- \+ }1 F6 s3 g959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side; [6 P0 J7 a9 Z- B& k
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
! H, x3 u. C' y+ m959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
: [4 u; E$ e( P; Z2 H4 ]960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
9 b5 [& H1 h/ J2 g* E N960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.! k; f1 i- A0 F/ X; O! Z, S- l3 O
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter! p2 _) E$ g' \& U2 q& i
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
/ ~$ q c( @6 X' C7 ~; `, m4 I961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol2 s: H* r! T; c) q$ O
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
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