有关时钟抖动

stupid · 发表于 2011-4-8 08:58

EDA365欢迎您！

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大家先看看这个帖子
https://www.eda365.com/forum-viewthread-tid-34298-highlight-%B6%B6%B6%AF.html

大家可以重点思考一下，时钟DCD从何而来，如何控制，PJ和BUJ又如何影响时钟。

stupid · 发表于 2011-5-24 12:02

本帖最后由 stupid 于 2011-5-24 12:06 编辑

Tutorial: Clock jitter measurement and effects
Rohit Mittal5/23/2011 7:07 AM EDT

Clock jitter is a parameter which affects system performance and can degrade otherwise superior component specifications. This article is a basic explanation of clock jitter and some of its effects, especially with respect to a phase lock loop (PLL).

At a very fundamental level, jitter is defined as the variation of a signal (in this case a clock output) from its ideal position in time, Figure 1.

Figure 1.Basic definition of jitter aspects

In an IC, a PLL (frequency synthesizer) is typically used to generate the clocks.

Jitter in clocks has two different components which arise due to various sources.

(a)
Random jitter (Rj). Rj arises due to thermal noise inherent in the system and exhibits a etermin distribution. Since Rj is unbounded it is characterized by its rms value. In a PLL, the low frequency RJ typically comes from the reference clock and Charge pump whereas the high frequency jitter is more a manifestation of the VCO thermal noise.
(b)
Determinstic jitter (Dj). Dj arises due to eterministic components. Examples include: PLL reference freedthrough, Power supply noise etc. Unlike data, there is no Intersymbol interference (ISI) term. Dj is bounded and specified as a peak number

This deviation from its ideal position can negatively impact data transmission between two clocked elements on-chip as well as off-chip. Example of on-chip systems includes timing violations between two flip flops.

Example of off-chip systems include a Serdes I/O (serializer/deserializer) link where data is sent over long traces of FR4 PC-board substrate. Excessive high-frequency jitter on the clock used for transmitting the data can cause eye closure and excessive bit errors (bit error rate, or BER). In either case different types of clock jitter cause the errors mentioned above.Hence it is critical to understand what type of jitter is important for ones application and how to measure/analyze them.

Jitter Measurements–time and frequency interplay

Jitter can be measured in two different ways: in the time domain and in the frequency domain.

Time-domain measurement is implemented using a low-noise-floor, real-time oscilloscope. Such a scope samples the clock and looks at the deviation of the zero crossing from an ideal clock. (Note, since no reference clock is input to the scope, the ideal clock is actually a derived clock and is an average of the time period of the jittery clock over a large number of clock cycles).

The time domain deviations can be post-processed to derive other types of jitter. Fortunately most advanced scopes include a jitter package which makes the computation much easier.

Frequency-domain measurement typically uses a spectrum analyzer. A spectrum analyzer mixes the input jittery clock with a "clean" reference clock, and then displays the shifted spectrum of the signal (after some filtering to get rid of harmonics and other artifacts). While an ideal signal will just have one tone, a real signal will have skirts around it (due to Rj) and possibly low-amplitude tones or spurs (due to Dj), Figure 2.

Figure 2: Frequency-domain measurement of a signal showing jitter-caused spurs

This is an exciting field with new instruments coming to market, such as signal source analyzer, which can measure open-loop responses as well.

An astute reader might wonder why bother about frequency-domain measurement when clocks are just used for timing elements. There are two main reasons for it:

(a)
Certain applications actually specify their compliance in frequency domain. One major application is RF: GSM, WiFi and similar. For example, GSM requires the phase noise and spur level to be lower than -128 dB/Hz and -68 dBc in the range of 600 kHz to 1.6 MHz offset.
(b)
Instruments used for frequency-domain phase noise analysis are typically more accurate than time-domain ones, especially in the region of high phase noise. Scopes suffer from timebase jitter as well as drift if it is necessary to take a larger sample size. (An excellent reference isReference 1). A spectrum analyzer uses a very-low-noise oscillator to mix with the input data. A noise floor as low as -170 dB/Hz at larger offset frequency is not uncommon.

It is possible to convert between time and frequency domain. Integrating the phase noise over a frequency range gives total rms phase jitter (with a normalization factor). A valuable byproduct of this duality is the possibility of using spectrum analyzer to accurately measure jitter in the frequency domain, and then to convert into a time domain number, rather than using a higher noise-floor instrument such as a scope.

Jphase is the deviation of VCO output edges from ideal placement in time (Reference 2):

Jperiod is the deviation of VCO period from ideal period. It is the derivative of the Jphase in time. This manifests itself as a sinc() function, (Reference 2):

Where Fvco is the frequency of oscillation

And S(f) = 2L(f) is the dual-sideband phase noise

The integration period varies from standard to standard. For instance, PCIe specifies a lower limit of 1.5 MHz. The upper limit can be taken as half of reference frequency to make sure there is no aliasing effect.

Converting the spectrum into a Jphase rms ps number can be cumbersome since the phase noise has different regions (1/f3, 1/f2. 1/f etc) necessitating numerical integration in small increments. In addition, correction factors to take into account resolution bandwidth (RBW) need to be added in. Fortunately, newer instruments take the complexity out of the equation and spit out the correct ps rms number.

Unfortunately, there is no such package for Jperiod. Therefore, Jperiod typically involves post-processing the spectrum analyzer data with a sinc() function.

Jitter Effects

Now that we have a good understanding of measuring jitter, we need to find out which type of jitter is important for which application

a)
In digital on-chip systems, it is the period jitter that is important. What we are most concerned about is whether the data delay from one flip-flop to the receiving flip-flop can tolerate a clock time period made lower by jitter. Therefore, in this case only high-frequency jitter (ie jitter which changes from within one clock period) is important. MTBF, RJ multiplication, and random period jitter are much less than rms jitter (which is integrated over the whole spectrum of phase noise). So if one considers just a PLL datasheet, quoting rms jitter it will likely be misleading and erroneous.

b)
In communication systems (off-chip) the data is typically sent over long distances of FR4 traces. At the receiving end, a clock data recovery (CDR) circuit recovers the clock from the data and re-generates the data. In such a system, the untracked jitter between derived clock and received data is more important, and can span several cycles of clock. Unlike the on-chip digital systems.

c)
RF systems depend upon the rejection of close-by interfering signals from the main signal path. The interfering signal gets mixed with the “skirts” from the oscillator. In such a case, the phase noise of the PLL is the critical parameter.

In some other types of communication systems (off-chip) the clock is sent with the data. In a way, they lie between (a) and (b) systems mentioned above. For the same BER and specifications, the requirements for PLL jitter are less stringent than systems with only an embedded clock.

Now that it is known which application stress which portion of the jitter spectrum, methods to cost-effectively mitigate them can be considered. For instance, the power-supply impact on jitter is not important for the first application (as long as there is no likely scenario of multi-GHz power-supply spikes).

However, such noise can have large impact on the second application, since a typical CDR bandwidth will only be in the tens of MHz range. In addition, a step response on the power supply will accumulate jitter until it gets corrected by PLL bandwidth. This will typically necessitate a regulator for such a PLL, causing additional area and power penalty. Even in the first application, a regulator may become necessary if there is requirement to cross from one clock domain to another, since long-term jitter starts to become important in that PLL.

Conclusion

PLLs are used everywhere, from within chip clocking to wireline data communication and RF systems. It is imperative to understand which particular application into which your PLL is going. Failure to do so will invariably lead to over-design or system failure.

References

1.
Brig Assay, "Understand the jitter specification in oscilloscopes",Planet Analog, April 1, 2011.(http://www.eetimes.com/design/analog-design/4214688/Understanding-the-jitter-specification-in-oscilloscopes)
2.
http://www.delroy.com/PLL_dir/DL2007/PLL_tutorial_slides_July07.pdf

About the author

Rohit Mittal is a passionate follower and practioner of analog/mixed-signal IC design. He has over 15 years of experience in this area with MSEE from Carnegie Mellon and BSEE from IIT Delhi, India. Rohit has 8 products (and about 100 derivative products) in high-volume production. He has worked on technologies ranging from 0.6μm BiCMOS to 32nm CMOS to SiGe and BCD. He has co-authored 7 IEEE journal papers. All of his designs have been sample-worthy on first silicon.

honejing · 发表于 2011-4-10 10:00

文中所提 DCD 的由來與幾個防治方法，清楚易理解，但是除了這幾點外，在高速的 channel設計中，是否還有其他會引起 DCD 的因素？

Common causes for duty cycle distortion (DCD) include trace mismatches (differential signaling), or mismatches in either the push-pull transistors on the driver and/or receive threshold mismatches. Minimizing jitter due to DCD involves using careful layout techniques as well as selecting good clock buffers. Some effective countermeasures for crosstalk include using differential signaling and shielding.

stupid · 发表于 2011-4-8 14:47

Signal Chain Basics #45: Is high-speed ADC clock jitter being over-specified for communication systems?
Robert Keller, Systems and Applications Manager, High-Speed Data Converters, Texas Instruments9/2/2010 2:27 PM EDT

There is a well-known relationship in analog-to-digital converters (ADCs) between the sample clock jitter and the resulting ADC signal-to-noise ratio (SNR) degradation (derived in reference 1), Equation 1:

SNRjitter(dBc) = 20 * log10(2 * p * fIN * tj)

where tj is the RMS jitter (typically in picoseconds or femtoseconds), fIN is the analog input frequency, and SNR jitter is the ADC SNR, if the only noise source is clock jitter. The total ADC SNR includes other noise sources such as thermal noise.

Here are some interesting points regarding Equation 1. First, there is no direct dependence on sample frequency. However, the integration of phase-noise to calculate jitter depends on the sample frequency. Also, since the RMS jitter value is the integrated phase-noise across frequency, the phase-noise dependence frequency dependence is lost in the analysis.

Using the RMS jitter effectively averages the phase-noise across the entire ADC output bandwidth, regardless of the actual phase-noise spectrum. Since the clock phase-noise typically decreases with increasing offset frequency, the noise due to clock jitter is highest near the large signal frequency.

This is the case when a band-pass filter is used on the clock signal, as described in Reference 2, where a crystal filter removes the clock phase-noise above ~100 kHz. This is illustrated in Figure 1, when the phase-noise is integrated in the wanted signal bandwidth, the noise estimated using jitter results in a higher estimate than integrating the in-band phase-noise.

Figure 1: ADC spectrum for a large blocker and small wanted signal.
(Click on image to enlarge)

How do you translate clock phase-noise to the ADC output noise? To demonstrate the relationship, we create a known level of phase-noise and measure the ADC output spectra. A 250-MHz clock with noise is generated using a high-speed DAC, such as the DAC5681 16-bit/1Gsps, and input as a clock for the ADC, using the ADS4149 14-bit/250Msps. The DAC pattern and capture size are set so the bin resolution in the DAC and ADC FFT’s are equal in size.

The DAC output pattern in Figure 2 consists of a 250-MHz tone and –60 dBc of random noise from 240 to 250-MHz. In a typical clock, the phase-noise is symmetric around the clock, but for clarity we use a single-sided noise.

Figure 2: 250-MHz clock with –60dB noise.
(Click on image to enlarge)

The ADC output using the DAC generated clock for input frequencies of 10 and 100MHz is shown in Figure 3. The clock phase-noise energy is mixed in the sample process with the input tone and is symmetrical around the carrier. For the 100-MHz input tone, the noise due to the clock phase-noise is ~71dB across ±10 MHz from the tone. For the 10-MHz input tone, the noise due to the clock phase-noise is ~91dB (per FFT bin). This is consistent with the SNR jitter equation, which predicts a 20-dB change with 10 times the input frequency.

Figure 3: ADC output spectra.
(Click on image to enlarge)

The ADC noise from the clock phase-noise can be described by Equation 2:

ADCNoise(fOFFSET) = – Phase-noise(fOFFSET) – 20 * log10 (fIN/fCLK)

where fOFFSET is the offset frequency, phase-noise is the one-sided phase-noise density, fIN is the input frequency, and fCLK is the clock frequency. Note that the units of phase-noise and ADCNoise are the same, i.e., dBc/Hz.

Returning to our example in Figure 3, the ADC noise at 100MHz of –71dB is 11dB lower than clock phase-noise of 60dB, –8dB is from the fIN/fCLK term in Equation 2, and 3dB is due to the clock phase-noise being on one side only, rather than symmetrical.

When used for specifying the required phase-noise for the ADC clock in communication systems, the ADCNoise should be integrated across the bandwidth of the wanted signal at the blocker offset to calculate the total that falls in the wanted signal (Figure 1).

The ADC clock phase-noise spectrum translates directly to noise in the ADC output with the same offset spectrum. Therefore, using jitter to calculate SNR is a simplification that often results in over specification of ADC clock phase-noise requirements.
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Conclusion
Join us next month when we will discuss clock jitter specifications in high speed serial data links.7 X+ Q5 k: ?4 _4 L; `, G

References

1.
“Clocking high-speed data converters,” by Eduardo Bartolome, Vineet Mishra, Goutam Dutta, and David Smith, Texas Instruments, 1Q 2005.

2.
“Implementing a CDC7005 Low Jitter Clock Solution for High-Speed High IF ADC Devices,” by Russell Hoppenstein and Firoj Kabir, Texas Instruments, December 2004.4 b$ h- d* }' [% b4 {

About the Author. M8 g: O7 h. O9 d) [; ]+ h( O
Robert Keller is the Systems and Applications Manager for High-Speed Data Converters. He has nine years experience supporting high-speed products in wireless infrastructure communication, test and measurement, and military systems. In 1988 he received a B.A. in Physics and Mathematics from Washington University in St. Louis, and a Ph. D. in Applied Physics from Stanford University in 1993. He has 10 US patents in networking and sensor applications. Robert can be reached at ti_scb@list.ti.com.

stupid · 发表于 2011-4-8 09:44

本帖最后由 stupid 于 2011-4-8 09:52 编辑

Understanding the effect of clock jitter on high-speed ADCs (Part 1 of 2)
Derek Redmayne & Alison Steer, Linear Technology Corp.8/12/2008 12:44 PM EDTDigitizing high-speed signals to a high resolution requires careful selection of a clock that will not compromise the sampling performance of the analog-to-digital converter (ADC). In this article, we'll give you a better understanding of clock jitter and how it affects the performance of the high-speed ADC.

As an example, we will highlight the latest high-performance ADC from Linear Technology, the 16-bit, 160 Msps LTC2209. This converter exhibits a signal-to-noise ratio (SNR) of 77.4 dB, with 100 dB spur free dynamic range (SFDR) throughout much of the baseband region.

Like most high-speed ADCs on the market today, the LTC2209 uses a sample-and-hold (S&H) circuit that essentially takes a snapshot of the ADC input at an instant in time. When the S&H switch is closed, the network at the input of the ADC is connected to the sample capacitor. At the instant the switch is opened, one-half clock cycle later, the voltage on the capacitor is recorded and held.

Variation in the time at which the switch is opened is known as aperture uncertainty, or jitter, and will result in an error voltage that is proportional to the magnitude of the jitter and the input-signal slew rate. In other words, the greater the input frequency and amplitude, the more susceptible you are to jitter on the clock source. Figure 1 demonstrates this relationship of slew rate being proportional to jitter.

Figure 1: Slew rate exacerbates the effects of clock jitter.
(Click on image to enlarge)

Describing a clock as "low jitter" has become almost meaningless. This is because it means different things to different interest groups. For a programmable logic vendor, 30 picoseconds, or even 50 psec, is considered low jitter. In contrast, high-performance ADCs need a clock with jitter under1 psec, depending on the input frequency.

More precisely, spectral power distribution of the sampled signal is the determining factor, as opposed to simply the highest frequency component, unless a full-scale signal at the upper end of the spectrum is expected. For a simplistic example, a uniform band of power from DC to 1 MHz is 6 dB less sensitive than a single tone, or a narrow band, with equivalent power at 1 MHz.

There are various contributors to jitter in any scenario, extending from the oscillator to any frequency dividers, clock buffers and any noise acquired due to coupling effects, in addition to the internal aperture jitter of the ADC itself.

The internal aperture jitter of the LTC2209 is 70 femtoseconds (fsec). For the level of performance exhibited by the LTC2209 and other members in Linear Technology's high-speed 16-bit family, 0.5 psec jitter (the best available from many oscillator vendor) may produce discernable compromise in SNR for some sampling scenarios. It is not the ADC but the sampling scenario that dictates the required jitter performance.

Any ADC that exhibits 77 dB SNR at 140 MHz input frequency would require the same jitter performance to achieve full data sheet SNR. It is the input frequency, not the clock frequency, which is the determining factor with respect to jitter performance. On the LTC2209, a clock that has 10 psec jitter would cause a loss of only about 0.7 dB SNR at an input frequency of 1 MHz. At 140 MHz, the SNR would degrade to 41.1dB.

Figure 2 demonstrates the effects of clock jitter on the SNR of the LTC2209 as a function of sampled input frequency, with a family of curves of increasing clock jitter ranging from a perfect clock to 100 psec of jitter. At 100 psec, the ADC SNR begins to degrade with input frequencies of only 200 kHz!

Figure 2: Jitter degradation of SNR as a function of input frequency.
(Click on image to enlarge)

The theoretical limit on SNR resulting from clock jitter is:

where fin is the input frequency and σ is the jitter in root mean square (RMS) seconds.

The jitter-related noise power is proportional to the input power (dBFS). As the input level is raised or decreased, the noise component related to jitter changes accordingly, For example, if we have a -1 dBFS input signal at a 70 MHz IF, sampled by a clock with 1 psec jitter, we can expect an SNR of 68 dBFS. At -5 dBFS, the noise component related to jitter would drop 4 dB to an SNR of 72 dBFS.

To calculate the total SNR degradation, we add the jitter-noise power to the published SNR of the ADC,

(Click on image to enlarge)

Understanding clock oscillator jitter specifications
Clock oscillators are usually specified in terms of spectral density of phase noise in dBc/Hz. An oscillator output can be decomposed into an amplitude term with associated amplitude noise and a frequency term with associated phase noise:

The spectral density measurements assume the AM component ε(t) of the noise is negligible compared to the phase noise component φ(t). This is a reasonable assumption with any quality frequency source.

The spectral density denoted as L(f) is stated as the ratio of the single-sideband phase-noise power in a 1-Hz bandwidth at an offset frequency, also called the Fourier frequency, relative to the carrier power:

(Click on image to enlarge)
Jitter is the integral of spectral phase density with respect to frequency between two limits in frequency, and expressed in time:

(Click on image to enlarge)
The result is frequency independent.

Most oscillators that rate jitter are rated between 12 kHz and 20 MHz. This is due to historical reasons related to optical communications and is not applicable to most other practical cases. Performance may, in fact, fall apart beyond these limits, so take care not to be lured in without careful examination.

For many oscillators where close-in phase noise dominates, the lower limit has the most impact on the published figure. While this expression is convenient, as it yields a single number useful for calculation of ADC SNR degradation, it is not as informative as the spectral density.

For example, two oscillators having different spectral content may have the same jitter over the same integration limits but may not produce the same SNR. Elevated wideband noise may not produce a poor jitter spec, but will degrade SNR. Close-in phase noise causes the fundamental signal to spread into adjacent frequency bins of an FFT, thereby reducing dynamic range, whereas broadband phase noise will uniformly elevate the noise floor throughout the entire Nyquist zone, thus reducing the overall SNR performance of the ADC.

Jitter does not affect SFDR unless the clock also contains spurs. The lower frequency limit of integration should correspond to the frequency resolution of any manipulations of the sampled data as the size of an FFT increases, for example.

Figure 3 shows the effect of band-limited clock jitter related to phase modulation of two signals of similar amplitude, but of different frequencies. This illustrates the exaggerated effect of both random phase noise and phase modulation of the clock in the presence of higher input frequencies. The clock input of the ADC should be regarded as the local oscillator port of the ADC, not a digital control signal. Anything present on the clock, including wideband noise extending to GHz frequencies, will mix with the input signal.

Figure 3: Effect of band-limited clock jitter related to phase modulation of two signals of similar amplitude, but of different frequencies.
(Click on image to enlarge)

(Part 2 will look at how the application, not the ADC, determines the clock-jitter need; selecting an oscillator to drive high-speed ADCs; and clock sources and architectures. You can read it by clicking here.)

Conclusion
The impact of jitter on ADC performance is a function of input frequency (slew rate), not sample rate. The choice of clock source will be determined by the application. Don't always believe the clock-source vendors. Test your clock sources with your ADC evaluation board before it is too late.

Related articles

"Added resistor preserves crystal oscillator's low output jitter," Dr. Gary Giust, PhaseLink Corp.
"Understand analog/digital converter clock jitter--and why you should care,"Bill Odom, Applications Engineer, National Semiconductor Corp.
"Enhance circuit timing design with programmable clock generators," Lin Wu, Product Marketing Manager, Texas Instruments$ B$ F# m/ q/ [

About the authors
Derek Redmayne is a mixed-signal applications engineer, and Alison Steer is a product marketing manager, both at Linear Technology Corp, Milpitas, CA.

Understanding the effect of clock jitter on high-speed ADCs (Part 2 of 2)
Derek Redmayne & Alison Steer, Linear Technology Corp.8/14/2008 12:00 PM EDT(You can read Part 1 here)
The application determines the needs, not the ADC
Applications which are receiving weak signals which are in close proximity to strong tones, such as.static reflections in Doppler ultrasound, radar, and RFID, are sensitive to close-in phase noise. Conversely, when digitizing a CCD output, jitter generally doesn't matter due to the low slew rate at the point in time at which sampling occurs. Video applications are also not very sensitive. For example, in HDTV the sample window is approximately 6400 psec (time per pixel).
High symbol-rate communications applications are generally not sensitive to close-in phase noise, and may not be overly sensitive to the effects of wideband phase noise. High crest-factor waveforms (WCDMA OFDM) with relatively even power distribution have a low RMS power level, and also require headroom, so will not elevate the noise floor as much as a full amplitude single tone. However, higher-order modulation types, such as QAM and M-nary phase modulation, are more susceptible to noise and have more narrow carrier-recovery loop bandwidths for the same symbol rates as, for example, QPSK used in CDMA systems.
A digital radio where strong interferers (single tones) may appear in close proximity, or may be much stronger than the signal of interest, is generally demanding in terms of close-in phase noise, and may be sensitive to wideband phase noise. As any wideband signal source tends to have a high crest factor, and requires headroom for interferers, the nominal power at the ADC may be low. The characteristics of the band of interest must be taken into consideration in deciding on a clock source.
Selecting an oscillator to drive high-speed ADCs
Most oscillators will have close-in phase noise that will limit the dynamic range close to a strong fundamental. If close-in phase noise is important, based on your dynamic range requirement in proximity to strong tones, you may need a phase locked loop (PLL) to reduce the close-in noise of your oscillator source, or to lock your oscillator to an accurate frequency reference. The use of a PLL as a jitter cleaner essentially provides a very narrowband tracking filter.
Your choice of oscillator will dictate your loop bandwidth, as well; your desired loop bandwidth will dictate the oscillator. A voltage-controlled crystal oscillator (VCXO) requires only a narrow loop bandwidth to track a stable reference. VCOs can provide wide tuning range, but need wider loop bandwidth in order to reduce their close-in phase noise to acceptable levels.
If you only require a very restricted tuning range, perhaps locking to a reference oscillator, the use of a VCXO is the best option. If you need the octave tuning range of a VCO, and need low close-in phase noise, you may have a problem, especially if you need high divider ratios and low reference-comparison frequencies in your PLL. Figure 4 shows a real VCXO phase noise plot, compared to a typical VCO.

Figure 4: Comparison of VCXO versus hypothetical VCO phase-noise performance
(Click on image to enlarge)

The optimal loop bandwidth for the PLL is suggested by the intersection of the noise density of the reference oscillator as multiplied by the center frequency, and the phase-noise plot of the VCXO or VCO. The example would suggest 2 kHz for the VCXO, and 300 kHz for the VCO. A 300 kHz corner requires a comparison frequency of at least 3 MHz, which suggests 5 MHz.
The VCXO could be used with a comparison frequency as low as 20 kHz. If a lower frequency reference were used (high divide ratios) with the VCO, the intersection of the multiplied phase noise with that of the VCO would be at a lower frequency, substantially increasing the jitter. The use of an excessively low loop bandwidth with a lower multiplication ratio will cause the phase noise of a VCO to remain within the loop bandwidth. If your application is insensitive to close-in phase noise, and does not need to be locked to a reference, an XO can be used.
Clock sources and clock architectures
A good clock can be compromised by routing it through an FPGA where internal crosstalk is prevalent. FPGAs often maximize their input/output connections (I/Os) at the expense of ground pins, resulting in ground bounce. If the FPGA is driving outputs at different rates, these will manifest themselves in any clock routed through the FPGA, and ultimately on the output of any ADC using that clock.
A low-noise flip-flop clocked by the clean VCO signal can be used as a retiming stage to eliminate jitter when an FPGA is used to frequency-divide the VCO. The FPGA can be used to implement a narrow-band PLL for an external VCXO, with an external loop filter, and a loop-filter driver protected from reflected ground bounce from the FPGA. Do not use a digital lock loop (DLL) to produce a clock for an ADC unless you are over-sampling the audio band.
A good clock can also be compromised by routing it among digital signals. Any clock originating at any distance from the ADC must be routed through a conduit of copper and vias. Figure 5 shows examples of good and bad routing of clocks. The bad cases are where the clocks are within cavities shared with digital signals.

Figure 5: Example of good and bad layout for clock routing.
(Click on image to enlarge)

Conclusion
The impact of jitter on ADC performance is a function of input frequency (slew rate), not sample rate. The choice of clock source will be determined by the application. Don't always believe the clock-source vendors. Test your clock sources with your ADC evaluation board before it is too late.
Related articles

"Added resistor preserves crystal oscillator's low output jitter," Dr. Gary Giust, PhaseLink Corp.
"Understand analog/digital converter clock jitter--and why you should care,"Bill Odom, Applications Engineer, National Semiconductor Corp.
"Enhance circuit timing design with programmable clock generators," Lin Wu, Product Marketing Manager, Texas Instruments
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About the authors
Derek Redmayne is a mixed-signal applications engineer, and Alison Steer is a product marketing manager, both at Linear Technology Corp, Milpitas, CA.

stupid · 发表于 2011-4-8 09:19

本帖最后由 stupid 于 2011-4-8 09:53 编辑

SIGNAL CHAIN BASICS #46: Basics of clock jitter specifications in high-speed links (Part I)
John Johnson, Manager, Market Development and Systems Engineering, Texas Instruments10/11/2010 12:02 AM EDT

(Editor's note: click here for a complete, linked list of all previous installments of the Signal Chain Basics series.)

Signal Chain Basics #41, Clock Jitter Demystified, helped you to gain an understanding of the basics of clock jitter. This two-part article deals with the basics of the impact of clock jitter on high-speed links. This article, Part 1, provides the foundational concepts of high-speed communications links. Part 2 will address the communications link budget from a clock jitter perspective.

Clock jitter specifications that pertain to high-speed communications links are a confusing mixture of terminology and numerical values. In order to decipher these specifications, a basic understanding of communications link architectures and clocking mechanisms is essential. The purpose of any communications link is to convey data across a transmission media with acceptable performance. Typical link performance parameters for any given media/communications environment includes data rate, transmission distance, and bit error ratio (BER).

Figure 1 shows a basic communications link comprising a transmitter, a medium of data propagation, and a receiver. The receiver includes a signal threshold to differentiate between a ‘1’ and a ‘0’ and a clocking mechanism, so that the time slot that each individual symbol occupies is identifiable.

Figure 1: Basic serial communications link
(Click on image to enlarge)

High-speed links commonly use a serializer/deserializer (SerDes) (Figure 2). The serializer multiplies the frequency presented on the transmit clock (TX CLK) port using an internal phase-locked loop (PLL). For clock recovery to separate the embedded clock from random data, the receiver must encounter a minimum density of edges; which necessitates schemes like 8B10B coding or data scrambling.

Figure 2: High-speed link – embedded clock
(Click on image to enlarge)

As the data traverses the media, discontinuities cause reflections, and cross-talk injects noise. The typical frequency response of a long transmission line is low pass, which causes problems in a system that relies on the timing of high-frequency signal content (edges). Additionally, the TX CLK oscillator injects noise into the system. Many modern communications links must achieve at least10-12BER (for every 1012 bits received, the receiver misidentifies only one of them).

An embedded clocking application has several jitter entry points (Figure 3). With respect to clocking, the SerDes multiplies the reference clock so that the link achieves the desired data rate. For example, a SerDes uses a 78.125 MHz clock to generate a 3.125 GHz link; therefore, the SerDes PLL multiplies the reference oscillator by 40 to attain the internal clock required. The phase noise of the transmitter clock (TX CLK) oscillator and the characteristics of the transmitter PLL (TX PLL) play a big role in clock jitter budgeting.

Figure 3: High-speed link – jitter entry points
(Click on image to enlarge)

This is because the TX PLL passes certain noise components from the TX CLK oscillator onto the data stream, and the noise contribution of the TX PLL feedback divider is proportional to the square of its multiplication factor (e.g., 402 = 1600).

Transmitter
The frequency response of a PLL is low pass. If the TX PLL loop bandwidth is f2, then noise above this frequency is passed through to the transmission media along with the in-band noise that is dominated by the TX CLK phase noise.

Receiver

The RX jitter responserepresents the bandwidth of the random noise passed by the TX CLK through the TX PLL and transmission medium. The loop bandwidth of the receiver clock recovery PLL (CR) is f1 (RX PLL BW). Therefore, the RX jitter BW represents the frequency band between the bandwidths of the TX and RX PLL. For example, the jitter measurement for SONET OC48 is 12 kHz – 20 MHz. From a clocking perspective, this area has the greatest impact on link performance bit-error-rate (BER), and often is dominated by the TX CLK noise content. This jitter measurement bandwidth is an integral part of the specifications for many communications standards including SONET, SDH, and fiber channel.

Link Budget
The transmission line contributes deterministic jitter only. All other elements comprising the communications link contribute both random and deterministic jitter to the overall jitter budget. In theory, the total budget must stay below one unit interval (1 UI) for reliable communication.

When Part 2 is published, it will address the overall link jitter budget for a high-speed communications system and provide specific examples of link budget calculations.

Joint us next month when we will talk about the life expectancy of digital capacitive isolators.

SIGNAL CHAIN BASICS #51: Clock jitter demystified—Basic specifications in high-speed links (Part 2)
John Johnson, Manager and Market Development and Systems Engineering, Texas Instruments3/25/2011 4:06 PM EDT

(Editor's note: Click here for a complete, linked list of all previous installments of the series.)

This article addresses the impact of clock jitter on high-speed link performance. InPart 1, we provided foundational concepts of high-speed communications links. In Part 2, we discuss the basics of jitter budgeting.

Standards that convey increasingly large amounts of data over greater distances are constantly being developed. Committees and standards bodies comprising engineers from various interests establish jitter budgets based on the goals of the standard being developed (throughput and distance); while taking into account the limitations of the blocks that make up the communications link.

Figure 1 shows a typical high-speed communications link incorporating an embedded clock. Each subsystem (clock, transmitter, channel, and receiver) contributes to the overall jitter budget. Subsystem jitter includes a deterministic (DJ) and a random component (RJ) as shown inthe Figure.

Figure 1 : Communications link – jitter components.

In order for acceptable (note 1) communication to occur, the following condition must be satisfied, Equation 1:

TJSYS(BER) ≤ 1 UI

Where:
TJSYS is the total jitter and
1UI is one unit interval (period of one bit)

Total jitter (TJ) includes the sum of deterministic and random jitter of each subsystem. Due to the nature of the random jitter, this summation requires special attention. Random jitter exhibits a Gaussian (random) distribution and is unbounded.

Therefore, random jitter is expressed as an RMS value and is evaluated within a specific bandwidth of measurement/integration. For example, the jitter measurement bandwidth of the receiver shown in Figure 1 is f2 - f1 (see Figure 2). This is because the receiver phase-locked loop (PLL) tracks jitter below f1 (thereby rejecting it), and the upper frequency limit of the transmit PLL is f2. From the receiver’s perspective, random noise that would degrade link performance falls between these limits.

Figure 2: High-speed communications link – random jitter measurement bandwidth.

Because random jitter is the result of stochastic processes, determining thetotal random jitter of the system requires a root summed squared (RSS) calculation as shown in Equation 2:

RJSYS = √ (RJCLK2 + RJTX2 + RJCH2+ RJRX2)

Determining the sum of the deterministic jitter sources is straightforward,Equation 3:

DJSYS = SJCLK + DJTX + DJCH + DJRX

Finally, estimating the total jitter of the system and, hence, the link budget is possible; however, some additional work is required. This calculation involves statistical mathematics. A parameter called Q-factor is employed (see Table 1).

Table 1: Q factor and bit error rate

Q-factor depends on bit error rate (BER) and is selected based on link performance/reliability goals. Due to the unbounded nature of random jitter, a bit error will (eventually) occur. For example, a BER of 10-8 means that one bit will be misinterpreted in error for every 100,000,000 bits transmitted. Modern communications systems typically require a BER that meets or exceeds 10-12.

The total jitter of the system (and hence the link budget) is calculated usingEquation 4:

TJSYS = DJSYS + 2 × Q(b) × RJSYS ≤ 1UI

For example, for a BER of 10-14, the total jitter is Equation 5:

TJSYS(10-14) = DJSYS + 15.302 × RJSYS

This article discusses the parameters comprising the total jitter budget. The next time we talk about clocks, we will examine the relationship between random jitter and phase noise.

Join us for the next Signal Chain Basics article, when we will cover the drive capability of RS-485 transceivers.

References

Data transmission with a known and acceptable number of bit errors (Bit Error Rate).
It should be noted that the random jitter contribution of the channel is negligible if the system uses a passive implementation.
For more information about clocking solutions, visit:www.ti.com/clocks-ca.: U" x) g0 c/ A7 `% W

stupid · 发表于 2011-4-8 09:06

本帖最后由 stupid 于 2011-4-8 09:14 编辑

SIGNAL CHAIN BASICS #41: Clock Jitter Demystified
John Johnson, 1 b# f% ~- p; W8 U
Market Development and Systems Engineering,
4 r" J. a0 F& }9 i! |, TTexas Instruments5/8/2010 6:00 AM EDT(Editor's note: click here for a complete, linked list of all previous installments of the Signal Chain Basics series.)

As consumers thirst for the high-definition experiences delivered by expanding amounts of signal bandwidth, design challenges related to clocking become increasingly difficult and complicated. The difficulty comes from the underlying physics that are foundational to signal integrity at high speed. The complexity arises from the terminology associated with clock jitter itself. This article presents basic information related to the terminology used to describe clock jitter.

The National Institute of Standards and Technology (NIST) (Reference 1) defines jitter as “the short term phase variation of the significant instants of a digital signal from their ideal positions in time.” Jitter terminology has its origins in both clock and data signals. This sometimes has caused specifications that are, at best, unclear and oftentimes incomplete. Observing and characterizing data jitter involves using time domain analysis due to the nature of signals involved. By contrast, engineers employ both time domain or frequency domain analysis to understand clock jitter and its impact on system performance.

Figure 1 depicts both a real (waveform a) and a noise-free (waveform b) clock signal. Period jitter is the maximum value of Δt; reflecting the differential magnitude of the P1 to Pn value range. Cycle-to-cycle jitter is the maximum deviation of two adjacent periods: Pn . . . Pn+1. Intuitively, the steeper the signal’s rise and fall time, the less influence random noise has in the time domain (or phase jitter). Consider the ideal case where rise and fall times are infinite. Clearly, any random noise influencing the signal’s voltage level (amplitude) cannot degrade phase-noise performance because the signal traverses the decision threshold (vt) instantaneously.

Figure 1: Real (a) and noise-free (b) clock signals.
(Click on image to enlarge)

Figure 2 shows the relationship between different components that comprise total jitter. Total jitter includes an unbounded component. Expressing it as a bounded pk-pk value includes certain caveats rooted in statistical analysis.

Figure 2: Jitter Components
(Click on image to enlarge)

To solve real problems, engineers need to understand which components are intrinsic to the devices that constitute the system, and which are not and are targets for design optimization. Because the scope of this article addresses clock jitter, ignore data dependent components (including inter-symbol interference, ISI). In general, the cause of ‘spreading’ the clock signal shown in Figure 1 (a) is therandom jitter component in Figure 2. The balance of the real clock’s signal distortion (including the trajectory and location in time of signal transitions) is due to the deterministic jittercomponents.

Signal integrity engineers often interchange the terms sinusoidal jitter andperiodic jitter. However, sinusoidal jitter is a better term because engineers may confuse periodic jitter with period jitter described earlier. Extrinsic sinusoidal signals such as RF carriers and switching power supplies generate spurious signals that, in turn, cause sinusoidal jitter. Cures normally involve some form of filtering and/or shielding.

Common causes for duty cycle distortion (DCD) include trace mismatches (differential signaling), or mismatches in either the push-pull transistors on the driver and/or receive threshold mismatches. Minimizing jitter due to DCD involves using careful layout techniques as well as selecting good clock buffers. Some effective countermeasures for crosstalk include using differential signaling and shielding.

Finally, in general, routing high-speed signals (Reference 2) often involves using good transmission line design techniques and proper termination. For example, the waveform of a 1-Gbps nonreturn to zero (NRZ) link travels about 2.5 cm before a transition completes. In this case signal integrity engineers must observe good high-speed design practices.

The primary contributor to random jitter in the clock generator is oscillator phase noise. Therefore, a good clocking device is essential to minimize the unbounded jitter component of total jitter.

Numerous books and papers have been published on this subject, attesting to the fact that clock jitter can be complicated. The good news is that there are also solutions in the signal integrity engineer’s toolbox to address most contributors to clock jitter including communications link reliability and data converter signal-to-noise-ratio (SNR). Future Signal Chain Basics articles on clocks will address individual components of jitter, with a bent toward the practical aspects of clock-jitter causes and problems with corresponding solutions.

Please join us next month when we will discuss digital isolation interfaces.

References

Characterization of Clocks and Oscillators,” edited by D.B. Sullivan, D.W. Allan, D.A. Howe, F.L. Walls, 1990.
Electromagnetic waves travel through copper wires at about 180 ps per inch.
For more information about clocking solutions, visithttp://www.ti.com/clocks-ca.( k+ i, Y+ O6 _9 u# V0 P

0 B. L \6 S! o5 S! P+ U
About the Author

John Johnson is the Manager of Market Development and Systems Engineering for the Clocks and Timing Group of Texas Instruments. John has 30 years of experience in the electronics industry and has worked in the fields of product development, marketing, systems engineering, and business management. He holds a MSEE from Purdue University.

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