求救—谁能帮忙改一改

zhong0985

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
% l' |  [6 N+ e6 R0 O9 vuse ieee.std_logic_unsigned.all;
9 P# _/ L# e" ientity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
% I0 f0 j* }0 l2 [* X  hset:in std_logic;
! r* A2 W* e3 ~! _  sig_h:in std_logic_vector(2 downto 0);
  din_h1ut std_logic_vector(3 downto 0);
. J' t) [1 R, R' A, `0 {- b  din_h0ut std_logic_vector(3 downto 0);
  pmut std_logic;
: N- c% B6 B; P3 y# [( L" L  cp_h:out std_logic);
  
: |; v7 Z; j0 B, C# kend hour;
architecture behav of hour is
signal clk:std_logic;
begin
8 J+ `6 T( R  e$ c    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
     variable co1:std_logic;
     variable co2: std_logic_vector(7 downto 0) ;
4 p$ |4 Q) c% Q8 s$ R0 I/ ]# m   begin
4 M9 B& ^' U3 \  h6 c    if sig_h="001"and tp_h='1' then clk<=clk_t;
( q4 t1 ^: n$ Q( [  J) E   else clk<=clk_h;
   end if;
    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
+ S* R4 y" }( f       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
            if  cq2="0010" and cq1="0100" then
    cq1:="0000";cq2:="0000";
# s! @0 l2 H! r/ J6 I    co1:='1';
   else co1:='0';
: T+ Z$ T) B' @* [      end if;
      if cq3="1010" then
& m7 r0 i: i5 `* V; y& L      cq4:=cq4+1;
      cq3:="0000";
( s$ w' e, w7 e% ]9 d- f    end if;
5 t& }/ N' ?4 T8 t' Q! E: ]2 P   if cq4="0001" and cq3="0010" then
         cq3:="0000";cq4:="0000";co2:=co2+1;
      end if;
3 l* [! e8 ?9 N" y    end if;
  ?3 c* p0 s' S. \  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
$ y  `3 d: u4 E" R2 T! A0 f3 ?  D         else
4 G, R. D& b, h& F           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
2 \1 j; l: t4 m1 a             end if;
5 _# ~' \) \% z1 A6 Y- A             pm<='1';
7 Q; J+ `# p# g; d, n  V            else pm<='0';
            end if;
            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
3 X# J/ S  m, F              else cp_h<='0';
. s3 e. p0 n; y7 R% i6 H/ j             end if;
/ \* l0 d8 p2 {           din_h1<=cq4;din_h0<=cq3;  
        end if;  --12/24转换
% ~. x. E( q& t  
     end process;
end behav;

zhong0985

报错：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
5 m6 v6 R) y8 \        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
        Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
3 b3 n9 P: O" vInfo: Found 2 design units, including 1 entities, in source file hour.vhd
' r/ I5 F+ s2 x& A) c6 C! C5 Q/ h        Info: Found design unit 1: hour-behav
        Info: Found entity 1: hour
4 _, d' G( t- C& y" U; |' ZInfo: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
) ~" C/ U; U: ^% LWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
" ]! q0 c6 I) ]. T4 t! BInfo (10041): Inferred latch for "pm" at hour.vhd(20)
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
0 B) t% h9 G, U% N" K# RError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
7 X( [8 R2 d$ S  I* A( j: ~$ e8 qError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
; n/ o) ^& Z- W3 W+ H/ OError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
% ~3 j6 }' C  p, E  q( w" vError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
8 c3 s; R# d" y  B6 k' |Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
        Error: Peak virtual memory: 184 megabytes
' I% m; \. B0 H; N/ a        Error: Processing ended: Sat Oct 31 17:04:04 2009
5 l% ^$ V  U' M! C; _* q( I        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
" l1 x8 G# C5 L! sError: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings