求救—谁能帮忙改一改

zhong0985

library ieee;
use ieee.std_logic_1164.all;
, V# v' m4 ^! k8 O3 O% I8 C2 I3 |- m+ nuse ieee.std_logic_arith.all;
5 S& @3 x( L3 o  `use ieee.std_logic_unsigned.all;
entity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
  hset:in std_logic;
! o& [% G6 B$ T( R* e  sig_h:in std_logic_vector(2 downto 0);
  din_h1ut std_logic_vector(3 downto 0);
  din_h0ut std_logic_vector(3 downto 0);
0 {% k( R; n: j& L  L  pmut std_logic;
  cp_h:out std_logic);
  
end hour;
* g3 n% c" K0 K7 b( v8 varchitecture behav of hour is
# H1 j: h& D! [9 |1 r3 B4 ?1 ]signal clk:std_logic;
begin
3 O  s% b, ^" B. a/ N    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
     variable co1:std_logic;
     variable co2: std_logic_vector(7 downto 0) ;
   begin
    if sig_h="001"and tp_h='1' then clk<=clk_t;
* i3 }& T* v* i6 ?   else clk<=clk_h;
; g7 B" ^3 p- o5 M# `   end if;
5 R2 Y/ m& s, p  t% x$ J) @    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
) h' \3 @. J& u& K            if  cq2="0010" and cq1="0100" then
, Y7 F$ F- b0 e3 j    cq1:="0000";cq2:="0000";
    co1:='1';
   else co1:='0';
      end if;
7 N# S+ N4 f4 `& j      if cq3="1010" then
! k+ h' ~1 B. {$ O% N" N0 Y4 X8 O/ A      cq4:=cq4+1;
  T. {% V6 a6 F  f      cq3:="0000";
    end if;
0 e4 l( ]; Q: a, O$ R0 t' j   if cq4="0001" and cq3="0010" then
         cq3:="0000";cq4:="0000";co2:=co2+1;
      end if;
    end if;
+ N$ y: k8 w. g0 z/ s3 m. V* A  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
         else
% ?% B) {; o: f( R- P: V           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
. H7 ]; Z7 t7 y/ L+ d1 C% m& T             end if;
             pm<='1';
            else pm<='0';
( O6 {1 \: k0 [' ^. l& \            end if;
            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
              else cp_h<='0';
) w: e; v3 H5 M2 |/ O5 Z% S- z             end if;
           din_h1<=cq4;din_h0<=cq3;  
. r+ C/ e5 B, f, _! j% q' \* _        end if;  --12/24转换
  
# w' I# ]+ b: j, i, y     end process;
3 q0 L9 o: F9 I, L+ M' mend behav;

zhong0985

报错：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
+ O8 z" q/ o4 v# l% U/ ]! Q# ^        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
        Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
Info: Found 2 design units, including 1 entities, in source file hour.vhd
+ |% M9 U4 d0 a; Y8 @! L' w        Info: Found design unit 1: hour-behav
6 v+ L4 I, `2 X        Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
9 k; ~8 o- |6 e. ?Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
4 |: i# z9 j7 Y* fWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "pm" at hour.vhd(20)
# I+ a* ?  A$ ~) \& G/ F$ nError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
- y6 t/ ^& p6 d+ JError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
; Z& ]5 H+ _# d/ MError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
# H  H0 F3 i" J8 K/ C* pError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
0 L+ H' _7 e" F8 xError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
$ o$ Y5 ?$ P* Q2 M; c( YError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
Error: Can't elaborate top-level user hierarchy
' y8 I* c) Q4 n0 `# m& nError: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
7 e' H7 `" W% k1 M( e        Error: Peak virtual memory: 184 megabytes
5 }/ F7 o" A- N: X8 Y" b! u/ S        Error: Processing ended: Sat Oct 31 17:04:04 2009
& `4 K. z6 A' N/ \+ h0 v# @        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings