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改进如下：
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* y! V8 T1 E3 Q, }7 e3 JHOTFIX VERSION: 015+ n5 P" A. h$ V9 @; ~4 s, Y
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/ x2 {2 A3 \0 K6 D/ Z4 ]! D# KCCRID PRODUCT PRODUCTLEVEL2 TITLE9 H: z7 d3 e/ y( n/ n$ ]3 }6 o- Q
========================================================================================================# Z! s& x5 @7 ]8 V$ r8 l+ r, U- D
264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip
/ Q9 h, \+ t' Y k0 N+ K3 L609206 APD OTHER parallel command fails to run on mcm files9 ~, O- k! J) S
646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time2 |7 U1 w6 _8 c9 e, P x7 f- F
650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames0 t+ {1 }0 n& ?& \
665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal$ y) s% Y; @+ P7 F2 e6 W# v
666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import: L! |0 @0 g$ u$ W+ X
669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n
( b% g6 { y( h) q% m669769 PSPICE DEHDL Edit Model on page border causes crash* E1 S; ?- N1 h4 y( p$ X) j% x# g
671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files.- g3 @9 f0 x0 t+ _% @4 l! B
672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl T9 t; k3 I2 X! W( H
672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke" p* ]$ g" w& a, e v
672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa& E0 ] ~' ^: \; i
676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets: f% C) |0 v* u
677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets1 o+ a0 S1 T8 j; L0 s
677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.; C- Q" ]2 t6 S; R$ c2 e( i+ q
678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license+ H% ^+ p( p3 O$ c
678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM% v; h4 g0 l, \5 P& P
678794 SCM PACKAGER Unable to package subdesign
, x& {( f* N. I678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2
. x/ B8 C6 `: p8 \678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced
( \4 g/ k# m; w% {+ P9 \4 }679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns& C8 X {5 C! E0 f1 J2 S. W* l% e
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i
- Y; U3 c6 e; \3 W679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo+ Q; s" A( k& p" b
679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.
+ z9 K% M1 N# l1 k+ D2 ^679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st9 w2 r4 A# ?$ A+ Q$ Y
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri
7 r' n* ?" r: K- K3 P; U! b681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase
5 D- {4 W# d' p( x! M8 B681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if! S) A U9 q3 L( Q$ _
682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte
, l0 d( F; T; E h683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
/ c( I8 \9 |# z( D2 Z683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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