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本帖最后由 partime 于 2016-8-10 20:06 编辑
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不知道有没有人上传分享,我刚下载上传过来,现分享!
: L, W$ B/ W# s8 a3 _7 G1 o) r5 M链接在下面,回复可见。顶起来,让更多的人看到!还有CCR,可以看看都修复了什么内容。
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& h% y9 H9 Q" B) MCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 M& v$ u# v5 C* X4 p$ ?$ u; J1 H ===================================================================================================================================
; u7 B, V) v+ [! F* v 1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
: A2 K$ ^* l3 ` 1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
+ Q' `+ ?& B) t$ e/ M 1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
0 P+ o7 F: E( Z* F: q6 M+ Z 1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
$ I) ]0 o8 T- E! K1 p- |1 z- D- n- l9 O 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
9 V' w a) |* ] t* [ 1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
8 ^. w& K+ o, e* A9 J" h7 x) x$ x: \ D 1584719 TDA CORE Caching errors coming for a board ref project while doing Block update$ o% J* K! F! J, ?$ p
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
# L: A7 z& i9 x( p: K. }7 N" h 1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed3 y$ j! d4 {) N" `( ~* ^" K3 i
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
$ d2 k( G: \( l' L$ Q 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component: K9 q! j$ U9 g' k( ? E
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior
) h# x% a/ M% W, n 1590639 CONCEPT_HDL OTHER DEHDL crash when importing design0 z- y4 |9 _8 d: t
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM/ p2 f2 s: f/ f
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified/ f+ b( I& u0 u& N! u3 A# _
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view
% \5 r# t6 p" G3 T7 Z 1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
+ }- W* Z$ @, K) ~7 A% N# C 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor% T/ `1 G' a3 }8 f2 \' f$ N) ~
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI
v6 K* E% Y/ I; c6 b 1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas
r ]: l* N q5 I7 b 1598629 F2B PACKAGERXL Export Physical crashes2 Y* U( ^ |8 v3 |
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
, G& w; Q0 U. b+ K) G( h; l- K8 r 1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.) C; M0 ^0 s3 P4 m/ S8 ]
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
, O$ V* t6 r0 b6 Q 1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
' E1 @2 E L% ` s$ K 1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
1 J+ y5 Q/ `+ z2 j7 S3 V 1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
0 J/ |' q4 ?! l! S8 C 1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
9 ?7 I! T- b- v 1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command1 |" @' q2 F" J
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer." T A9 ^! A. N/ g2 A/ M1 ~
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error( _, ^5 w+ k7 c1 J F% v: {
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard$ a6 R" {" J' f- ~- R$ X; b; _' N
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