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DATE: 05-28-2016 HOTFIX VERSION: 071
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) @1 y3 L8 u2 o% `( f. N. Z1 y1 \
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1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets
. @2 Y! e) ~' K1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package# {6 `$ W0 H; |; n; P
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
( [% n! [; @; t5 m1 o+ J% n* g+ z1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
; {) e7 T' m4 t, M5 D1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
# h3 c! }. o/ M1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
' j7 d: Z; o4 X9 ]- ?& _! O) t1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)
$ e3 {) w4 _- q/ N7 g6 f/ x5 S1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
& d6 {7 \: L3 s1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None', m* n U+ ^0 ~) k ]
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library8 P8 ]& }" H* j \
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG9 p W! L# [; f; c {# b+ j
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon |8 ], O0 }0 c5 l
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets% B- A$ w o" {& b& g* q" a
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
! [& o! Z* w. J" D1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
# p5 _. P& n, }; _1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
- ~1 W5 x7 e+ f& X" W1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
# x9 ~' q- v9 v0 _0 j+ i9 K1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
+ E8 t. L0 C' j3 ~ y1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions8 _* ]! G2 ]( B
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
$ @# l$ A% x; @& i" D% O$ h& ^1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.. b. Q! z# a6 }; y* g
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct P6 i8 h* ]' @/ ^ ~
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window! |: L% x/ m) L( `% N: g
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
% {* j6 v5 {' n: E7 Q8 F1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed
+ E" z+ ? H. R# W) Z1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...; L3 `9 k/ R: i R$ L5 Y
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
& @4 G* F2 G# _. V1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short- x# W5 A+ d8 M" ~" I2 W$ W% I
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
& @+ y8 {# ?+ x! }* d1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only( F5 `+ T4 H+ \4 o+ W/ W
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display: X& m, d7 T% z, l6 k
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
- g* O+ G! X5 Y5 T1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
6 x9 U* s! I, c/ N/ E. e1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings* A V- a; v4 J+ @
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'! M# t; T! @& B4 i
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files/ E/ x1 q: V# w1 r
, S3 R5 S# y" x8 p% S; V
DATE: 04-22-2016 HOTFIX VERSION: 069; X3 q; y' Y8 S2 [2 }
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output% K! W0 h r: [3 z8 B; S9 S
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode
/ |! ?4 j6 X- a! F1 ?1 E8 a" m" _1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail! i* j$ v2 @8 Z9 t% T7 N ?- C
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
& K6 ]9 T4 N- b0 ~, U1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing% P! k/ q, A2 k8 o
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
# m$ ~3 ~0 o7 k( _( ~; H1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
. l5 o; P2 E4 a" l" G P1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork, E: P* ?4 q9 R; w9 q! y# }
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
* g3 B5 F, B- A7 l( a9 P: g* ]* A# L1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
- P$ o) T; e# O) H6 }9 I1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work5 u6 F a* E; R
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork
1 C' l- f3 d j! I& |! n1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message5 q6 }7 V: r1 e5 b: y
1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point
$ w5 A/ i- y0 `- x" W1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
' b* G0 p7 t+ M6 @1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems# w! y, |/ S( `* h5 y* @* r0 {
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro* }; O5 N0 z: v
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
9 }8 n: ?# c/ Z# O- b4 l2 f" t1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
3 r" R2 Z3 P& F1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
" ]2 v' L% @8 `7 @, J! H1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted! l( D( x! {5 p3 l* B
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die: O: b7 Y1 U) q$ H/ v
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
9 I+ ?' s5 A; r ~( Y9 F1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error+ d) `- R; z6 l6 D! M
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.
) x- h5 L- c* }
6 Q# x) u0 x. P, tDATE: 03-23-2016 HOTFIX VERSION: 068
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CCRID PRODUCT PRODUCTLEVEL2 TITLE$ [/ b; Y! K* p% k" z. H! k R$ d
===================================================================================================================================
. d q3 Q! u/ B0 \( ]1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
; L+ k+ q4 N& F, n D$ O1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
5 q; o/ c" e4 a1 T. q: t$ q/ B1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
7 ?) c+ r$ U3 s- }! i6 t {, u1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short
9 B4 R* c+ V" Y' V4 V# c) ^1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system, D' V* `+ C/ R# m. i* Z
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
- l% h# c0 V% M% |" d, j1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol: A5 @: y/ ^7 I2 n) S- r7 x' E
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file1 J- B9 q, D( h5 J `9 ]
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report/ H2 f' _5 ?$ z7 f0 R, g: x4 V) r) }) B& M
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'- `4 x% H; G$ d3 ]
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have ., q8 {( g. N- ]7 u, r
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts5 s: f- @' w1 \1 u: i1 t
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
. @6 ~& o% D1 ?* ?
3 V* _* u8 y/ `7 P* v- Z3 PDATE: 03-11-2016 HOTFIX VERSION: 067
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, O$ ?# @) r- P6 Q; {/ ]1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
2 b6 L: r- V% n, }1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
+ I9 H- r: Q. d0 t1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error0 K8 R# y2 d( T% P# D
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
6 w" c8 }5 C; m- m+ n1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property ]- v+ x. s9 ^+ \, q; F- s
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net9 `$ F, c9 a5 n8 b( u1 U) ~
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file, Q' f) o% l1 w' X r B. F
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes( D' o. `3 T" m
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing- Z: y) h% N5 U
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager* q% e; W/ l* T9 G# t% D
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters8 B7 J* t4 U: e
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
5 e+ r- n9 L* ]1 J1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer' n. m1 R, \0 N9 M8 _
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net( n% L) } u3 [
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
3 g. S- ^" B9 X; K; M1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
7 [8 E0 R2 V5 R% Q1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error
1 S1 g( \/ p$ V$ e$ C1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled." _$ C' C2 Y% T2 O
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib$ A$ _# `5 p) R% k' U
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines
6 o; z o0 q# k! K4 N1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
5 P& J) w1 I0 a' @6 n7 r) L1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
! ~/ q8 \0 A* B3 m- n1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
! G" a! d0 r: n# t! W1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash c8 b; ]! M: _$ V& O
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked2 U d" b5 N4 C, K/ n
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.
: A* h* d, C8 Q1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with L$ w( v+ }+ Z1 f. h4 f, q" z( h
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design+ J C" z& \3 b+ @2 N9 K1 @
1 `- }! [: g+ R5 D2 s; i5 @DATE: 02-26-2016 HOTFIX VERSION: 066( h, z. j+ r3 i( T1 a4 Q$ i: L
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CCRID PRODUCT PRODUCTLEVEL2 TITLE) O+ B/ }. Q9 D
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6 N0 A; i5 Y* H) i |1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated
# B! `$ _( P9 {1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes5 _: h& n* n$ M9 C) x
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions! _6 H) ^1 ?. _1 r- H
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message
' }+ E: c' Z y3 k1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
/ G1 L% ^+ M# m$ _1 A3 `/ D! p1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue' U6 S2 h1 p# s$ f, X4 D' m
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer
4 C* g9 e; Q' ?: F$ a1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins$ Q" i1 S1 e1 S: x
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
( r# _1 n# l6 }; u1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed
3 b# ]9 Q* f7 g3 U0 Y" M9 \/ {, v
DATE: 02-12-2016 HOTFIX VERSION: 065
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working" o) _1 c2 n& \3 y
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via# x6 d l* ^: Z$ K! _
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit. h5 @0 @, `; ]2 q
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents. X6 w5 j% c1 w S9 v8 O0 T y
1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms
1 O) O5 {0 z& D! N3 g- G1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine' L: d' i# S. v( e/ ]& \ O$ x! u
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger- w+ N) X* S* n8 a! b
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design* H$ X i3 [* F& s* t$ A/ Z
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
6 c* f G9 A( y$ X9 @1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.
4 H! c! c9 J; u: D6 }- T; H9 L6 `, k& K* D2 ^1 H2 b
DATE: 01-29-2016 HOTFIX VERSION: 064
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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" c9 U. ^; Y% w6 C ^' S, p1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
- p: s9 y+ W" b/ i `( @1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF
+ A7 N3 k( R+ C" e6 x& h1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.& p5 u0 ^9 c; ]9 }6 @7 k. R
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected/ ?8 d' f# M7 h+ G' K
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
+ V0 b# ]- J! b. ^/ h1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
! } m. e8 V3 @; {5 _% h1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas) J2 M$ U9 ~ Q6 ~/ m* W
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
, u2 M6 c; w) y# F: \8 |1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist' l2 u4 a7 \( k8 b: ]1 z* d
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic* n' y; g. `( e0 F: O6 O$ B8 k7 h
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor( O3 I( z+ h% n$ I
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file)+ ~' l# v! t" N, t: i& }7 J
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
1 E! W- h; |; M1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash* ?; p" y' k5 H6 o1 p
1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes
5 s0 U' _ s, l, H# o1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor, z F: T" R( t. Z) Z
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
* i; d; u. ~6 ~8 o5 j0 T, o0 d1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
5 f: X* j9 Z* L$ r' R5 b1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
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DATE: 01-15-2016 HOTFIX VERSION: 063
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4 E8 U5 D; ] T1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region/ m" b' `1 n! J7 _
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs: _% ?. X" ?& D8 f; h
1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs
3 B, u! G+ R( g/ A7 s9 B" D2 h1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant! W& U. o' v, v% ^0 X5 t
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
7 e; G6 E" v, M7 Y1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6
* X0 x$ D& b1 o1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance, F ?8 f! {3 a) b: [
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
2 r, O6 c9 N7 C4 P" ?1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly.* X& D( {, [5 T3 `2 `9 R
1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out* y, O& L0 s; S& w5 m) g% ~6 m
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
; F; M; C. ]+ ^' k" Y7 Y. _% r1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property' q5 J& a, g* N- ~: F' B
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly. i! K$ o# Q8 n* I' j5 {/ L4 c
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation8 Z3 G) E) `! g7 K# z% j
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol1 ?/ t: U% Q' s* p
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'# V" G) j) K! u! U
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
! n: y0 v% L8 U4 w0 f+ q# k$ j1519518 CONCEPT_HDL OTHER Genview does not generate split symbols+ ]1 ?- l9 R2 c8 l$ q+ o1 @) f5 o
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
2 Y+ w1 I& O- V4 l# Y1520207 CONCEPT_HDL CORE Genview crashes after renaming ports: A6 R- |3 i6 Y8 u2 o$ r/ W, U
6 R' D5 f3 n' Z# L2 G0 J
DATE: 12-11-2015 HOTFIX VERSION: 062
2 K" s3 n' y9 X/ r1 {& F. n& d===================================================================================================================================
, Z8 q$ d2 k uCCRID PRODUCT PRODUCTLEVEL2 TITLE
8 ]( z2 j7 A: X6 P===================================================================================================================================
9 d3 r5 }8 i& s7 l# G7 |+ n3 ^1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
7 @, U5 m f' A" G1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
3 x1 ]) O4 Q1 @* ]% x1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option
9 A: j1 Y! w$ D7 e1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
! m. r, J8 q8 b& t# ^. D. ^4 b, c1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view* `# ~; k3 }3 z/ K" D/ T- U4 k
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked* Y4 G# b Q0 c
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
7 X' b7 @' f. i2 {' }1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file. W) o! t' |4 s' H
1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
0 @) {, s" t* c# B, n! ?1490311 SCM OTHER Block Packaging reports duplication when it should not
! J! V& ]7 g+ ~% G, ]1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'" a5 c0 m+ I; {* O9 _/ e* ]
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message' Y0 S+ `* @7 W7 @: h3 L
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)+ I6 ^# S' e4 q J$ _9 W
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit- ~$ O# M8 I j; c. `; g& K
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
" V' U; a3 u$ Q4 s- |: M1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
) k9 H9 h1 | i5 h1 G1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types1 J5 Z: a. Y6 e; X9 D+ f% n0 G
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'5 q, A, M, m7 u: k' C" l
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly7 P6 J; w: k4 D% e$ i. Y3 Z
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
# b1 `3 v, c% Q( C# v1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch; ]4 Z v8 I; ^, K) g: e
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default, r+ e" C" N3 ~
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts3 F2 R7 z0 C8 H( A9 K
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks( n( ~$ A& B' Z
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out5 [, p: ?: v' P9 S9 A- g3 K" O7 P* }* q
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF9 V7 ?- m' R$ x& O5 T: A
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
$ z! {8 M+ x y! W; o0 Z1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
# y) I* b$ e- c/ y! |7 @# |) f1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
- `8 I' F4 u6 J. g1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location/ w! h- o2 y& ?9 P" H/ |! g1 Q
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized l* s, ]- B; K( A1 a2 ~4 o: T
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
3 z% o n. w* E0 r, B1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items1 u) W+ a4 M$ e# J* t4 T1 T, }
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
, i- C/ y# t% t0 X1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving6 U4 ~8 L1 t$ l, M! A" D1 S' Y
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None% B. W3 Z: \6 W$ E: \# T
' K; x: t; x3 X* f' xDATE: 11-20-2015 HOTFIX VERSION: 061 x) P0 _0 }9 J% l5 ] Z- z
===================================================================================================================================) [& S" v _6 }3 \3 [' Q3 Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
" }8 T$ U1 g' H, ~+ t5 g===================================================================================================================================- ~7 [# @0 v9 r1 J Z1 \$ Z/ C- K8 k
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value) z0 s5 z6 v$ }# a6 Z# e V0 c
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
6 e6 G {; V' F5 l, Z: t/ ?1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
- X- U* P6 @5 Y) |& R) } V1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
' M5 ?3 h" D3 |1 A( y1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins3 f9 V6 V# a8 Y7 q) d8 v' t
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set* x5 x# `' I8 U: d8 k* x8 J; q6 O
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
* \& ], ^) I5 K3 p$ D1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools4 L K0 y+ N& o' _
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename8 b9 _0 F1 p- ]
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
$ J4 f% V4 j# a6 K+ A5 I9 d1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
/ {# t" z8 M+ v1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy* ]! H* ^/ E4 F8 x0 O
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
' L3 a8 ?" N' }1 J5 x' d2 X9 o9 }1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
4 X( ~, x' d" m+ D- s# W1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice$ v" J; b8 E! g0 x R. |% u
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues: t1 D/ Z6 O2 j2 F
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
! `: E/ E/ |' z# V: r2 N8 @1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project& L+ A3 t# V, ?% Y7 \. ?3 S
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
+ N: m4 A) e4 D) ~* V( S% K1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
* v. [3 }8 v. q3 o7 G1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems9 e% Q7 `! F4 u& n2 F
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported3 |1 K# P5 Y ?
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior0 \6 B& m; P1 }" [' a
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board( q/ a2 l$ l: L" x4 M
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager3 k. A6 C3 d& G; ^( T9 v
1490299 SCM OTHER ASA does not update revision properly
! E' I% z, o4 X' X/ D1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer
4 h% @3 [1 }3 J. j1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
! F! N! M2 w' u1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working' H, z1 u6 b! D$ u+ H5 D- o
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
& N1 ^: ^ @! m4 A! x' _0 X1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash3 o- H( z6 f5 T1 L& Y- s: T7 _, _0 S
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL# f5 j0 j& G. a* t9 M* R
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581" Z3 r" R# Z' F4 _
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
- [0 u$ E* \0 _; [) }1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
4 h4 u3 X& Q" s- D O; ?; f1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file. _* g4 \$ F" M: s7 n
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 |
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发表于 2016-6-29 12:21
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发表于 2016-8-22 09:13
