数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

zhangsong123

通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
: K0 {7 \0 n. Noutput [7:0]led;
output [5:0]led_seg;
3 C; i; ~  [: M3 S4 h# {output SOS_En_Sig;
# ?7 x$ m8 p" s  dparameter seg_num0=8'hc0,
          seg_num1=8'hf9,
, }" d' T: X9 X# H) `             seg_num2=8'ha4,
, T5 ?; [  n. E+ v7 K, H             seg_num3=8'hb0,
' }$ e- n" z5 [' N" R             seg_num4=8'h99,
$ |! |- C8 B5 T1 v             seg_num5=8'h92,
             seg_num6=8'h82,
) x2 O" e6 s# ?$ S) U5 S1 H( D             seg_num7=8'hf8,
             seg_num8=8'h80,
             seg_num9=8'h90;
* ]9 I2 ^/ i0 J. Cparameter seg_en0=6'b111110,
3 v6 H  o9 [" S- y* `          seg_en1=6'b111101,
             seg_en2=6'b111011,
2 n# O* q6 c* v             seg_en3=6'b110111,
             seg_en4=6'b101111,
             seg_en5=6'b011111;
1 l) U4 o* W2 L- d$ _( ?; |! d' oreg [26:0]count;
reg [3:0] count1;
  ?0 M- v; P% ]# Greg [3:0] count2;
! n$ [: Q# \3 G2 h0 P5 areg [7:0] led_reg;
- X. Z: B7 ]  S% p( W) }* L/ v# K$ }reg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
8 ]% Q1 G  l5 @: qif(!rst_n) count<=27'd0;
: m" Y( n2 Z$ P! G# L' }else if(count==27'd49_999_999) count<=27'd0;
/ y! r# z3 H$ B$ J$ S* y1 aelse count<=count+1'b1;
wire clk_div=(count==27'd49_999_999);
# I5 q5 J9 c" ealways@(posedge clk_div or negedge rst_n)
  F0 j9 v/ x$ K! `if(!rst_n)
: C& |# s& _4 tbegin
% S; K/ a/ k$ S6 X1 [8 W: B5 Qcount1<=4'd0;
count2<=4'd4;
: W4 w! B9 A1 }! S" ]4 R* mend
else if((count1==4'd0)&&(count2==4'd0))
begin
count1<=4'd0;
4 o2 p3 F/ X# v. L% S0 xcount2<=4'd4;
end
else if(count1==4'd0)
begin
count2<= count2-1'b1;
& Q/ c; D( h; K4 v' w& @count1<=4'd9;
end
else count1<=count1-1'b1;
4 n2 k" c2 ^2 s; Sreg [26:0]count_1ms;//
6 i1 x2 R1 h1 W1 ualways@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
9 M( C3 \9 I& X+ \3 Sif(!rst_n)
, q+ M$ u; W) K0 B& |& t* s% V& \begin
$ p: f8 V# K7 k# U! |5 {+ \8 \0 a0 uled_reg<=8'hff;
led_seg_reg<=6'b111111;
: Q& I" Q0 i0 f6 x! s, ]+ ?2 Lstate<=2'b00;
end
6 P2 i) e4 B, p& J2 Y0 ]& |else if(state==2'b00)
" Y7 C5 K7 s* F3 ]4 Nbegin
state<=2'b01;
led_seg_reg<=6'b111101;
, e  @) r2 Q0 X* w3 r0 xcase(count2)
/ D& e5 J) p7 \! @6 x' F/ S) E4'd0: led_reg<=seg_num0;  
9 x' Q8 Y& Y, `" k# |' _4'd1: led_reg<=seg_num1;  
8 q0 I1 D6 b; L# G7 C' G4'd2:led_reg<=seg_num2;
4'd3: led_reg<=seg_num3;  
4'd4: led_reg<=seg_num4;  
: G) r) c9 o: p- \- ~4'd5: led_reg<=seg_num5;  
0 _- q" m0 F* y4'd6: led_reg<=seg_num6;  
4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
2 @0 S. t* A3 m  {: U% ndefault: led_reg<=seg_num0;  
endcase
end
else if(state==2'b01)
! {, R' m3 g# d. _$ Q. _begin
7 h7 j, E  m$ p" rstate<=2'b00;
7 i% |- ^% @( a, ?- ~( y( Aled_seg_reg<=6'b111110;
case(count1)
$ k# ]+ n4 I3 N% i7 T0 N4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
! O* W: l2 o9 i% }% z6 L* h4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
, ~& J$ \8 e7 b( T' T7 W4'd8:led_reg<=seg_num8;
4'd9:led_reg<=seg_num9;
default:led_reg<=seg_num0;
endcase
- V3 n3 m& L% @* h8 kend
reg isEn;
always@(posedge clk or negedge rst_n)
7 b$ t+ I9 U. q1 f: |7 P# ?) [, Iif(!rst_n)
* Y4 H6 M; Y0 }begin
isEn<=1'b0;
5 h  K9 z- |0 ^/ Send
else
" \) F, Y6 J8 _$ c# K5 N4 g/ dbegin
3 W, H$ i( q( g0 f' _; zisEn<=1'b1;
( ?/ B: j" p8 i/ q& o. g" |end
) q( U  n. ?/ D: I3 ~% Lassign led=led_reg;
+ S; J. V! y7 m- o' l5 }0 zassign led_seg=led_seg_reg;
; T/ z3 E+ @4 t( n5 ^" @assign SOS_En_Sig=isEn;
endmodule

: A- m( \6 N7 C' ]% b  ?