数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

zhangsong123 · 发表于 2016-4-13 18:01

EDA365欢迎您！

您需要登录才可以下载或查看，没有帐号？注册

x

通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
output [7:0]led;
output [5:0]led_seg;
output SOS_En_Sig;
parameter seg_num0=8'hc0,
      seg_num1=8'hf9,
         seg_num2=8'ha4,
         seg_num3=8'hb0,
         seg_num4=8'h99,
         seg_num5=8'h92,
         seg_num6=8'h82,
         seg_num7=8'hf8,
         seg_num8=8'h80,
         seg_num9=8'h90;
parameter seg_en0=6'b111110,
      seg_en1=6'b111101,
         seg_en2=6'b111011,
         seg_en3=6'b110111,
         seg_en4=6'b101111,
         seg_en5=6'b011111;
reg [26:0]count;
reg [3:0] count1;
reg [3:0] count2;
reg [7:0] led_reg;
reg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
else count<=count+1'b1;
wire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
if(!rst_n)
begin
count1<=4'd0;
count2<=4'd4;
end
else if((count1==4'd0)&&(count2==4'd0))
begin
count1<=4'd0;
count2<=4'd4;
end
else if(count1==4'd0)
begin
count2<= count2-1'b1;
count1<=4'd9;
end
else count1<=count1-1'b1;
reg [26:0]count_1ms;//
always@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
if(!rst_n)
begin
led_reg<=8'hff;
led_seg_reg<=6'b111111;
state<=2'b00;
end
else if(state==2'b00)
begin
state<=2'b01;
led_seg_reg<=6'b111101;
case(count2)
4'd0: led_reg<=seg_num0;
4'd1: led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3: led_reg<=seg_num3;
4'd4: led_reg<=seg_num4;
4'd5: led_reg<=seg_num5;
4'd6: led_reg<=seg_num6;
4'd7: led_reg<=seg_num7;
4'd8: led_reg<=seg_num8;
4'd9: led_reg<=seg_num9;
default: led_reg<=seg_num0;
endcase
end
else if(state==2'b01)
begin
state<=2'b00;
led_seg_reg<=6'b111110;
case(count1)
4'd0:led_reg<=seg_num0;
4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
4'd8:led_reg<=seg_num8;
4'd9:led_reg<=seg_num9;
default:led_reg<=seg_num0;
endcase
end
reg isEn;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
isEn<=1'b0;
end
else
begin
isEn<=1'b1;
end
assign led=led_reg;
assign led_seg=led_seg_reg;
assign SOS_En_Sig=isEn;
endmodule

		自动登录	找回密码
密码			注册

数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

EDA365欢迎您！

浏览过的版块

推荐内容 /1