|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
DATE: 07-31-2015 HOTFIX VERSION: 054" t7 z! w" d9 L& z5 o1 p7 i
===================================================================================================================================
% P+ }/ J3 I" }3 ]1 LCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ A2 g" {3 W0 ~. N0 t4 i2 B* A4 ?===================================================================================================================================. Y! f- q8 T I; v; }1 T) s
694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL8 {" P! |2 j( ]. @, Z2 ^
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions- m8 w% C( v, @! V
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List3 y- b; f X! A1 u# P. y: L
1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate( X$ J$ x3 v) D9 u: ~6 c
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees
% s& ]/ Z3 E. W. @1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias4 R/ s; m) r8 Y. l
1412635 APD DATABASE APD crashes on saving design5 H- [& G6 {/ f& q9 \ a4 ?) ?
1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices8 B, k5 P* P8 |7 N" t" l" C4 W
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation8 k& ]# H7 I6 B u
1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.
0 y# O$ @8 T3 l$ ]4 X& A1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50& l4 C& T% k4 Y% F8 q9 X7 n
1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
1 _, U G; u5 c/ {1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
4 t- _ B+ u" A# R* N6 v6 y! B1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated' _: o! Q2 y6 W( a% K
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output
9 J6 E$ N) S4 ~6 {- W1 E1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification8 U7 m I7 W0 E3 i5 f& G7 _1 H
1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.
. p/ ] G! Y2 X7 _% i1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets
( F- a. P: T$ h3 U1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor1 C" q2 f2 O, \
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow
7 g* t( H, u C! T& n1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
0 @6 Q- e5 C: C% Y/ O3 _4 c1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board3 i6 u9 z0 ?% G& H
1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks; P- n( T+ W' P2 X; o
1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports. t' k& h, h. E& A. E5 g' E
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC
8 R2 ~0 m- v8 z) ^1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary
' |2 ?3 p$ p1 h1 U1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.
]4 O5 @5 H' {. a1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1
8 O& X) X$ [7 ^3 A! K7 e" A
7 k0 c2 o6 u/ b7 Q2 I
} q6 w1 I/ D6 w' fhttp://pan.baidu.com/s/1mg28zJM; p: C% [4 {( u; u+ \
|
评分
-
查看全部评分
|
[复制链接]
/1 
发表于 2015-8-3 11:54
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
