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8 a) \5 d }0 Q1 N! C2 F 才看到网友说AD15出来了，然后刷微博就看到了这个。。。
; v* {& k+ k C4 n" }- n& N+ f2 V8 O
5 f6 T+ f5 `* ?
9 i- H0 }4 d6 D3 |) e3 t0 s8 _6 k0 h* j+ _) ]2 t3 c+ w
AltiumDesigner15.0.7出来了！
3 g& l3 o. f7 G9 X$ k3 q: U; Z1 C我唯一的感觉就是，Altium，你更新的太快了啊！有事没事，你就更新，
6 h; i; F2 J) Z# @) F5 E( }或者说是，你是在修Bug么？？; {% _3 Z$ v8 d4 t% ^1 t+ @
貌似AD14就一直是Bug不断，这次AD15估计也一样，不过，9 k8 H5 }8 r! @0 w" B7 P
貌似AD15更新了高速PCB设计和GerberX2的支持。具体更新如下。' u3 z$ |9 |4 s/ n. V' m
就一个问题，AD总是在不停的更新，是表示软件不稳定呢，还是？？？
( l, N/ C6 T, |5 U5 f" ]8 O8 b或者说，你会更新到AltiumDesigner15版本么？
0 W+ l, y- X! Y! H/ K+ m8 l4 i3 @! ~- o: W7 H0 T' k* @
Release Notes for Altium Designer Version 15.0
! F: r. N2 Y0 M$ c6 G; V3 \! |# u) n5 d: RModified by Nikolay Ponomarenko on 17-Nov-2014" k; }$ F4 E. \0 K1 q% w
Key feature highlights
+ s6 k' l6 E/ [# cHigh Speed Design with xSignals2 Z! b1 b7 F. J* v( E4 @. E
Solder Mask Expansion Enhancements
# r7 Q- k2 }1 zAccurate Route Length Calculation+ i: H/ G, a' ~/ R
Polygon Enhancements
$ [7 O' T' z) b* Y$ _OLE Object Support in PCB Documents
) A' H/ i; `; j- J0 C7 F' T4 pSupport for Rectangular Pad Holes
) u3 r* X1 p- a: G" i1 iSeparate 2D & 3D View Orientations
% h. O; X- X* X6 IIPC-2581 Support/ Y$ _/ H4 `3 u( U c% f3 l
Gerber X2 Support
8 @8 Q% K- O, u5 J- gIDX Support' E( p$ D' m' G8 k- O
Exporting to IDF in Unicode Format
; r$ S( ?, [" A; TTrue Variants Enhancements9 n. k$ J$ T0 |
Output Job Editor Enhancements2 R. H; Q. ?: Z( y V6 B' O
Upgraded Duplicate UID Correction
, n: R$ |/ r9 j) I: J7 @7 n3 A3 VSystem and Performance Enhancements
' ?' r( y) K+ [# n; G6 ^5 p8 XVault Connection Enhancements
$ k/ X, Q ` ZAbility to Control Parameter Visibility for Vault Components
! K! _) F. T# d' ^3 KParameter List Templates& S- |) L7 X+ w5 ~& B6 P
Parameter-based Name Templates3 ?( H. n& `4 ]; d0 O% x
Vivado toolchain improvements9 P1 H) r$ e8 N3 D2 K |
Intuitive Import and Export
2 m; {" a7 ]" o% {& V4 [ RVersion 15.0.7. `5 \8 n( m' E1 Y' u) c
Build: 36915 Date:17 November 20141 e) [4 n4 |0 B% x
1015 Support for high DPI screens using oversized fonts has been reviewed and improved.1 o( I7 C9 Y) A8 \
1335 PCB NC drill layer pair reports now correctly report layer spans for blind/buried via holes,% S6 q: P! ]/ K7 a% i
when layers are shuffled out of default order.; o: ~ `) k9 u
1381 Export to AutoCAD now correctly includes thru-hole pad geometries and holes.
% r9 h) b; {- g" Y: T4 V1382 After certain editing sequences the PCB editor would incorrectly switch to masking the display,
, E. ^' f6 h& w+ R% ^$ K6 Gthis no longer occurs.
5 X8 J" v! I+ T2 `1 q/ a1408 IDF export now includes an option to export in Unicode format.* E1 y1 D4 B! s9 n
1615 Changing PCB layer names could result in layer-related lists populating incorrectly and certain+ M; x. g4 N4 v# ^3 `
outputs not generating correctly, this has been fixed.
& R6 g+ ]+ }; g9 p+ H0 Z2613 A Vault Content Cart can now target regular folders.3 [" \: K4 v0 I1 u0 Y# `" c. K, i
2816 It is now possible to define a CmpLib Component Naming scheme using a template with) [% s, f2 {, {
values from any parameter, for example CMP-[Value]-[PackageReference]-{0001}.1 e: g" F8 t" S( n7 S' {
2817/ @6 x* l* p5 I2 j, E
The CmpLib editor now supports the addition of new parameters via customizable parameter
: d+ ~- V1 ^3 x: k2 d2 K8 B/ [- [) ^( hlist templates. Click the Required Models/Parameters Add button to access the templates' p: W; i n# g+ c0 ~$ ^
(samples are stored in the \Templates folder).
, O+ {' |2 g& H2 @9 v2855 Duplicate UniqueIDs are detected by the Schematic compiler and detailed in the Messages
2 g3 }5 j# d+ d) O- s6 y! _: {0 Zpanel. Existing duplicate UIDs are also automatically resolved during document loading.2 O- |, W9 T8 {3 ~* F% z3 p% s
2910 Release Notes column is now available when using Vault-based libraries in the Libraries panel.& @9 b4 v" ~9 @1 h: |) H* W
3006 The Component Cuts Wire mode now functions correctly when the Always Drag option is
3 A x" L% }$ T; P7 ^- \( b. ]enabled.) P' [" v4 i3 U9 z* m Y
3008. u" E; r; o5 N0 N- k+ R) H* o2 @& Q
OutputJob Editor enhanced by the addition of: mouse wheel scrolling & scroll bars when not
5 t8 d% l* W" B+ p ball Jobs/Containers are visible, drag and drop to change Job order, multi-Job Enable/Disable
1 D3 K) m# l; i, nright-click commands & shortcuts (select the container first).
9 O5 v: F' ^" r! |! p3026 Import and Export options are now directly accessible via the Files menu. Save As commands$ j& g0 f5 h+ Z& _
are now used exclusively for Altium file formats. (BC:1812, BC:2731 partial)4 v& a7 O6 [; U' r7 |6 t- h2 ]
3033 Gerber X2 is now available as an output format. It supports output generation via the PCB
- | R z+ l# ^$ M: L3 y& G; z9 Eeditor Fabrication Outputs menu, or via an OutputJob.4 A* q7 [- y1 E% t& f; Z
3035
# @* h5 e* L+ V3 K( F7 L) PIPC-2581B is now available as an output format. Install the extension and generate output via
) j6 F% H# H2 W0 ~$ M- T1 `the PCB editor Fabrication Outputs menu, or via an OutputJob. Download a free viewer from
, h* _2 p% i) H7 k5 S1 [( a7 bhttp://www.ipc2581.com/index.php/ipc-2581-files
/ B2 g( E$ P( i! i& C1 ~' G+ b3081 The Vaults panel now supports changing the column visibility and order. These changes,
2 P1 L: P) S7 T' valong with panel-section resize actions are retained between sessions.
1 C, }0 p/ `( _! T3143 Timeout errors after releasing project documents to a Vault have been fixed.
$ `, a* k# q; x5 q3188 OutputJobs now support using a slash character in the Output Container Name./ k$ G6 x7 R$ N0 A5 u
3189! G4 i- Y8 p( Q5 V8 Q# U( Z( x5 b8 a9 m
It is now possible to pre-configure the display state of Vault component parameters, via the
5 E% h T1 j) SVault Folder Properties dialog (Type = altium-component-library) and the Vault Library dialog
" A0 D% \: [5 R; L. L(add a Vault as a Library).# C2 m4 n& V/ L9 L1 F1 h- y! h
3205 Switching from the logical to the physical tab of a schematic no longer leaves artifacts on the) c _: x. P1 @. c# }2 q
screen.) B% t( }( q. r/ r1 u
3225 Schematic dragging has been further developed to improve wire/bus bending and reduce the
4 T2 e/ I- R: T; G$ zlikelihood of a netlist change.
# l, i0 U- B1 O3 @* A3227 Schematic dragging has been further developed to improve object handling and the quality of
, D* q7 z$ Q0 M+ ithe result, and reduce the likelihood of a netlist change.
1 U/ z8 D) \4 X) p0 m6 x( V3232 Polygon vertex deletion using Ctrl+Hover+Click is now working correctly. Hold the left mouse. F% C: x8 Q* ^7 ^$ z
button down as you click, until the vertex disappears.; D7 u) t$ m' m& M& z% Q9 T* }7 }
3251 Releasing projects to the vault with file-locking being enabled works correctly now
' H0 g' A- M' g- z* @3272 The schematic library editor panel now supports standard copy and paste shortcuts, Ctrl+C
/ |: t" B& E9 P% l$ Rand Ctrl+V.8 f0 ^- D- Q+ \3 ~+ n& B+ z% F
3293 BOM filters no longer mix up the parameters. Note that for an existing BOM the filters must be: C$ {. T O. V$ T, l. w x$ {
cleared, the BOM saved, closed and re-opened, and the filters re-defined./ o: |; P4 k) e n5 S4 u4 ^3 o
3338 Multi-net routing no longer creates a clearance violation at corners when the Converge
- Q. Z+ C1 ]1 M* f/ C, y# nshortcut (C) is pressed.
, N0 |! r& b! w% p. l9 P' y) ~3341 When a PDF is generated from a schematic that includes a hyperlink, clicking the hyperlink: @+ B g* M0 J0 ]* U
now opens the target web page correctly.
. S3 Z F% U; H: w' g; ^& r, T# { ~3357 Teardrop removal speed has been improved.
( N: q- Y8 {& e% }0 z3381 Second click to select an individual segment in a schematic wire now works correctly. S' x5 Q% G! k7 n" V2 z
3412 The issue with not being able to close documents having "=" character in their name has& D- u* R, [8 @
been resolved
& i$ F/ [) d* G3419 When the Interactive Router is in push mode, a via on the pushing net can push other-net
- ?* O: X8 z3 T% T. t6 b9 iobjects, including vias.5 d6 @( F+ S& u5 ? _ I$ ^. R, |+ {
3423 A specific Verilog HDL project would cause an AV on compile, this no longer occurs., e1 q" w* j+ D! |. D* A0 N+ M
3425 Update from Libraries now correctly preserves existing location and orientation of parameter
- V/ f2 X3 s6 ]- I# |$ E+ u5 @strings.+ F7 p$ K3 ?& Q: B/ c
3437 2D and 3D PCB view orientations are now completely separate, each retains the previous2 V5 F# M0 H0 H% o, E) s
orientation and zoom when switching between the views.% L' k+ R% c: R, X' b8 r9 M1 N
3441& g$ {4 W- N v+ F. E" D6 M& r
Pin-pairs have been added to the PCB editor, delivering the ability to define the path and
0 s1 {; B1 t; ~) L& T( I( ?) {+ uconstraints for a signal to travel between a source and destination, through termination9 K5 H7 i' ^3 {& c8 ~$ ~
components and y-splits.! p' J1 u/ C# r9 l' l
3442 The import of complex arc shapes from AutoCAD has been improved.
$ \$ V6 _$ c X3443 The PCB Editor now supports embedding OLE objects, such as Word or Excel documents, into" h2 A& p. m3 X# {6 h
a PCB document (Place В» Object from File).2 A( O; {$ r6 Z! s; h, E
3456 Xilinx Vivado toolchain is now correctly detected, and can also be added manually in the FPGA1 w$ s" i7 ^; |- X! a
- Place and Route preference settings.; L* u0 @7 ]/ _
3457 Split plane editing could occasionally cause an exception, this no longer occurs.
: M( S( t$ D, n9 w3459$ N. G+ c$ x; j% l3 H$ q
When a wire is placed perpendicular to multiple schematic pins and then dragged, a wire
) d& h6 @( B9 u3 h+ _* lsegment is automatically added between every pin and the wire being dragged. This fix
- v6 \7 ~4 x$ M$ J7 Brestores previous schematic editing behavior.4 o1 F7 h! d2 J6 R8 r8 R) m
3477 Schematic library editor, the Parameter Manager now supports editing parameters across T) u# d/ N6 t3 [' ~; l+ u
multiple selected components.
# Y( P( n. R' m$ G; a& i1 V. H3492 A warning is displayed when you attempt to complete an invalid blanket (has intersecting
; Y/ G' u4 k/ y. a* l/ `; o7 Wedges) in the schematic editor.( c* B& d6 Y& D4 m$ u6 ~+ i
3495 PCB component fanout now functions correctly when there is an unpoured polygon under the3 R( ^ p; ^2 a/ J
component. }, ^# S0 a1 [, I2 z6 L# i
3497 Click and drag to move a group of selected objects now be functions correctly.; @% p. [$ o, c. E+ t& m
3498 An exception that occurred during import of specific DxDesigner projects has been resolved.
$ Q3 j: i# I. D3514 PCB Step model import has been enhanced with better support for curved shapes.* p" v7 ^: E% b' o/ K$ j+ K
3521 Fileless editing of an external SIM model no longer generates an AV.
1 R, z: Z% }; v! X8 E$ E- z6 F3528 AVS 1.1 is now supported by Altium Designer 14.3.& T' R6 o* t8 L* q t0 k7 u. x
3529 Component pads placed on a signal layer other than top or bottom could not be edited in$ M c! w1 X" z
certain layer-stack configurations, this no longer occurs.6 Z8 b0 Z1 i0 F; I' _
3530 Top and Bottom Solder Mask layers are now included in the PCB Filter panel's Layer list.
8 ~/ @, l. \9 O9 O# u4 }3546 The IPC Footprint Wizard now previews 2-pin and 3-pin DFN component correctly.
$ E. S" J- y2 C/ G, r3551 Schematic auto-junctions now size correctly regardless of the wire width.
# S9 x* R& `2 C3556 Component primitives placed on mechanical layer 17 or higher now have their layer displayed" J/ u, m, d; r* s+ d* B
correctly in the Components mode of the PCB Panel.
* d+ Y, N, ~3 j* C6 I3560 It is now possible to connect to an SVN repository with a user name containing the @
; y' i) e& {; y* G/ T+ \character.; ~/ l: p6 e r% z6 e! h0 k& f) h
3561 The correct Lifecycle and Naming Schema is now being loaded during CmpLib file-less editing.4 h6 |3 N5 y, ?! c! H% M
3567 Model selection drop-downs in the CmpLib editor now display the Lifecycle state in color.- N- P( ?6 e& i P
3568 The Vaults panel now shows the Note data from the correct Lifecycle state.1 y- \( m: A3 k: V: P7 d3 u* [) E
3576 PDF generated by running OutputJob can be opened directly from OutputJob document3 d9 o% N' g9 L5 D8 `
3577 Simulation model pin mapping now works correctly in the CmpLib editor.
9 f5 B' @9 W+ G4 m; X3585 Pin swapping was not correctly generating an ECO after performing PCB pin swapping, this
9 q [+ g0 V; I% khas been resolved.
5 ?* {. K' W3 e2 W& T* G3592 The path tracing routines used for creating a polygon from selected primitives have been
9 Z3 W4 @( G# Z; r: }7 o* ?9 dimproved, to better handle small objects and multiple paths.. k# q5 k( O3 X1 l
3598 From-To panel now shows length taking via heights into account
' ?' `* z ], {% M; n3611 The schematic Place Wire command now correctly retains the corner mode used in the
x$ H9 O9 _# R0 ^1 P K" V7 Jprevious wire placement.
8 z* i, J5 j, p0 l6 g! D3626 Vault-defined part choice currencies are now used in Altium Designer supplier dialogues
" t/ q; X: G+ k7 J( R3633 Updating Altium Designer from an NIS no longer requires a current Portal connection.
) n) x6 u7 X9 w/ f' X3634 "Access denied" error when installing an update from NIS has been resolved( t# V, |- f S2 T: l
3640 Support for rectangular-shaped pad holes has been added% v$ D9 I7 l# C
3664 PCB exception while re-building a net to an arc center point in a specific design no longer
! ]4 r, ]1 \* n- l* L8 Poccurs.
: x1 S. ~6 H r8 B: D+ x" I3681 Plane connects (thermal reliefs) are now shown correctly when board is flipped
" L. W: [- F8 H( j/ `6 S8 d3689 Exception no longer occurs when choosing PCB font style in VariantManager (BC:4664)8 u# Q: s8 i- j' L5 l3 N5 C
3692 Pads with rotated square holes no longer show copper still being present after running the" k- ~$ l( X. Y m, A4 m: c0 L
Remove Unused Pad Shape command.! ~$ ? |# Z V- ]( Q
3695 GOST specific documents can now be generated in BOM Report outputs
4 ^6 L6 ]8 h; _% D: n" ~3707 "No model link found for component" error no longer occurs while editing old cmplib files5 m: y O& Z& `5 u3 ~1 ]0 c4 n+ C
3708 Clicking on a supplier part number in the Vaults panel no longer causes an exception.
" c: e3 w _ [' o3721 Occasional exceptions during a print preview no longer occur.7 F; [! {# _: @
3722 Under certain conditions changes made in the Variant Management dialog could cause an
. j9 F& t1 s7 d/ c2 |exception, this no longer occurs.: N0 g# ?0 p/ @
3729 The Variant Management dialog now immediately reflects changes to components, such as$ s1 J) \" R2 m' l7 ~$ E1 e3 n$ ?
clearing or choosing an Alternate Part, improving usability.+ a* n6 s* ^; L
3732 The Edit action is now available when right-clicking in the Search results panel in the
! M3 |" u. G' G3 p* c& }VaultExplorer
: Q, W+ U+ j. S9 E7 L1 m/ g3736 Fixed error while releasing Vault revisions with extra long file and path names
1 m/ a% x. m% V5 s+ @8 H& Z' x3737 Changes to Comment and Description are no longer lost during component release from the7 \2 h8 q- i3 r% v
CmpLib editor) j, W6 v H* P$ ?" [
3739 A Length column has been added to the Primitives table in the Nets view of the PCB panel- j& b1 x. v4 v2 Z
3755 Scope section of the Teardrops dialog was modified to distinguish TH and SMD pads
\" z1 G" V) i& F t) ^6 y3757 Duplicate Port UIDs no longer cause Port names to be changed when generating a PDF from) |) c. q& H, y! O% i
the schematic.: a# m) i6 i* [) C8 f! t& I% Y
3774 Under certain conditions, schematic compile masks did not exclude components or net( x7 r, o0 A9 S6 c" i
objects underneath them, this has been resolved.+ D: {% p1 F2 o0 y* c6 T! Z
3778 On a schematic with a lot of wiring, placing a wire with the Break Wires at Autojunction option
3 P9 e$ @ a# y4 Y; G5 penabled was very slow, this has been optimized. E/ ]" {5 T9 [
3779 Improved performance of selection and zooming in Schematic in comparison with 14.3
( h' i* F: x2 z+ M4 W3785 Under certain conditions it was possible to get the PCB Layer Stack Manager graphical
; {1 g9 p) w; P' hrepresentation out of sync with the tabular layer detail region, this has been resolved.' {1 f* Y. k) e6 q/ g3 E7 c$ \
3787 The " rint as a single job" option in Output Job File documents now properly combines the' G) p# t5 ~/ H' ^1 c" i0 Y1 `
separate documents to a single print output4 E0 z4 Z; c; x6 S6 D% x9 P$ V
3789
" L0 _) S: i$ S. R0 JPCB re-annotation on a variant design with not-fitted parts could result in the varied parts% [! X; s! L5 @. r" h' \/ ]" H
becoming out of sync, this no longer occurs. Note: PCB re-annotation on a design that uses
% x/ t" c$ a) |" ]; y. calternate parts with different footprints is not yet supported.
, c' q* \. h3 K3792 STEP models from Inventor 2014 are now loaded without errors- G$ O+ f- a- p% Z2 ?; b; H* Z* a$ }; O
3800 Variant PCB drawing options have been updated to make it easier to understand how Not
" n( W5 @- p v/ D( Z! lFitted components are displayed.. b0 J8 Z3 K# s8 I0 d" R
3809 It is now possible to specify different values for solder mask expansions for top and bottom+ ]5 I: a( ?5 r: i" f) s$ c
layers, @9 e9 B# U4 z$ ^, M3 |/ }
3834 Empty surface constructs are now suppressed in ODB++ fabrication output.
+ S/ c% \" J3 E9 e4 T3835 The IPC footprint wizard now correctly supports defining PLCC packages with different D and E
. `% o W8 |/ c, \. O9 t( opin counts, allowing packages with any even number of pins to be created.
w2 W$ h. P$ \7 r; W/ l3836 Dragging multiple schematic wire ends could occasionally result in one wire being shorter- c6 I1 i* a, {# D% {; b
than the rest, this no longer occurs.
( v2 @; X- n' J! @3841 Reset All command added to the Variant Manager, use this to restore all parameters to! Q, S, w# v: r5 z
alternate or base component values.
$ K$ U( F, ]% h" U& l# H6 _) _3844 The issue resulting in "I/O error 103" error message when some of the project files are
$ W" q% i9 s" Q- Kread-only has been resolved' ]2 v S6 t* g
3845 The speed of updating from libraries or a database has been improved for designs that% k- M7 H1 z5 C/ C# o
include variants using alternate parts.
# [8 H, F" \& y5 b( U4 [+ ^& {3 z3849 In certain circumstances a component would still be shown as varied after resetting1 Q, l' l$ p# a1 b7 u, i, J6 w7 C
parameter variations, this has been resolved.
3 d$ u6 h3 z0 v8 m3857 Polygon management was improved in comparison with 14.3 (restored shelving, modified
3 W' |- k. z7 P1 Dconcept)
* V* s" {1 N \" y' T& x9 C3875 The Vaults panel right-click menus now display correctly when Display scaling is being used.* p, L6 O: x) i; W
3876 Elements of the Vaults panel were being compressed when Display scaling is being used, this) A0 T* {, m* ?4 R
no longer occurs.& n: N* `* d& V7 p+ I$ {$ n) `6 W
3888 Crash reports can now be send from behind a proxy: [" C# @+ O, `
3889 Simulation Waveform viewer print preview issue has been fixed.0 l @5 O1 g# h
3900 Class generation settings are now stored for device sheets (BC:3840)8 Y! E3 B& ]" N, c
3903 The time to open the PCB Classes dialog has been substantially reduced, particularly on
! m& E+ z! C! Q4 jdesigns with a large number of classes.1 a1 E% m6 ~1 v2 g9 A
3972 ODB++ output did not generate drill data for drill holes included in a panel, when none of the% n3 i) y# ^% ^1 w! ?' z/ n
embedded boards had drill holes, this has been resolved.
0 g; _, Z5 o3 x- X+ F* ]" C( Q2 }6 P3984 Drawing of Schematic Blanket directives has been further optimized to get them to draw
2 D( A! {! q3 [/ X; bquickly and also correctly display the fill color.
* d( N9 p: X X4005 Variant designs that include alternate parts with different footprints can now be re-annotated2 T! k1 T* }5 g- c" Z _! P# ^" `
in the PCB editor.
9 X b9 T# ?( V6 B& ]0 ^( ^8 V5 s4016 PCB DRC now supports stacked alternate parts in a variant-based design.$ ~+ _2 W$ L4 }, P. K+ D+ Y( L
4049 Signal length column was added to Nets panel (this length is being calculated using more
3 G. H+ E# q* Z# w; wprecise xSignal engine)
7 A: ]9 h! R ]% ^6 v. x& h4062 All extensions within a group can now be installed in a single action.$ P3 i4 c1 q/ M- p* |4 |4 b
4069 Some PCB dialogs were ignoring the board units and always displaying in mils, this no longer
) h7 [: K- }, ~: t" q" ^+ V9 Noccurs.
( s" x& s" n* `- p; c4076 Modified Polygon rule support check for shelved polygons9 R0 `6 Z: P1 s$ l
4083 During import of a P-CAD PCB file the layer types are now correctly detected and assigned for
, I0 v _1 [& J# w8 C+ y M aall possible layer configurations.
- U( a3 \' W1 l/ _) F+ K7 F" x4092 The DRC Violations Display page of the Preferences dialog now displays the complete list of
& D5 R+ t! L5 H" q% e. h7 `8 uDisplay Style entries when Windows display scaling is being used.% j. G/ i5 @% h
4098 An AV could occur while placing a pin in a schematic library and pressing Esc to quit the
4 Q+ R$ e4 p2 x, fcommand, this no longer happens.5 @$ q8 u. P; f% f& H0 u
4111 With a specific combination of preferences, placing a component from the schematic libraries" f4 l/ U" ]. G- d Q9 V5 x9 s
panel could cause Altium Designer to crash, this no longer occurs.# k V" w# y5 h2 R H5 B
4121 After configuring components for pin swapping, it is no longer necessary for the designer to
& @$ Z( U7 L& N$ \" y$ Q) Xmanually recompile the design to make those swap configurations available.7 H% _+ O: Z1 s' S) J n
4133 Changes made in the FPGA Signal Manager are now correctly added to the constraint file. @% }9 T$ u2 s! @4 m, q: a
4135 Silk to Solder Mask design rule now correctly detects both silk to solder mask or silk to copper# k) i+ x' h1 N4 ^* c2 B' \* Q2 L
rule check configurations.
% q3 B0 [1 j. |4215 When a polygon is shelved, connections created by the polygon are maintained internally so# j% R$ w: U' n, I" |5 ?7 @
the connection lines will not be displayed.
" k) U1 M' j' X; q' f! i9 {5 ?, V4351 NIOS II CPU does not generates with Altera Quartus version 13.0 or later. i) s6 k8 ^7 X4 r A
Source URL: http://techdocs.altium.com/display/ADOH/Release+Notes+for+Altium+Designer+Version+15.0
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发表于 2014-11-21 18:54
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