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DATE: 05-24-2013 HOTFIX VERSION: 010
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3 c" a4 f0 H: A. v+ V* WCCRID PRODUCT PRODUCTLEVEL2 TITLE6 s' H0 c, W- Q! i) k5 P) S; R0 x
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1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
' z1 _! B) Q F4 @2 y1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
8 o- ^7 `' U$ F ]; x1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files8 J9 r; S6 ?6 n' D( a _
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor9 p" [$ h$ g L2 e
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6' h# o8 O i) _
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border
4 d( ~3 X" v# M4 t, g1131775 ADW LRM LRM error with local libs & TDA
$ w* c( q" V1 K4 G1 @6 v5 X, @1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4, U' R# C. \+ P) w% _& y
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
/ _% E- C& T8 o1 A8 q0 B1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
! N2 {& Z. N1 a: h Y1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
$ T7 A& L4 h; `0 q6 Z5 y9 g1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?- D1 u# w0 V0 I8 e& T1 _# [
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer./ K. f3 r0 d4 u& r: l$ B) H0 `7 {
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor7 [% z) Z0 p- t; a( i9 }0 L
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro) D: Z, _- y) b4 Z& B
1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
$ C! B3 |1 P5 U) F) \1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
; O" z- z& R4 G3 a9 r, a1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash
: H' E2 s" `! s. @/ w1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
u- c+ z1 g0 O: n( y- v0 j- h1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering, z! K; o2 ]3 @$ B) Z6 {" l- g
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor2 l( F& P! ]2 R% Q0 e' y( S
( ]5 l* r- x- [: S4 w
DATE: 05-9-2013 HOTFIX VERSION: 0093 B9 F% q H8 G! U, _
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- m' T2 X. X/ O8 n0 A7 c2 S961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp
7 c& U' t7 P8 m/ X0 E0 v1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function' i9 f+ H* d, M! k! C( I. n
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da
. X% a6 W4 `/ S1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB4 x9 V4 H' A/ @% D' H& i
1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6
' ~9 U8 e0 D, C5 i' }' f0 i1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock
& j" P: L( Q2 B- U1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor, C" O& e8 d0 A! S0 o( E9 _1 j
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro
f$ e/ K- Y7 e' ~0 ^8 _1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.
# M5 N5 F$ D( q# S. d3 {# y1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl( E3 Z5 a( x, S* O! z! ]
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode.
7 N3 \* X. m! w' G$ \8 [8 U& b1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager
( w% v5 f g" \- ~1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent
; Q5 ]% T; L* j% y& C W/ c1126096 SCM REPORTS Two nets missing in report
8 i+ d/ ~+ i; @6 n* n: |2 P/ o1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD
" p- J6 S# ~+ s, \6 L1 M1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.
9 E$ h, X/ F7 j0 d) k' q1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd& x3 D% Z* R1 [$ u
1130737 F2B PACKAGERXL Error - pxl.exe has stopped working! O: `+ z" E2 g. M
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters
0 H: c2 d6 ?) P& ^1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide. ~4 G2 O! z, I& q
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder.. A# N; ~) h3 Z! M4 ?* q a" ^
1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes# N+ _3 m" z( F4 x- H0 \& H
1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes& |- C; h5 H- \* r* s
- o& e" `% s. @
DATE: 04-26-2013 HOTFIX VERSION: 008# g, [# `& v1 D1 q# Q h
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CCRID PRODUCT PRODUCTLEVEL2 TITLE8 p2 X4 Q- }2 A+ s- X$ _3 q) S
===================================================================================================================================" j/ e6 N- U( ~2 w P
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
2 |; Y: e% V3 J" ~/ f1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation* Q" a% e: ^6 n' D+ b# ^1 a. o1 j* q
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
5 g% ]$ W: T/ c& T! s9 }1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.! H) }+ K; s5 V& ?( j
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section- `5 q8 a! |- a( r$ j
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running3 Z. k, E/ B$ H6 w8 o* U
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
- l; `- k; w, v ?6 _7 Q6 K$ `1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence# O4 b/ `; M' t) t
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.2 i" P4 G4 k! G/ N( x2 ^: b* D6 Z
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
4 E4 g) K ]7 @9 C( _% s+ g: a; F$ E1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
9 I) R. i' L; d7 d7 d2 {, o- B1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
R1 b- L, r+ W( w0 W2 Q1120414 ADW LRM TDO Cache design issue5 ~2 V1 T3 H% I; e: @" b0 H; E
1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via
6 ?6 p Y' }% H J9 V1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
; I! p6 ]) ^3 e. t. l/ }4 f1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
; Y! k7 G1 o; s+ S# ?& }' i1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.. [! P- N# s$ z5 h# `
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
; C G7 F9 G. D+ k/ U8 g# X1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
$ P3 ~0 V, c8 L# t e1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable8 g. m! O; q7 `1 I# _" a9 t5 S$ ~
1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
: H- B& l+ O k1123816 CAPTURE PART_EDITOR Movement of pin in part editor) B5 ^/ b/ W1 Q6 O8 w
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 500 Z9 T9 U6 [9 y3 P2 h, r |: q
7 C' F* f. l4 K( ^+ d7 @DATE: 04-13-2013 HOTFIX VERSION: 007
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CCRID PRODUCT PRODUCTLEVEL2 TITLE0 W) \1 B N$ H9 {
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2 E3 I( ]9 K3 P) J; z1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die$ {" z" J& K# H! f, n" w
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
! q$ h: M3 q% g3 F1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.
( ~2 C" D3 Q: I3 o1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components1 B% u% W4 H7 r" H, P9 |' |
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly: ]2 l! Y; S3 d) X! s' d2 \3 x
1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
. M& x+ O/ {' [% E9 k1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
- [$ C2 M" d4 ]$ {1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer., N m+ F! a6 ~
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
$ b; W" p8 e2 D: a1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
2 c9 z3 Z% j5 V" x5 o. f/ H, ^( c1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
8 N/ @: J3 R& Z5 q1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh* Z; E7 w1 v2 {" _( x) m% f W
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
7 `$ S6 L* J3 Y+ n, `1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
7 s/ X1 u. u, F8 B; {* _& P+ D1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
: D _: p, h/ n1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently, H( u' y3 u$ N+ r6 e- F
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps+ a$ D2 p; v% N
1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
- F+ J: H5 g. T2 D1 W1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
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0 g6 b, o6 a5 q f1 U" fDATE: 03-29-2013 HOTFIX VERSION: 006- \4 U: {7 J" h; Y `9 Q f
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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2 W) Z5 T1 a, Y1 g+ S" W625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.2 n% U! I# ]' O+ g) l. c
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
3 ~! Y5 e' b4 w8 {$ f* u; N0 C650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
" `+ b h m! j, h1 I B- Y653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
6 J) D4 {4 P6 P8 L K" s7 h687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect7 W& v+ ^3 X/ l+ a
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
6 ~0 Q9 ^+ m: r825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other3 O, v1 b" i) j" `- ^
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
* S' q& i3 {1 L, v$ u/ e+ P835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.6 @& |6 Z L% y1 s+ p
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
& X/ \7 F4 p5 e- h6 r871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
' P/ a1 z. {) o& H9 ]9 w9 ]873917 CONCEPT_HDL CORE Markers dialog is not refreshed4 E9 C# P. W- x; f6 @+ [
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
" M) n/ d! w7 u& i888290 APD DIE_GENERATOR Die Generation Improvement) `, L8 R; [) X
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator# O$ ~ k6 M7 [3 l5 y/ z5 E
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice" y" P) T' p, V
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
]! w6 U5 [1 l# y% Z; C922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
8 Z H9 V/ G# s* z& |923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
a: o$ f* U$ |935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC. N0 Q. D. ]: G/ R c( _
945393 FSP OTHER group contigous pin support enhancement
$ v2 `3 |$ X1 G1 r969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
5 a. d8 Y M0 E6 p" e7 ^1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes0 K3 f v! d0 Y4 D8 n5 g. [
1005812 F2B BOM bomhdl fails on bigger SCM Projects
/ n5 ]0 A& L4 [" r: L4 v* `9 B1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture: j2 s1 |- `. i3 N B% O% J9 f
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names5 A: w; H# h7 u6 K9 A
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net, a: N9 U: o4 \) w
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical8 S; r6 z: b9 r5 n& X( z! A
1032387 FSP OTHER Pointer to set Mapping file for project based library.
) k; g1 D- E2 g+ p- P/ x1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 燕LL PLL_3 does not exist in device instance�
2 _) Y9 L- M l2 i1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
$ [5 ]0 l1 _& O7 t" V% }% c, q8 m1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
1 n& y/ k- O3 g* e* V1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
7 ^% Q$ b e( ~: o" @' K V) X1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
; v. ^/ v. S8 {3 ]2 j, U% }1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll/ ^. K9 Z. e/ o- E, ~5 F g
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation0 s- _# p- p6 D Q' K
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects$ L1 `& z: ^9 k" |% q
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
+ p9 e& I4 \$ m) P) }1 a1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
" c' ^9 G8 ]- ^6 }! s! U2 d1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
, s% ~8 Y, F3 g$ B8 t1 b1065636 CONCEPT_HDL OTHER Text not visible in published pdf- F+ e- S5 h' _4 J% Z2 P
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
" @' g4 x/ p7 a% t3 G1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
) i8 C1 }8 |( h, j& t- P1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
4 }! R2 C1 g; }% ^$ y1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic) u8 k i' s; n! Y$ o
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
" b: A. E( T# w4 v; i2 G/ e& e1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
! b ]3 I2 \& V s, E) y7 {1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal+ N; T) A9 ]6 H6 q+ k8 o. G
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check& ?" @- X7 [' l2 P2 @% |
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.& r" P4 Z9 C9 d9 U4 l1 r4 O
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)4 @: o# d8 z" f: s2 R3 \
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die& g N! L+ @* L5 v
1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
8 E( ?$ w( h8 h1 g1 n. C$ h1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
& A8 g5 K/ x m/ g8 K- f1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects0 e8 j) M& d! z5 a
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format2 b7 H% s3 E- K( x3 B
1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net2 _5 A' a; f3 ]: X, @
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic7 P& e% {5 c# h- b. q/ A( w3 C6 {
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
( t1 u# F# r4 C7 c0 W# E+ k8 M. M: z1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
9 ?! T) ^- R* k: g0 @9 l& [1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
6 ^5 v+ C. [. F: Z5 l1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors# Z7 F6 K2 }7 i/ s2 r6 C
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.7 q3 T9 \, X7 g+ |3 a& M
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
4 Z% n) \8 ~. X3 q/ C2 ?1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
- G9 W4 @4 M- f. c1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options6 H) a3 @ M' k! |) D& F
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5- @8 F/ D Y+ h* P
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.) F& Q$ | ^% x" W% F
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
2 u' W8 h8 i! e7 F4 I7 S. j1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
& h2 R( V: ?! Y% e& F* U) h1078270 SCM UI Physical net is not unique or not valid
. L$ _: b4 r" T5 l! j1 ^1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
! i' `( l. O2 @. z8 L5 m3 n; i3 g1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
9 I- p. ^/ S0 Y6 S; [$ }1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
! b+ k' e! A9 {1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"- ^4 h4 E( J! C9 J. s4 I+ T
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
% r7 q5 C" q* V: w1 r% [1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
7 u' a7 w4 p; p0 Q& m# e1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
. z, M& F7 m1 I) x% T# E, C9 \" G$ G1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
8 U7 P/ | Z6 ~& V2 j% F1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error) X I. k7 P; ]: y" Z3 a% c
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.) ]( }% [5 b1 S+ c2 T; q5 @
1081760 FSP CONFIG_SETTINGS Content of 澹PGA Input/Output Onchip termination� columns resets after update csv command
2 M9 U' y( ~; |: B/ E6 x1082220 FLOWS OTHER Error SPCOCV-353
* {- _" f! b, Z# C! h1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.' T6 y2 O; `3 E2 ^- x& h$ G
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
/ ^ i6 h) V( i1 x1 r& u1082737 CAPTURE GENERAL The 澤rea select� icon shows wrong icon in Capture canvas.
$ ^5 S3 u* U) P3 S( X4 ~1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
% w! V" b9 ?! W9 T) u/ L1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way: X) k$ i$ t& M, `! R/ E0 Z8 G. m/ h
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
' B/ [5 m( q+ g! G" s7 d2 k# [ y2 I1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
, M X1 c% h- h8 v1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
" W1 b4 U2 I4 u: ^: F6 M# g# @" W! o1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.% }8 Z c3 [2 L& L$ s# D9 }* {
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
: ^% D6 ~9 {; _7 t |+ O1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
/ t6 R1 v2 E: I N2 Q1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
, P& W |- n3 O* g4 W/ V, S1 k1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results" g* e) o" d( m3 H4 b" W1 L
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.* U! q a, t- c3 x9 E& W6 s
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
* C- ~5 D4 R! G1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
% s) a8 `6 X+ g$ @8 V, j1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
1 j, o- p& @. L1 Z) Q0 G1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
2 V6 r: K0 W# c1 E% h4 T1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design, h+ {) r$ L7 M L2 |
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated# \! p6 ^2 [5 F# S5 |
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins: T$ Z/ w" J' a
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
' j2 C# {. J2 `( x* a) n4 g1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
) j4 r/ x7 ]' I' O, D; S7 q1087221 CONCEPT_HDL OTHER Part manager could not update any parts." R J0 G1 l1 n1 D4 |6 S) }+ G
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
+ O' S" c1 ^! m$ a; T1 p1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
$ p! N+ R0 @. |- p; s. ?9 F1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
1 n7 k4 X$ u. c" v/ ]1088231 F2B PACKAGERXL Design fails to package in 16.5
, R5 ]( _6 c% r# }- _+ H, ?1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
7 x2 }/ ?- L* ^1 S4 N1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor# n4 Q. n) Y' O, L5 O$ b4 c$ y- t
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
7 E$ @) S' {2 \1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
2 }+ w2 ~: Z& v+ a' C. _1089259 SCM IMPORTS Cannot import block into ASA design; u. A. _# ?. P4 y! F# \3 z. V
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form% L+ }" Z7 @; i, U
1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project* O1 }3 s1 R% z: Z( }; B# B6 n
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory( d/ Z( q9 T1 O! I
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
. b# v0 G3 w- f1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB1659 n1 f7 ^6 E6 [7 t7 n& Z
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
1 G" ^" [: ]$ o: m( y1 V, M; K( `1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-227 F: [* `& J3 M, i0 y' @
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.( a: d. \2 _! m2 e3 J" Z
1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
; e0 I6 x {: X- L: }- P1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
+ m* D2 H8 h4 r& s1091359 CAPTURE GENERAL Toolbar Customization missing description7 I# k+ W6 ]/ Y
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive( }+ w6 @: D7 I( m J8 S
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
5 a' R. O( Q/ ?! M: x8 t* g P/ g1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
: D+ H, h! C) K2 q: Q1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design0 |; _6 _! X( [
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
( \: k& A! G/ I, e9 z) q1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters1 F( L1 ^/ c3 f& Y0 W, G
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error! b/ U w. r6 i" d
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder! q: M: G7 v$ s" t5 k
1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor* x) Z3 ~4 J$ _6 ^
1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
, T P) w1 }( ~0 P4 A W1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
( t/ z/ M1 ?0 p) g' _" }1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
2 k# R* | u5 j* Q1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
9 @; Y! O2 |, r& P/ n/ [1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic$ g' k3 B3 ]/ U1 T
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
+ ^! ?. S; y& s- x5 P9 L) u$ k1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet4 G( ^3 S5 |0 A3 l# e* d- M
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die t& e4 d( m$ K9 f* T& ~ P
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
7 [ J/ {7 F0 a( y6 u, d+ s/ i1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3, S e- o& N' |& k( q: J
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
. m! p) u; v3 V1 ]; `+ [5 m$ n1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
/ L9 a7 i3 x/ d! z" g2 U1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically6 P- `" K5 k3 |9 m6 p
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
7 D. |! t+ t! [ U1 u) |: E7 S( t1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate2 k; f3 m1 Q% i& ]; M8 J/ e
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
0 [2 j4 n- ^$ U7 }7 A1 y9 B1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL% M7 x& _4 m2 E7 N# k) g. b# ]
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.2 W* q: X% J y
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side4 ]1 m4 B$ ?; M8 D0 @
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
" r& c$ ?- O6 S* l1 k1 g1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.; M- [0 q1 B y$ b
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives3 Z& D: K/ p' E& I- H" B, w# v' ~6 a* \
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
' y" v6 Q) |- T1 S( N8 |1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts! |5 i5 t H) _* M5 d5 C7 j8 E8 S
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
% ^+ ? d& n! J4 h0 r. S1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.9 @1 d5 E9 m3 q* j/ X" c- w: H6 H& X3 m
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties2 h% y1 ~% h% |8 r
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.63 i) ~( h6 T7 M4 Y7 h( j8 ?* D' @
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
2 R4 x8 t* `& `1 D2 x1 x1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
/ w S) v. @4 N1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad& C4 h9 z( {! l. ^4 K4 C. p, m
1103703 F2B DESIGNSYNC Toolcrash with Design Differences) S$ M9 C9 K5 m% k0 n' I
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view9 M' b1 u& C& k. U3 ?0 I j
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
- m' e# V2 K; u; a& A1104121 PSPICE AA_OPT 燕arameter Selection� window not showing all the components : on WinXP
' [7 k- `, `( R; K- L1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
9 Q8 @, H) a& O* I* g( v6 C1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
' ]6 ?0 O, \; x1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule." k; |1 s: r8 j2 X
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
! r( {$ n' j" o) j; R1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
! n6 K- @9 C2 D9 X: g z, O1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
8 z& N; \) Y: j1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
- n% e$ P3 V& p1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax+ |6 `0 a8 _- H0 n% i& W1 @' ], e4 `
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
& c' e: [ K4 \6 P1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
. F4 u& D1 O' [: F! F# `$ ?1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid; F4 N- y! y# ]5 c4 D F/ e
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
# J- {2 l! k4 m- f, N: j7 B1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param. Y/ k6 @8 ~, H. U& z% n6 C8 V
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
4 F1 Y3 w# x% `- q1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).9 n) m0 V7 { ^
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke/ K3 f5 _3 J) D0 L( F$ L1 W$ I
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.4 ^$ a7 T; E }# Q; d/ G$ x4 S. z ~
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
$ \1 ^3 M) P4 g4 F [: D1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs2 M/ i3 K% K1 R) S# m Q1 C
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6$ ]+ Z+ ~% T1 |& {0 [( I- y
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.# L+ [: v) o7 j& l
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
5 o2 w7 U7 r1 m) q9 q1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6; K& _ X K; u) J6 j# v
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
& M" x# U0 @0 x+ e& E+ E/ o' b* c1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters/ X* x8 s/ \, l5 q0 [
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
" m" S' L, L/ k' ~7 E! H1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP/ Q8 N8 c1 p0 N g$ R
1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
7 q [( Y$ }) x/ e1112774 GRE CORE Allegro GRE not able to commit plan after topological plan) a; `; d* S2 t9 E- }" U
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color., X& ?, \1 Z" Q
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
- H( h( n9 s0 v" o1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
( B& a5 x; B9 I# g2 f' a* ^5 j# I8 t) a% r# B1 p0 l# i
DATE: 03-7-2013 HOTFIX VERSION: 005
5 q- t# q w+ ^===================================================================================================================================4 t1 x( k- ~5 C6 |( x+ {
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ B* ]- r1 d4 [# B) `===================================================================================================================================* C; v, ?! Y9 |% P j2 H
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102! ?" Y, p5 W9 d" ~& h' \
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed' l- p8 l6 F' @
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
; N; i ]- @& d* N' e5 j( `1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
7 {% V/ G; v4 B1 u4 U1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view
7 i% n' \) K* `, X3 M, C- P1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
: [1 I s1 @5 n; K% ]- S, B1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
, o) s( s: H; I1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
" m' Z! G: u( `, E3 W: x1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.
1 E- }4 ^, a. z9 {5 @$ d( ?. [0 j0 ~1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
' ?; [7 \$ ]7 w" y, \* {+ h8 O1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional1 [: F- A4 s7 u3 k
7 K2 `1 z6 Y# n( C7 P
DATE: 02-22-2013 HOTFIX VERSION: 0049 X2 A$ x7 @. g3 P w/ p5 [
===================================================================================================================================& x3 a7 s, e5 ~$ W* k; P; j% u
CCRID PRODUCT PRODUCTLEVEL2 TITLE
4 R- G9 g" |& ^' i- T* I===================================================================================================================================! Z6 X+ @3 `. s2 ?7 y" H
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly
: o3 Q) w4 e" \1 ~# n* p# }; N1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing1 U# f' N( s R) t" Q8 H- d+ w
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
8 P1 ~* U L+ F& G1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition
- V9 ]' \, i0 E; Q8 @4 N1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend5 e0 V$ U5 `: e, b; l3 ?
1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report
6 v' A) [% {! f% x! u1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command) T+ q1 l ~* z( H3 {! l0 P. b9 ]
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit.6 \7 Q7 C" u, n8 n9 w4 y
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat
8 [: D: F. A/ G: D! N3 p1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.- Q3 E! h0 w2 Q1 B3 Z
7 z( t; E" f: k3 M! m3 U$ tDATE: 02-8-2013 HOTFIX VERSION: 003
; U* o" u9 |% a) N g/ D===================================================================================================================================
2 w) X" O4 L5 TCCRID PRODUCT PRODUCTLEVEL2 TITLE6 g9 ]3 u6 Z$ w8 C% m, R7 F
===================================================================================================================================
) N: e0 V( E9 R1 F- }1 t- O `3 Y1077728 APD EXTRACT Extracta.exe generate the incorrect result
: T' v7 I6 R5 Z& [/ F7 a+ k1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF
+ \% e6 M( X- N! }( t6 X8 G& n1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer1 R3 z# T+ u/ {
1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
) N+ e1 }0 v5 N9 W$ y2 B1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on }$ y# _5 N( I& `0 p4 B$ o
1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent* y7 J& z- O" X( [
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
9 S, q2 v6 F5 X; L1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor9 L p" F% R+ z% _. g/ ]
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn篙 show up after 燙uppress unconnected pads� option.- k! |3 ?) M) r. a+ Z, P' [; u! ^
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff( l/ s2 M( j3 X% B+ I
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
( u9 Y- ?0 v% [6 ^# B' \1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35
0 m/ \0 k8 q2 T$ q: b+ D$ C* `1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
9 N& E3 |% _1 ~1 g+ t8 _1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.1 f, v' L# w' `' \' e% _
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
3 u, x0 q% M/ q
" y ^% c7 \0 ]5 s( ^& jDATE: 1-25-2013 HOTFIX VERSION: 002 D7 Z& e Y6 O% T# V
===================================================================================================================================) x! }( j& ~/ J
CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 ]4 S8 _. v" K( i: m===================================================================================================================================' z' m; Q" I: n) O
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute) E! P& w1 r/ U! T, M3 V
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"- P/ {' X$ N# v: P+ j% W3 l4 y- }% V
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes! k2 T, [/ D: F) ?. Y
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
8 h8 U% _/ c! Z1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 330 k7 x6 d. X" M" R
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence2 d: p) P' s8 O* \
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
+ C9 C3 a5 B3 m" ?+ L; q1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
8 ~$ S" b% j& j1 A9 C9 U" j9 X1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
3 \3 h; d z/ x9 u# w1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
4 M# s! Z. d" |5 U9 L; q1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.; X# i# y! z# |
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.; `) r3 o" A! X3 r3 N$ n
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
- S& d* J: G" E( y5 |3 W2 B1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white/ `4 G4 Q" T- K3 W* h2 ?
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
/ s3 ?& i# h- c, C% i% @1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
! ]: L4 x i9 D2 n* a3 [ Z% Q1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.( x! a4 v) [' T6 A9 d! h% H- W# x
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
7 n9 j0 S- j6 j$ ?. j& m5 Z0 l9 v1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.8 v0 L$ ]3 A6 I4 J& l
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.67 `+ B6 ` e- z
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout% M" D( D/ r" |, V6 T- J ]
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
! ~+ r! L2 b# b9 X5 w1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.4 C) t8 F' A8 W% q1 \" v- B
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
* a9 T4 \% g$ t, K1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties" i5 ~) z8 t Q* Z
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error5 v/ X* |& l" |$ M, f/ d. k, ^
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric% g1 J0 d6 t( A' ^4 `* z8 s: Y
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
$ Z: R4 n6 ?- w, j# r9 S5 F5 P1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue$ U7 N/ f$ l5 n' c, k& k+ b
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
( X$ a+ x: N6 ?; ~" c& N1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
: ?7 V. R5 ~/ n1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
1 \3 B( V( z7 j8 h1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
0 ?' V; b! O/ [! m: m0 |% {) S1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function. d g8 X5 w! S$ c+ \( Z3 z9 v6 b& ]
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
% D/ B. o) [- O/ }1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
$ X3 a( P& P% p! J1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group) C1 n" m" w' y9 Q% _& K
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle ?2 n4 }! @9 N4 Z$ |6 z$ N- v' r( m" j
1090689 ADW LRM LRM: Unable to select any Row regardless of Status
9 T* A+ R y9 W0 ~# U- e# h# }. _1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle: h# u3 Y- `! _3 \6 z1 l' G/ M) @
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas.
+ @+ A, x E: I0 |8 I, o8 j1091218 ADW LRM LRM is not worked for the block design of included project4 ^3 ?$ I4 B, b9 ~
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads) R; @ l1 {3 j
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
# c% c! P7 @7 M% c; }4 p1092916 CAPTURE OTHER Capture crash4 D$ M3 Y! P: ~1 Y
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database
% X/ ^5 w' M3 }, L2 S% |( B8 M9 d: n9 v! _2 Z( j
DATE: 12-18-2012 HOTFIX VERSION: 001
" n( f0 ?% `) @* r===================================================================================================================================) o6 y! A! O" m# c- Q
CCRID PRODUCT PRODUCTLEVEL2 TITLE" I$ I' V4 Y3 A) }+ h2 _8 Y
===================================================================================================================================( p0 [" Z# G$ I) ^, \: j
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap
7 v# P" [. G* S0 F, r745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
) j, x; G3 B5 q0 a+ S: B8 H! G825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted
; `/ x T! N S; C7 D$ P& I871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash; g$ Q) \5 E* w5 o) t; u
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments4 H' Q" m- J% f# d/ |- b
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
9 B. z" |) Q. V" k7 }( v+ y4 N923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
! k z! X6 `+ @0 `: _ o( Y938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic! I' n8 s. s! w5 `+ q
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.' N$ `3 F- A& r; x/ G3 B$ w: J
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing: {) B6 [ L$ ~
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor: J& @4 e' }3 v8 E2 j
981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
% U- |1 Y5 ?7 U982273 SCM OTHER Package radio button is grayed out+ O- }! j# A3 E1 b, A
988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
& y$ Z1 E6 v% O" Q# l5 Q989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode( g" T1 ^/ g; D
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
, N% d# `& V" Y. q9 L: D8 h. f996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections7 r" B ?' k/ T& @7 N1 c1 M# P9 g
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?+ y1 c2 o6 S. E( p! e
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model$ W" v: d% C4 z: W
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
- p) u9 ~5 S3 ]& u3 r/ h1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg& x1 D9 h! n3 G& s6 E6 N( ?; h
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.8 S; S. w+ R7 y, H3 j) g
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
" @: J+ F+ \6 \# D6 j( L1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin& K F; v9 X8 e+ `6 w: b
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs) C( B* j. @ l9 F& t. E/ A
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts
+ X6 O7 ^& z; ]9 R1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
. j5 W! D# z( t$ j y7 _, T1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.! E6 {7 T% }" ~
1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button( I% {9 E3 f" R& f: U4 u+ W- `
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
" J$ ?, N. v) X' c$ j1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
U- l. m0 X9 Y6 L- b4 M1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed' o( E! I7 V2 U" Q
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product
7 Y; y1 S' G+ [- i2 r' o1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
/ V4 M# ^/ j3 Z r8 R7 x4 j* z. J1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
4 q" Z/ E& |8 p/ f1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)1 o# L8 T! r$ p& F ~) v, u
1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
9 z% F5 n% M$ z# C3 _; l; {1038285 SCM UI Restore the option to launch DE-HDL after schgen.
; d9 ]3 W: w" F! B2 A1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
" {7 ]5 L* n) i1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
" E* b5 b; U0 w( {, E$ z1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
0 I6 S% v& B5 R6 K8 V7 k1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing! b4 {5 o; r( ~: ]/ r
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.: d- E3 ]' o( n* C7 C
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.: w5 T. B( `. }4 S2 P( x
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu& v3 e7 X, g" N+ D
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.
0 ~8 b+ Z8 K: u4 p% [ A1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow8 Y; |* J2 Q/ s1 S1 x- T0 {0 o
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
6 u. p: F$ {, a$ k6 k1043903 GRE GLOBAL This design crashes during planning phases in GRE.7 J( V2 V/ ]) Q8 D0 T$ F5 l
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached J% x1 p+ \9 e! j
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory
3 ]6 l$ l+ I; u) P# Y) s" x6 h) B1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.8 ^1 {! F$ Z, i" P; O/ z( L9 [+ l
1044577 GRE CORE Plan > Topological either crashes or hangs GRE1 c5 o m! ~" n0 W, f3 T- y: U
1044687 TDA CORE tda does not get launched if java is not installed
* G* D2 H& U, Z. Y, C- D! V- x% B5 ^1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
$ N) m2 V9 C$ c4 {: k+ @. B0 `6 }1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.
' s4 T+ ^2 Q* v+ P0 d4 m3 u1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
4 V1 H6 C7 B2 i$ h1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
3 X6 W' C2 Y4 n/ ]3 g+ U1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
" U0 L x; d) n/ V1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow: ~7 w B* c& e7 u3 b$ W
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.9 Y. ]$ C1 n& J+ ^4 i8 Z+ @5 Y8 R
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill- d7 r k$ l$ p9 o
1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond." Q4 H' j4 A) {8 \! f
1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
2 c% K! S* o/ e) {6 M# C1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5 _. K! o+ B4 k( T
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value8 G/ ^1 O" ^8 E1 P; J E- H! D
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
& ~8 V+ @6 d, U1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn篙.+ W( r- J8 m( l4 G ]& E+ g; C& U! @
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
* X+ T; ]$ Q+ x; x1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.3 X' U, M8 A% D4 g: Z
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
, C4 v' K t2 j3 h1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
, H3 B# P, x4 `( K4 F Z. f1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.34 `1 Z+ i2 f5 R* W
1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
& S+ @3 N, D. {. Q* K/ z' ~4 q; O1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors- ^$ u& f% w) m1 _/ B' @$ D
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.0 L( x4 e$ C3 n) L( }% v1 F
1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.* H+ T+ y3 D1 w! F8 v
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
! j8 m; O# ]! T9 w* S4 H5 I' Y1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs: Q: U0 h! i- y4 f D' G
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label
* A8 S8 h: M8 Q# C8 |1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
/ K* e% i( O# u' t& C* r5 s2 |1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
* V* q% Y# l* _0 r1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down& o3 ]( J: @) B: {
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
6 U8 f8 ~3 b7 O6 r* K* ?9 f6 r# g1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.% P1 I' C: S! U8 ?2 X1 O& x
1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
. Z5 Q: a( h a7 ?7 j( Z5 f1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
; d# \. `+ v$ A# }! E7 B$ ?5 s1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.; O; `+ k+ y" ]* l
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.& F, f8 E8 D, I. R4 |
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move5 V9 g8 w1 U5 T, k: u0 I0 Q
1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value A, N! {6 [. F5 [# u
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer* a& }% ~( |' [" K, i1 Q* v. P
1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report$ [8 ?& Q2 [$ v' g# ~) R1 D; i, C
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.
7 y% `# z3 s% F1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
Y) d0 j* t" Q3 ]( y1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.! i8 F% [ a4 C1 H V9 l- ^5 U
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets/ x/ H3 v% p( c5 A1 \
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?4 x6 C- T$ _6 l" k0 u- o: l3 L( x4 I
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values. S& w z0 m: ]6 C
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
, s: d* @6 v2 R1 v2 r0 I1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00; V/ v, Z2 d, p3 M0 @/ s4 Z
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation( u; L7 Q, K5 a% S
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed." |7 G' X0 X3 G$ L& ]! v# y! g0 w( t6 w
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken9 \+ P4 k" o, }8 Z& v
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
( E& }: A% }% x! h9 ~1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.5 V! s3 \ \2 [; s1 d
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
# R1 Y( W/ J U4 G2 S1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design0 u4 M* J( N; [% L1 R7 v8 }
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV, M, Z0 C) C( H3 L) T9 ?" o$ ]
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.$ g# \# t5 B) T- c4 L
1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X* m4 Y; y3 ^' @7 m5 L8 Q! y# R
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application
( g6 x7 {; x, O1 L; }1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
; P7 }+ m- b; X: `; q; }' x1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
. t, z4 x) @2 K p( j, u- I8 l1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
1 X. H4 F9 R7 T) e% W/ E& f; R1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.8 z5 v B- S7 A$ ~' H( r* r
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file" ^$ o% M5 x4 B3 e, d& S: k
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 盧hange properties� command( T2 a- ?5 m# S- \/ ^$ a
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended: H4 v' c0 I. ]
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -30000679 v5 V1 ?7 ~' X; _* O
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design8 m6 o+ V" y, i) u9 z3 H
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify4 H( e4 y2 |( E% O% i
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids* h2 r* Q: u7 a, U( T- @; N- V% B q
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes h3 C8 g1 r, z
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow- {6 s. L) Z/ x1 M5 o
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal
5 m( t0 G; K2 M' `, f1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.6 ^$ j8 }+ |" i
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6$ _4 h: D, `$ L$ X
1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
' }. h% t/ G {4 q" X% T! C1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
& M; x4 @/ ]+ {9 | b1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
) y- n% u; @' H# v1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor
! j* A8 t9 O! {5 e5 b1073464 SCM SCHGEN Schgen never completes.
, e2 i# U6 R! Y2 y1 `% x C1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory0 s4 v: t' F: ], ?2 i; E8 q
1073745 CONCEPT_HDL CORE Import design fails
$ d0 @& h& a3 F3 S4 e/ r3 A1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
|' u1 }# u0 n+ P: F: B: w2 |/ W/ X1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
* J2 P' j& i1 b' w& D1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
6 r( D: `: d' e6 x1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter& Y; ]+ Y& W! v- I- v
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
: b( p. V. s- _- v1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
7 E1 c" Q4 _! r) T. P& P: E6 R1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
. p% f: p6 V* E# [5 O- P1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
7 r% C8 p6 U) |" w' f0 K1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer
' { X! ?+ n& |+ u1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces. Q G% J8 k9 w) P! w, N% W# s
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
& I) k2 v, q. i* f- B4 F! {: u4 Z1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix3 G5 `! }+ \) y
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes& z8 M0 w% h1 T! n& |: B
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
2 C" v- b- b6 p1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
) K$ H% Z+ _ A9 g' T1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
& N6 r" }. t% n3 x0 f' R1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.67 q, m2 M& b$ P# H/ `; c) O
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
! _ ^; a& R# R" F% G. u2 K& E/ o1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
& H' s3 t, |4 T* K9 @+ k1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
3 w1 N0 R1 R1 z$ w, T8 l1077169 APD SHAPE Shape > Check is producing bogus results.9 ]7 O3 _ x% v' A) v: `
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.+ } k5 m3 c4 X- V6 S* U$ y
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim- k) g" }# o; n: q' W$ @
1078380 SCM OTHER Custom template works in Windows but not Linux+ E- C0 r" j) ?4 i5 M
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
1 {0 E9 j% o7 w8 j1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide7 z* H% Y ^* }; f
1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
7 b1 |9 s) `6 \& Q; F: ^1 K1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"4 k5 a' B" n9 e+ \
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
2 |, F% N5 t7 O3 X0 Z1 D% F1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
& h7 V4 v0 z7 H6 E& w3 R5 K1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
& [& ?9 M1 ^( P. l9 C: ~1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release./ D c7 w- ` k' y8 U; h8 j/ R
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发表于 2013-5-25 16:00
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