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本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑
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别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了
4 c# ?5 S7 G& ] KDATE: 12-18-2012 HOTFIX VERSION: 001
8 e* L: l& z2 c===================================================================================================================================* ]& ?6 j+ i: K% _1 q
CCRID PRODUCT PRODUCTLEVEL2 TITLE1 H) ~& u9 G9 ?3 U0 t
===================================================================================================================================
7 p% d2 |" ~0 j, t501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap3 `: I6 f8 @& q3 k/ r! v
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched
+ @% D/ D! t( L$ q( T$ T! _825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted6 A& e1 Z. k$ _! F; J+ x
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash2 C( E9 f) k9 \
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
7 o' T# N8 E: ?% z. z! q898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore, r% e/ ~9 ]5 l! Q
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties
/ E/ t' X" Z0 P938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
2 B* l7 I& \; n; Q% v947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.' k" g- S- X/ L* B6 C' v8 f) R
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing6 R/ Q; r# p0 c& g5 l
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
7 v# A5 ^$ p# R( s981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
+ u% J! V# o w. F982273 SCM OTHER Package radio button is grayed out
, |. K6 `) x$ F4 F988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command
# T% z6 ^3 P0 P; O989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode7 s/ z6 t; J) J i6 T& d: V/ E
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
6 _# x8 T" H2 [2 X) n# {996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections+ \5 H2 q" v* I; K. d" j# {; k
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?% M' f: _7 @0 {2 z- f7 B/ E* c# ]
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model: |6 S8 z+ D- O
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs, \6 ~2 C) ^7 `& ^
1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
a$ B9 W" Q; v. g% g1 w1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.
/ K" G, I/ `3 j4 ] Z% v# V* e1016859 SCM REPORTS dsreportgen exits with %errorlevel%
5 y! }$ P8 {7 z7 @7 G5 i1 W; y1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin# K- _0 b# n& \/ Y; Y! g
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs4 ?! t# P X8 ~( D1 N
1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts( s: T" W) j0 M$ V
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
5 T( r* V9 l/ o3 C8 C+ V; L0 r1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
( Z3 `0 _' I+ G1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button q' g8 t& I, M4 R( t- M2 [: v+ w
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out
" r- i3 @' M8 f! P5 P! c1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist
0 R, T) g' K+ H1 I2 C/ b. c5 J1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed
) V# E$ ]# B6 W' ]# o1035624 CONCEPT_HDL CORE Options pre-selected when launching base product% m1 P0 n) K2 [) e& \
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
! F% [# w( C5 O1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it." v- [) e- U: _' y8 c: n
1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
7 p: o8 @- c5 q f% p( p# ?4 b1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
; {% I" S+ q# H4 N& h# ?1 _1038285 SCM UI Restore the option to launch DE-HDL after schgen.
% l3 ^$ }2 o' y4 M1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself.", a7 U9 V& T8 w: F7 ]( I& k
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro
7 o F$ O5 C2 {( s9 c1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected3 z: a9 Q! g8 O: G
1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing5 p. q& |# E* ^6 s
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found./ B; v! o4 } I, u. x& Z; e
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.4 e% C4 F7 ]7 {; P& J! n9 |4 \
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu" ^! X3 l# t& N8 P
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.8 B) n8 x# W& g$ e( ]0 l
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow
, ?- J0 a/ i& Y r7 j# W: }1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory! B; L0 O' b/ P& b# Q
1043903 GRE GLOBAL This design crashes during planning phases in GRE.5 I* L$ B+ O/ b9 \! G
1044029 PSPICE ENCRYPTION Encrypted lib not working for attached4 c9 b) K! ^7 r( O- T B( G
1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory7 X0 w, f* t( R" S. n+ b
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
0 H9 z; w! S5 r. @2 C) y1044577 GRE CORE Plan > Topological either crashes or hangs GRE( i e; C4 i" D' Y1 `0 `0 b9 a" l! c
1044687 TDA CORE tda does not get launched if java is not installed5 {9 i6 \; `9 {/ b! O# y1 \: q+ b
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
; G) u3 X6 [ W4 _5 q y1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.6 M. `* h9 B+ P# N& }. ?9 ]
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?& I7 w5 q/ d [' U0 l
1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.
9 w2 t5 X8 K, @4 m1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.
* f8 T- z* _ p. t$ d1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow' A' v% A! g# f2 x
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.; L/ s! D6 i, n7 O
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
- W# V5 {5 z8 F0 |/ B8 D7 m1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
# g1 d2 q0 x: h) v1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5, ]0 f$ C2 W8 M" G, |
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5
; s W; C5 @& g9 v, }1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value3 j. W0 F, f& ?
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version
, ?- Y3 z) c1 Y. I% ?$ x" `/ W1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.1 L2 E. Z# v, d) W& ]4 Q# [
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
; J6 O/ Y! p' {4 u/ v& Z" m1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.8 W: P7 J* t3 C' M M
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes+ A4 A% g. y) N3 x( j) O7 i" ]
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.
7 R y2 X: m, q+ Z, x" D1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
+ K: d" [& b5 P* c' {6 M ^: V' S1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file
1 b7 S$ `6 T+ T, ]. @1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors: `' D& z7 J0 w: v8 |- N
1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
( f. x& l$ D2 S1 E0 I1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts./ l( p- N" p6 O l. I+ W! ^9 I
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
1 U" @" y0 w# t) L* ^( A, k5 X1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs
s7 o8 r, o' o( x0 s$ m7 s1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label. }: O5 A/ L# }& l# l9 e" c) {
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.
; V5 I1 I7 L* ~; z+ C- z, c1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy& v+ G( Z& \0 U9 Y) y. P$ v1 V
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down
" y, X6 P' T3 ]* {8 ^$ H$ h1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
; {# w2 ~8 D, e/ p; B G1 v" O( W1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
2 C6 c% d% w- t0 |1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views& M$ Z& ~+ d) O: ]
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline
7 U9 s! ]9 @: |6 ~( |1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.3 L7 b' x) f( Z% v8 `
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created., }2 i: o8 x0 M5 _; L* n
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
* B" Z& d& |3 ^2 L1 j; D* `1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value5 ]8 H+ \9 ^; ^3 }; J
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
x: t1 i9 I7 z9 t1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
! q" ?: G9 {, u3 ~- Q: k, p' h1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.7 V# C$ L. J1 c' q4 K
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete
8 s0 e( V' b, w0 [' v: v( D1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties./ G* l" A1 G( m# [8 f! J. \' e: E, j
1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets p: T. f5 Z, `$ ~; S" I
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?
# f" O! ~7 R1 X2 E1 ]+ b1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.0 W, J4 X8 f" u- ]* z
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
( O9 T, t( g: S1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00
% E6 P0 Y6 U. s7 y7 a1 ?1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation& J0 F3 O5 r, U4 z5 ^4 v' T
1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
2 q5 F0 _0 K3 W, `2 x1063284 PCB_LIBRARIAN OTHER PDV Save As is broken: R+ J0 R) [. C# b5 C
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs
: q3 h( S( s; P g8 Y1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.9 X4 p2 k+ M7 ~2 Z
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager. W; l& `/ Y( a& B3 O
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design O. S1 A$ [1 \/ f' W! g
1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV
6 x6 d) `" \$ a3 O0 i1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.
8 N3 w) B7 b5 M: p4 g# O7 Q1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
. `/ C0 F* O+ j' A8 N9 C1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application3 t& z5 V8 n' ]- E/ j
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
9 _8 _' V& ?* u& y1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
# ^. U7 a. |+ D' q; u1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic
) y7 t; s, `+ }' _1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent. q% N# P0 F: K! I3 V
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file
: d W& P! L K1 C3 C2 A1 w1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command
2 A8 V9 D+ F& u: i( H1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended" d) y8 o t. y: B
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
. @9 p6 f" D# V# `1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design
+ ~; g4 v* T5 u3 O( D1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify8 }& T. I1 X( [! Z. a( t1 F8 z
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
. {0 [! {7 _* C' r) m1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes2 |! b3 a4 _7 f/ V) F4 { X O
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
5 S5 {' s4 w! B2 h7 R( [! W8 h1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal9 G2 _+ n I5 I( m
1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
Q: v u _' K5 @1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
# n3 G3 K9 [$ S$ ]" ?( M1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5
6 t: n: r! I+ W( L$ e/ }2 S1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
$ G' O- P1 ~9 e/ e: I1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
% P1 r3 Y* l; W- T' E1 |% n9 V1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor5 y1 r2 y6 R( W# o9 q" d
1073464 SCM SCHGEN Schgen never completes.
8 c* N' E! T; D' [# L o1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory
+ K9 Z& ]7 p3 K- k N+ {1073745 CONCEPT_HDL CORE Import design fails4 B. t, q8 \* S1 [1 y$ d
1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
( V, N T- q: d% m1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE
1 m9 l0 {# w2 C1 D9 C4 z4 V; T1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
* H2 y) {8 |/ A1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter
! h/ O' G$ E6 A! p8 A% P6 z2 f1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal$ `0 l2 c0 q& N% D; }6 r/ y
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.
" q% g9 p2 ~1 n( H" u9 F1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI& h6 s; C: d; C0 f6 \4 {
1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block
; G& ~5 {" H4 J: |1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer7 F. b1 _# u. f& Y7 _
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces6 l* L$ b+ G3 X; P1 |( Q' n$ H
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
4 C$ O' X4 V6 H) e1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix
% P4 h0 L [/ o% C' s1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
- a" n# _: ]& ~8 A$ N' V1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top: ?; f/ B- \ m2 V5 V( \/ n4 X+ b+ |0 D
1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
. [% l0 p, n3 I$ r0 ?+ T, I: n1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value* l+ A( I+ O) L6 }; U- ]' n+ t
1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6
3 j+ H1 o9 g1 Z h9 a& h" D' y1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey
8 {2 p# s/ ~1 `3 r1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database
' v: l6 _# Z: ^$ ?9 k0 a d0 }% R' h0 u( [1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset; D0 O$ t/ I8 K$ n3 l# [
1077169 APD SHAPE Shape > Check is producing bogus results.; i! s* Y6 ^) \1 W8 f
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.6 S+ t; [! x1 o( Q, C+ g
1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim+ o% G! Z# @5 f! S' l
1078380 SCM OTHER Custom template works in Windows but not Linux
9 U& y& y" g, B% `1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.+ H a2 q. |0 W
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
7 S. y/ d" {8 K# R1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
+ j5 j& W( S/ e4 n/ v3 O* d( n1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"
# ]" B) Z6 S8 z0 n( j$ m3 i# D+ l1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
9 T4 M. V- N+ J% Y3 @1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control* ~! e, q z {/ D
1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
* z9 s, }+ ^) f$ Q# \& j* R$ G1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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发表于 2012-12-17 12:49
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发表于 2012-12-17 16:50
