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我的还是不行呢，
* e3 g/ I- T+ g& D$ T9 \, ?Translating E:/SPB16.3/Allegro/temp/project/S713OBX_SUBFPC/S713OBX_SUBFPC_V1.01(110503)0950.asc.
8 [: }4 h4 W' [4 fUsing translator version @(#)$CDS: pads_in.exe v16-3-85D 11/3/2009 Copyr 2009 CADENCE DESIGN SYSTEMS.5 g4 D1 R- J' Y, ^9 o7 K
Reading PADS ASCII file header.
* [! k' b) w5 k% I2 H Version = PowerPCB4.0
- ~( |, d. ?' d& z Route Layers = 2
+ K8 A3 h6 t" v. D4 f# H5 B# q Units = METRIC" G5 L9 u" i0 U( n
Hatch mode = Vertical / Horizontal
2 ]6 S& C1 j, Y$ s1 \ Hatch grid = 0.100000, angle = 0.000000, anti-pad spacing = 0.000008
# i, U: E+ v* `! l3 l/ g* h2 n- `Initializing new database.) U/ X+ ?4 F% k \8 [
Creating layers.7 `7 W& v; O; M
Reading PADS ASCII file body.2 N7 E/ j2 _7 k2 v& b5 N& B
*MISC*
$ e4 I& d+ \& a4 o4 I9 ?0 s *MISC*2 N# z' g( y7 X% |9 U: O, g
Information: CSet 1_5_6 renamed to DEFAULT
* A, p; b! V y7 V5 r
6 D: ?2 D3 T- M" ^& s# EWarning: Allegro doesn't support default electrical CSets.8 o2 z! Z& A' J0 A
*MISC*
3 }, G; ]4 ~$ i) q+ M; L1 q *MISC*4 l) Y5 R! H s W, r; P) U) Z
*MISC*
% H! `( P# ^8 n! n帮忙看一下什么问题呢， |
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发表于 2013-3-10 11:44
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