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求助capture原理图导入allegro PCB Editor$ T3 e& v: P9 ^: ]8 h
刚刚学习allegro,请问网表导入allegro PCB Editor时要怎么设置?导入网表之前要做些什么准备?
& r ~9 o# C: R* K在原理图中我把原件的PCB footprint都填上了,跟allegro里面的封装名一致。其实令我很疑惑的是,仅仅3 s0 X5 x! J" B# X
是在导入网表前设置了网表的路径,却没有具体选择是哪个网络表,加入我的指定路径里有很多个网表,那
$ q: p& N4 S/ O0 ^; r' P# j. d+ X岂不是很乱,所以我把原理图的名字和PCB 都取同样的名字,而且存放的路径都一样。但是都不能导入,我怀疑是allegro里要设置封装的路径,请大家指教,谢谢
& W- z- A5 q5 @; i+ K. v7 ?8 S6 m下面是导入错误提示
$ N$ s. I( _/ O: g3 F1 ]Cadence Design Systems, Inc. netrev 15.7 Wed Oct 27 14:42:35 2010
, O# f/ x0 ` r- S" ?& g2 d& ~" j(C) Copyright 2002 Cadence Design Systems, Inc.( p% O- ?) [; L4 _! f8 Z$ u
------ Directives ------
& S) k. j2 R) w: M- z7 l5 HRIPUP_ETCH FALSE;
" g* K0 t# J* B: i8 h# pRIPUP_SYMBOLS ALWAYS;
: H' e1 f, A( J1 y+ {% CMISSING SYMBOL AS ERROR FALSE;9 D( Z6 k1 r4 V+ _0 F$ A
SCHEMATIC_DIRECTORY 'E:/Cadence/work/pad';
' `" U% |) _9 K2 C) L, J9 U; `( E% yBOARD_DIRECTORY '';* u' g4 x$ I( Q! c" F
OLD_BOARD_NAME 'E:/Cadence/work/pad/MYDSIGNE.brd';
1 X6 R5 ^: j; |1 R) H; `NEW_BOARD_NAME 'E:/Cadence/work/pad/MYDSIGNE.brd';" G# K) d$ b' R; `; _* c6 V
CmdLine: netrev -$ -5 -i E:/Cadence/work/pad -y 1 E:/Cadence/work/pad/#Taaaaaa03360.tmp; H. Y# B- i$ T7 {3 h4 u' r% N/ |
------ Preparing to read pst files ------
9 K6 S# S" I; k) Y+ M1 |! ?# V' B- f+ L/ \, Z$ h- G
#1 ERROR(24) File not found s& B) `. X% }; k+ q! r. @/ o& t
Packager files not found
2 o# v7 {+ E% |; W& ^# o2 E3 c2 A#2 ERROR(102) Run stopped because errors were detected
, @9 q! j" k; c' jnetrev run on Oct 27 14:42:35 20107 ?8 Q8 S# ^( W+ y' e
COMPILE 'logic'
' q& j& b S# l CHECK_PIN_NAMES OFF
& @6 Z+ a% c& R- z% ^ CROSS_REFERENCE OFF, t' R; a$ L R, C8 v
FEEDBACK OFF+ w6 B" A u2 [ I3 K' X2 O" }1 ^
INCREMENTAL OFF$ d* z5 y! \, I6 g7 f
INTERFACE_TYPE PHYSICAL* j& Z3 E9 r$ J+ P: E1 _: p) s% I8 \
MAX_ERRORS 500
) f& ?. z* O2 d" P MERGE_MINIMUM 51 V( [/ G5 O3 F5 z8 a8 c
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
' N4 u$ P7 o( l% z8 X+ z NET_NAME_LENGTH 242 }( L7 y& |8 c
OVERSIGHTS ON( l6 b7 n+ _3 I6 Q4 M9 p6 N* o
REPLACE_CHECK OFF
1 U. e6 I1 ]6 m" v* f# e SINGLE_NODE_NETS ON! x% k" C$ S# b% a8 N6 s+ Z
SPLIT_MINIMUM 0! K# z- R; G6 Z
SUPPRESS 20
* {2 \1 p0 U- F" X! \+ q) j WARNINGS ON
- t1 \4 I/ O2 k- O 2 errors detected [3 @0 J. ?3 L* N3 @) W+ t) E) ?
No oversight detected: o1 Z6 b, b3 L: U( S) _3 x
No warning detected. ~2 Q, \* J1 k% N! N8 q# x
cpu time 0:00:049 g: c4 ?2 o4 r9 t/ ]
elapsed time 0:00:000 v8 ^. h$ f* b" g1 W+ h! ]( p
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