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本帖最后由 yulizi 于 2011-12-22 11:18 编辑
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DATE: 12-16-2011 HOTFIX VERSION: 013
6 \4 @) l. ~2 X- Q===================================================================================================================================
$ [9 @. H: R& l( ?2 M$ ] _CCRID PRODUCT PRODUCTLEVEL2 TITLE% p+ f5 U& ^% ?- y+ Q+ c' {9 Q
===================================================================================================================================
! ^( d/ Z( B7 Y) L. M) X; c875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.$ o. `# z' z" t
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design+ `4 j* }; W1 G0 U
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
3 N5 a3 ~. W$ o `! ^941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window& o# ]; V, \# `/ Y
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command r6 f' V& a# ?$ T. p9 J
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
% n9 u, h% V0 Y0 G946770 CONCEPT_HDL CORE 揤iew Design?function is missing in Windows Mode after reseting the menus." P: z9 p/ Z8 i
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
6 Y* m! j& y( v: ~953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
1 w5 _& m1 F, F953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
, N9 ~+ A/ f9 ]4 D! q953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly1 j" e4 ~! Y* S& \
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes?
% t) }- t! }" y! b! n" c9 @9 d954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.; {% A/ X0 h+ v* a
954498 SCM B2F SCM crashes when importing physical; f( Y2 d: x* T1 ?, r. p Y+ ]
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?+ G# @& j5 d: R& U' A' g( n S; {5 I" B
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
$ X% @0 c0 y$ D; E955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view7 b9 j# ~, \& {2 p' `
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.4 Q& ^2 R r# M/ ^2 \9 Z5 t
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window2 c5 m r! y/ _2 A
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039
0 a$ {2 ^8 R4 b( [; t$ D3 i+ r955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME# S! m/ s7 M7 e7 `; |4 Y/ i# ?
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL3 t# X# n/ R: O; v8 X U7 c5 p
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
% k0 @; `6 ~4 u" }, y# v1 b955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
6 \- m" f1 l7 Z$ M1 I& [2 [& |955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void
, ?: E1 ]9 K. n956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
5 k+ E& L$ D! x! t1 V1 V956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file& C) b; K& }! Z$ u0 r4 m
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from "Properties" dialogue box.
( h' K: W2 w! Q& M( y% X956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
. i! F: |' h; R, ?! B$ J956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined5 Y& ?5 X6 ~& P/ i l, x# t
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board
4 d0 w* J+ {" W2 p956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component7 D" a0 c, q1 H2 G$ m# W
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly! K7 M1 R# `& Z# h
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5: D) e- j7 }# i v# D0 ]% s# P4 W
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results8 F" l' H5 v( D( l, ~: M* m: r
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
8 n0 x7 i8 o N( Q; K957009 CAPTURE NETLIST_OTHER Problem getting database property in Mentor PADS PCB netlist A) \' T1 S( F" ]5 ^8 D
957137 APD DXF_IF DXF out command dose not work correctly.
- `3 r! |! R: W) a, n, ^. q957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
6 d3 ?8 O7 R+ H5 `$ N/ ~$ b957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment., J7 j' f: I" n, m& D, b) G3 r4 K$ Y! X
957267 CONCEPT_HDL INFRA Packager Error after Import Design$ i' p( {/ r6 l+ ^
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
0 C( z F1 k, ]" f# d958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.9 X0 _: V, Q2 N% q! B2 I* r
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design: ^) Y3 O/ `8 p' I
958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
3 x0 x4 r. l v/ V. Z+ y* j m7 y958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
h3 R; @5 }2 F }958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
4 [% A G; {" a9 X3 z959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
3 S& X/ Z! ^7 D5 J959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs: u* L0 M- \3 o5 p" j
959253 CONCEPT_HDL INFRA Design will not open
" j: I- i, q% M( s) `6 f2 ]. e3 }959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side
4 |5 B# H% J/ l& n$ e. G& j5 S959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.: }( s. v. w$ Y. j1 T1 s
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred: G+ k. C: z+ m6 G: o
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
. p+ m7 a' o5 a2 D$ @6 S! ` Q960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
/ \" N/ W7 n% S8 ^/ s# p960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter1 C% T+ s, w g! }) m
961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3+ A9 m* I8 {% i( t
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
5 z( N! a% c' P H- {" ~" w962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers |
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发表于 2011-12-22 08:57
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