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Translating E:\WORK\TEST\1.asc.
1 N: |+ E, R) M# u7 hReading PADS ASCII file header./ M0 V$ f/ n8 N- R* w/ v& Y' g& K' D
Version = PowerPCB5.0
3 N6 `4 y0 }, H; T g# O! N9 U Route Layers = 4
, p/ W# e( u+ R% | Units = METRIC1 E; C! @! U( z# J
Hatch mode = Vertical / Horizontal$ @8 O: s: n! \* ^9 {
Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315$ s0 J; o4 t& g9 W
Initializing new database.
9 s" P6 U [- F; P/ G( \+ d Creating layers.
2 r; _; G$ D: i1 K6 e( r" AReading PADS ASCII file body.$ D" _* i/ b8 U8 M" r
*PARTTYPE*" c* k" ?8 X2 w. z7 h1 S+ |
*MISC*4 A' f1 e: q+ s
*MISC*
. E" t6 s$ I: _, ?6 T *MISC*5 S; \' O8 }% T6 y8 n
*MISC*
. [9 A2 i. [, s- p" I *MISC*
2 o+ ]% B. f; F* M *REUSE*% T2 w. Q4 }: q3 j2 l2 Z; p+ Y
*TEXT*! V1 r4 ^) y1 [: Y7 Q; g
*LINES*
4 l9 }3 [3 K5 S- P+ G0 ~ *VIA*
" y6 n2 k* z$ _- ?% M' i" d7 a7 { *PARTDECAL*
7 x+ B3 z) c6 w( } *PARTTYPE*
/ j) _0 t; D8 ]2 a2 V *PART*
1 M( t l/ w- {* N *ROUTE*
; p9 X# a+ } N* F4 U6 M' \# A9 J Writing routes.
: n) b$ Y3 f& r2 f2 ~* \ *END*, C: _- \2 o2 S. `
% P l# q2 o5 z: F, V# n, X===============================================================================' z6 D2 J9 C: W
PADS layer usage summary:- Q& b/ o$ m& q
Layers 1 to 4 are route layers./ q O. v) U) b% ?2 j" s3 G% I
LINES:
6 t& }" y% z- }& X0 w 0 BOARD GEOMETRY - ALL
9 @5 f# c; P: B5 Z# G L 1 ETCH - TOP
% l/ H1 r. m9 I. X 3 ETCH - INTERNAL2! M+ F) _, S! Y* \
4 ETCH - BOTTOM
3 j- e0 h; ^& h/ X 9 * Not mapped!7 k" l r5 g! e3 G0 l4 M1 K% g
10 * Not mapped!
- j; B5 u( ]7 ^) a$ u; f% I: _ COPPER:
' ?6 g. r4 u! ]/ \! s( `5 f TEXT:% B1 `! z- T& Y9 @& j
1 ETCH - TOP# E" z; H2 V8 j2 J" a
26 * Not mapped!
% F8 \5 R% v; h7 j/ S DECALS:
$ k! q/ ]- j( y! N7 f, } 0 PACKAGE GEOMETRY - SILKSCREEN_TOP* U3 l' a. M, r; w) X
1 PACKAGE GEOMETRY - SILKSCREEN_TOP$ f- W9 p# `0 ^8 {5 q
12 * Not mapped! S. Q* C1 E- @3 B; L9 {, ?$ f
19 * Not mapped!
* L3 E+ D* {: k7 U( V2 q& a 26 * Not mapped!
7 s8 V9 k, H }, ^4 o PADS:
. J' ]- Y. A0 V( ~0 _1 l 0 ETCH - internal_pad_def
6 A2 L5 u2 X2 x9 r8 b! r 1 ETCH - TOP
* i1 ?+ U* e' S0 S+ Y- P$ M 2 ETCH - INTERNAL1
( W# @) |" P8 g3 _9 F 3 ETCH - INTERNAL2
& i) ?3 U4 U( B) @: B" E! P1 j* G 4 ETCH - BOTTOM8 G. I/ d+ G, Y
6 * Not mapped!7 C& X& |) _7 F) V
15 * Not mapped!; q0 e% _' x) l/ |* v
16 * Not mapped!
. j9 q6 ]+ O% U* s9 v7 w 23 * Not mapped!0 o. I' p. ? ?. ?
VIAS:
: r' V7 R# [: C! s; H 0 VIA CLASS - internal_pad_def
- \8 h5 m; x2 h$ ~& E 1 VIA CLASS - TOP1 ?. O0 G7 U$ ~4 _# I! A" t
2 VIA CLASS - INTERNAL1
' T' x) q G6 ]/ B* O2 g- Y 3 VIA CLASS - INTERNAL2
" k: o9 b* [. G8 l 4 VIA CLASS - BOTTOM
9 m1 F3 t+ z2 l7 L8 V# W, w: T8 f+ o5 X' ]% n
WARNING: 63 data objects mapped to the UNUSED class were ignored.
' w7 \3 S5 N4 ^ Z. I4 D, S$ _' N===============================================================================5 m( a! @1 c- y8 }# {7 h, R$ w
8 m$ B' q3 l$ L( MCreating E:\WORK\TEST\1.brd.$ D2 q4 k: l$ N4 p$ G
Loading netlist:/ w, N* ^- M+ i
E:\WORK\TEST\1.TXT7 p4 |* @4 u' V$ ]2 m
Writing database.1 [, j4 U4 u9 N+ i. f9 r! Z9 V
ERROR: Error while writing the Allegro database.; c: j. Q8 `- y1 y7 B
Closing database.
: X. {% ` ?4 ^3 B+ R9 DTranslation complete.6 |/ b7 x1 t/ E* Z1 T7 y* t, U
Finished with errors!; V) H8 \2 y2 x- t
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