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本帖最后由 T45524093 于 2010-4-29 09:17 编辑 - {* ~! `, A) U6 o L
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http://downloads.nordcad.dk/Hotfix_SPB16.30.007_wint_1of1.exe" s# Q4 U B# w# M( W5 j
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DATE: 04-23-2010 HOTFIX VERSION: 0070 W! S1 {# n% F& U1 Q) K
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7 S6 m6 a4 p0 A. O% [% A/ l721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why?3 l. R' I1 Z; A1 i) s/ M- M
740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp
* j9 p' W4 E9 P' N5 x ?744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools
. Q# E5 @: Y* m, g+ U1 b+ F$ }* G747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0.
5 c' B. i/ E4 I) Q% A747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.
: H! D: x2 y$ {, \) x- f2 \& P751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3
6 j' G0 \1 @. X; a757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit., l E X9 B w- P1 o" n; X2 n Q
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work
6 J+ Y/ Y9 t: j( G9 c& Q6 h& b760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result- T$ @( e4 j+ D) ?; e8 X1 x
761177 CIS OTHER Error Message - Memory exhausted
1 q; }& U! \5 D: h2 ]762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location.
5 Y5 a: N) G5 T6 @763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.
' [* M# h0 P8 A$ k8 D- o763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created." a; I1 h$ o2 z6 `" [8 u
763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager?- D h, K2 z, t& n, }
764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.34 B+ Q R0 k, T+ U6 B2 } Y2 u
764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle.) P# P( {* C3 a* L* _
764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad, H5 a4 `) ~/ f D' [( P8 |
764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3
" H" E) j) p0 P4 Z6 j0 U8 d765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro1 k3 b" F# D4 T; e! a
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question
' P" N/ _. ^, O! a& I: N. B765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape.
+ P0 Z: |! L/ _766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle( y' x& F# G. k* [8 e
766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design6 |! w7 ^+ T V2 H/ L: b
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3
! f# G8 Y! y# u J1 L% N. t766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit b* k0 ^: P! e) Q* o. X: C
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.
% B/ `; `& f) S% v767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.
( z5 T, J! v, t1 F6 r( w767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs.
3 B m) \5 p. E767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly
3 Y, \' y5 I% z Q! J768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy.. ]* e% K( h: ?. ?/ C% V
769150 CIS PART_MANAGER Update All part Status on a group changes 揇o Not Stuff? status to 揝tuffed? in V61.3_ISR_5. |
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发表于 2010-4-29 09:15
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