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改进如下：! b, k* T; x* _- A% X
J, j- ~) I( }) F/ j! e
HOTFIX VERSION: 015
+ O0 W; s0 B, p4 ]9 Y# m========================================================================================================
( y* N5 h2 ] t- `3 H9 x: I% S7 vCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 \& J9 p% b2 B F( Z9 @========================================================================================================; q( N' L* Z6 a9 a8 f8 b* |
264893 APD EDIT_SHAPE Shape Edit Boundary toggle invokes S pattern not flip
6 w. L1 V8 s$ }9 e609206 APD OTHER parallel command fails to run on mcm files
5 J! [5 [1 |* Y$ U/ v7 O8 ?7 D646375 PCB_LIBRARIAN CORE Saving a design or Export Physical takes a long time$ q8 z) z& A4 x$ u
650721 PSPICE DEHDL Pins shorted due to update in unnamed netnames
/ w% T! A& W, S7 S- J9 L" C665343 APD EDIT_ETCH Diff pair is routed with gap less then primary gap for a smal6 l. f8 w. o3 i/ m
666736 ALLEGRO_EDITOR ARTWORK There are some shapes not filled when RS274X garber is import
; v8 }" M7 N) f669411 CONSTRAINT_MGR CONCEPT_HDL DEHDL Constraint Manager crashes when SigXP is opened for a n+ Z1 |* u8 F' L3 x! ^" v# F
669769 PSPICE DEHDL Edit Model on page border causes crash1 v6 q$ E4 A+ ^% i% r% x
671583 ALLEGRO_EDITOR SCHEM_FTB PartLogic does not work with library level ptf files." g1 R$ @, D/ P5 F* U6 I, O
672656 CONCEPT_HDL CORE Using Select cut/paste commands crashes concepthdl
% t: K& Y! R" e( a672806 F2B PACKAGERXL Export physical fails if datasheet hyperlink is defined as ke
+ ^ D: D3 }6 m" r+ w& L' \! e$ k/ u672995 CONSTRAINT_MGR CONCEPT_HDL Changing target on net in RPD groups does not clear the pinpa
+ j0 u+ h9 K8 l676268 ALLEGRO_EDITOR EDIT_ETCH MIN/MAX heads up meter not working for some nets
" d, h1 ?7 D, A% c9 A* b: ]8 B677049 ALLEGRO_EDITOR SHAPE Wrong DRCs created on sliding Nets
3 r S% Y" P6 [. p0 H& r677123 ALLEGRO_EDITOR SHAPE Shape does not void cline in slide mode.
2 @1 M9 X. x; v: {" ~9 ]; \; `% [678030 SPECCTRA LICENSING Cannot start Allegro PCB Router with SIP525 license
& L7 T7 U. c* a# t! f# c678075 CONSTRAINT_MGR ANALYSIS Wrong buffer delays are used in switch/settle times in CM
6 T+ _! ?' b1 p678794 SCM PACKAGER Unable to package subdesign1 z6 j* u; E, V6 b. m
678851 SIG_INTEGRITY OTHER Difference in lengths in 16.01 and 16.2% F; T5 ~! K, l# w( d
678884 ALLEGRO_EDITOR DATABASE dbdoctor fixes corruption and then it's reintroduced
: y0 ?/ L9 I/ H! |- x679224 ALLEGRO_EDITOR DATABASE dbdoctor states it fixes an error but the error returns2 v, b- Q6 b7 B
679228 CONSTRAINT_MGR DATABASE Wire Length over Parent Die ADRC is not updated dynamically i( s; Q$ W: i4 W# u' K
679288 CONSTRAINT_MGR SCHEM_FTB ECSets on some of the nets are missing after importing the lo z* q# Q! N# X5 X4 \
679954 ALLEGRO_EDITOR DATABASE Unable to keep changes to the VIA list in constraint manager.
) j' p/ }" U8 h! @9 P679990 APD VIA_STRUCTURE In Via Structure > Replace after selecting the Old and New st, a+ u& Y/ t' N0 u8 o {6 _
681074 ALLEGRO_EDITOR SHAPE void is not correct with pin having multidri
t" p3 Z# @ o6 k. ?5 k681140 SIG_INTEGRITY TRANSLATOR Spc2spc crashes on attached testcase C, C1 Y" P) k: X4 r
681975 APD SKILL axlExtentDB and axlExtentLayout functions will return nil if
: Z* A( f, R0 i7 g. ~$ D682587 ALLEGRO_EDITOR OTHER Allegro moves all text when any text on symbol is out of exte
! D" Y, b0 M( L683479 ALLEGRO_EDITOR DRC_CONSTR Modifying design pad to multiple drill creates unexpacted P-L
6 r) @% \5 k5 q6 W- ?683515 APD DRC_CONSTRAINTS DRC is possibly bogus as it seems to be confusing layers |
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发表于 2009-7-27 21:04
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