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Electrical(电气规则)
& y& ]' h! v& C5 M& s9 A Clearance(安全间距规则) - G1 p3 `! E0 B* Y; F
short-circuit(短路规则) " U8 |' J; g' R
Unrouted Net(未布线网络规则) s2 M v% {& s" b" i2 ]. A
Unconnected Pin(未连线引脚规则)
* z# S1 j( l5 U) e; cRouting(走线规则) / V; v/ c* T& ]
Width(走线宽度规则) 4 S3 }( P( }' \/ z
Routing Topology(走线拓扑布局规则)
4 F' j9 X, k8 }. G9 B0 Z) C4 G Routing Priority(布线优先级规则)
4 B2 Z: ^4 h f2 _' ?. _ Routing Layers(板层布线规则) # W$ M: w( i6 @/ y$ p- Z
Routing Corners(导线转角规则)
0 _3 Z0 g7 N) I7 u2 Z$ x- o) W8 _ Routing Via Style(布线过孔形式规则)
1 k3 l9 u+ p# V& [! O. R1 D Fanout Control(布线扇出控制规则)
8 s. m& s8 q4 P) V1 H( TSMT(表贴焊盘规则)
- a M7 b% W8 G5 J1 j SMD To Corner(SMD焊盘与导线拐角处最小间距规则)
3 U/ Y: g. c' n7 E- \- n SMD To Plane(SMD焊盘与电源层过孔最小间距规则) * M7 p1 j7 u0 n3 R6 t$ K
SMD Neck-Down(SMD焊盘颈缩率规则) ! W. G( T3 j" R+ x6 R
Mask(阻焊层规则)
4 M/ Z& X# c3 \1 E9 Q3 l9 n. j' q Solder Mask Expansion(阻焊层收缩量规则)
6 ~; A1 T* |9 S: \ Paste Mask Expansion(助焊层收缩量规则)
; A' q, I# F- \1 UPlane(电源层规则) 6 K# H$ {: g- E( M
Power Plane Connect(电源层连接类型规则)
) o! {! W6 s2 v Power Plane Clearance(电源层安全间距规则) 1 A9 }6 D; Y6 Y1 }1 u' ~
Polygon Connect Style(焊盘与覆铜连接类型规则) 8 M3 `7 y6 ?: Z0 j% D) {$ S
Testpoint(测试点规则)
& j/ o4 P: e- I2 b2 E Testpoint Style(测试点样式规则) " k0 o/ F& O/ `! ?
Testpoint Usage(测试点使用规则)
2 c$ ^4 J3 l3 E' [& eManufacturing(电路板制作规则) / D, F1 Z& I+ P3 Y# K
Minimum Annular Ring(最小包环限制规则) 8 R. Y1 v b* g) Y5 a
Acute Angle Constraint(锐角限制规则)
2 b( g) H( j/ c: N' Z/ q Hole Size(孔径大小设计规则)
7 s/ X2 Z+ l/ G, ^2 m, M Q Layer Pairs(板层对设计规则)
) o0 r3 }+ L. X8 D jHighspeed(高频电路规则)
7 C9 A& O9 w/ b4 w; z! Y Parallel Segment(平行铜膜线段间距限制规则)
3 R" a; P1 r5 \' y# g Length(网络长度限制规则) + F( b2 H3 r- n- R* W# b# U! D
Matched Net Lengths(网络长度匹配规则) 0 b4 M# ]+ i" _8 q7 i7 N3 f8 q
Daisy Chain Stub Length (菊花状布线分支长度限制规则) 7 n; n5 U/ g& V9 j- L
Vias Under SMD(SMD焊盘下过孔限制规则)
8 b# ^( a. O, z* P+ o8 E Maximum Via Count(最大过孔数目限制规则) + {) ?+ }. P% D+ d9 }& x# n* b) l
Placement(元件布置规则) - v2 R% i5 Y# b* \8 o
Room Definition(元件集合定义规则) - ]4 F3 a, z; j) s
Component Clearance(元件间距限制规则)
2 E! z5 [& @& b w# d Component Orientations(元件布置方向规则) & j2 K6 ^; | r% @
Permitted Layers(允许元件布置板层规则)
+ j( K. _8 C2 A) ^ m2 C Nets To Ignore(网络忽略规则)
9 G: F8 b7 N3 `, I4 W Hight(高度规则) $ W' \3 [. D5 R9 z, a5 j4 M, F
Signal Integrity(信号完整性规则)
) G1 {) w, q6 z R% d Signal Stimulus(激励信号规则)
0 D! b! a& q4 a& z5 R p/ A2 ^ Overshoot-Failing Edge(负超调量限制规则) ! Y v* I' A( D' S
Overshoot-Rising Edge(正超调量限制规则)
! S2 \1 w# g, v+ W Undershoot-Falling Edge(负下冲超调量限制规则)
+ ~6 @5 p. l9 e. v9 Y Undershoot-Rising Edge(正下冲超调量限制规则)
* I V$ l: o5 ]3 N" H$ ] Impedance(阻抗限制规则) 0 k5 y; T2 q9 u1 a+ N2 t
Signal Top Value(高电平信号规则) ' n0 T* J' D( }8 A9 b% `' Z: \
Signal Base Value(低电平信号规则) - v0 e/ A+ }- m1 Y, W
Flight Time-Rising Edge(上升飞行时间规则)
7 x+ S/ X+ H3 u* l1 n Flight Time-Falling Edge(下降飞行时间规则) " r9 h$ P) G3 F
Slope-Rising Edge(上升沿时间规则)
( z9 k# T7 w/ Y% h6 V; a+ |" A Slope-Falling Edge(下降沿时间规则) " U: ~" ^9 e# P4 G' _; d, _ ?
Supply Nets(电源网络规则) ! k3 T9 h6 E: `. m( T7 h( h/ n
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