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Electrical(电气规则) 7 X$ q: r; W0 `+ p
Clearance(安全间距规则) 0 j$ |. H* O* |- |7 E# K+ D' N, A" G
short-circuit(短路规则)
1 ]+ U% [- z3 h+ P# b! ` Unrouted Net(未布线网络规则)
$ J _( b) q3 m6 \/ z% @& s Unconnected Pin(未连线引脚规则) ) U! F$ h* O2 b1 s. s% k, b. S
Routing(走线规则) 0 u. Y1 e, F" [9 j: ?3 O; q; T+ _2 J
Width(走线宽度规则) ( G6 ]1 I+ }7 s2 c0 ~/ ]6 s/ q4 f* D
Routing Topology(走线拓扑布局规则) 3 j4 A; k6 G; Z% L. @
Routing Priority(布线优先级规则) ' _" V) Z6 s$ S
Routing Layers(板层布线规则) " g( t( s6 `6 m T- I# J# v% k
Routing Corners(导线转角规则) $ y! C3 s, k' A7 H$ U* \: H6 S
Routing Via Style(布线过孔形式规则) - K! r3 I. ~ ?
Fanout Control(布线扇出控制规则)
# S# m% `) C0 N$ gSMT(表贴焊盘规则) ) `& G7 |& Y0 }) G
SMD To Corner(SMD焊盘与导线拐角处最小间距规则) $ a& h r" d# l6 J( Y' R
SMD To Plane(SMD焊盘与电源层过孔最小间距规则)
, r) l1 n& }+ q2 z! k0 l' U+ M3 k SMD Neck-Down(SMD焊盘颈缩率规则)
+ v' A4 y- k+ h; e* l1 D$ ]+ @1 iMask(阻焊层规则) ' g) z- T& j0 r. s: U- s- Q, v4 P
Solder Mask Expansion(阻焊层收缩量规则)
# F h v5 f# ?9 g; d8 k- Q# J Paste Mask Expansion(助焊层收缩量规则)
3 F& o7 n/ {( O6 B uPlane(电源层规则)
- {. N7 Y: e; v4 a Power Plane Connect(电源层连接类型规则) ; }9 t! t3 {" U
Power Plane Clearance(电源层安全间距规则) * N/ x R" T0 n" _4 c% z
Polygon Connect Style(焊盘与覆铜连接类型规则) . k' A" t+ W2 t7 c/ c
Testpoint(测试点规则)
" a. m" D/ B1 q: J) H5 g: U4 |7 j Testpoint Style(测试点样式规则) ' J; [0 W0 j# |5 U9 S7 o) d
Testpoint Usage(测试点使用规则) # X/ J- a, H- H7 A, W" t
Manufacturing(电路板制作规则) 5 P" i0 f) f, ]( Y/ I) X8 v; S+ }' Y% X
Minimum Annular Ring(最小包环限制规则) " O/ x H ]( g! W
Acute Angle Constraint(锐角限制规则) * W3 t+ T1 a7 { b
Hole Size(孔径大小设计规则)
( U$ t, v* G5 p1 o7 S1 u# s6 @ Layer Pairs(板层对设计规则)
: \9 K0 S% h) f7 d1 P/ mHighspeed(高频电路规则) 9 X5 u0 T. ?4 X8 @- X3 L
Parallel Segment(平行铜膜线段间距限制规则) + V6 [7 U- f& h
Length(网络长度限制规则) 0 h" {# A" H. B2 q4 N" J
Matched Net Lengths(网络长度匹配规则) ; F% i, ~, G) j' K) t
Daisy Chain Stub Length (菊花状布线分支长度限制规则)
2 ~' v1 ?2 o4 {& z! @& ?6 M Vias Under SMD(SMD焊盘下过孔限制规则)
! y7 Y: x7 j3 C0 b/ A+ D Maximum Via Count(最大过孔数目限制规则)
" v. K9 p, c" x% K' m# {# W9 SPlacement(元件布置规则)
0 }$ E) Y# V0 y$ [: p6 m Room Definition(元件集合定义规则)
# C4 y" r/ G6 b, z Component Clearance(元件间距限制规则)
5 n/ A$ w" V- U C# I, J+ k1 i# d Component Orientations(元件布置方向规则)
& ^) H" f/ \/ _6 q. p- N+ S+ c Permitted Layers(允许元件布置板层规则)! g. |* \. n/ R! g- y2 O$ o& v' N. v
Nets To Ignore(网络忽略规则)
1 w5 k4 e5 Q+ a( o6 p! [/ f5 E* d Hight(高度规则) . d$ G$ J9 x# E7 S0 [ g& `# R
Signal Integrity(信号完整性规则)
6 \; y! {$ x6 ]- t" f Signal Stimulus(激励信号规则) # M! S5 w$ {4 O- W* v
Overshoot-Failing Edge(负超调量限制规则) t$ K* P9 K# L! p, }& N) M0 q
Overshoot-Rising Edge(正超调量限制规则)
+ G; x h1 @8 n& v# U Undershoot-Falling Edge(负下冲超调量限制规则)
! l, A% y$ f6 O* ^. p Undershoot-Rising Edge(正下冲超调量限制规则)
3 ^/ u# G) w8 E& X/ V Impedance(阻抗限制规则)
2 @' J/ p5 M# J3 q# M Signal Top Value(高电平信号规则)
. H2 f0 q( z" u Signal Base Value(低电平信号规则)
4 z- ~. Q6 k% K& m) [- h Flight Time-Rising Edge(上升飞行时间规则) ( e; o' O8 A. D, V
Flight Time-Falling Edge(下降飞行时间规则) ! @6 w4 |: P( }8 i5 b1 ]3 l
Slope-Rising Edge(上升沿时间规则) 8 A) S3 \3 }8 X9 l8 \
Slope-Falling Edge(下降沿时间规则)
6 c1 e0 {) k" }2 q3 p2 l Supply Nets(电源网络规则)
F1 G$ n# m1 d2 G4 M5 Q/ o9 Y& _9 w; y0 V- T7 s* Q
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