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" r+ z/ V" N: ~8 W; o6 I6 cDATE: 08-14-2016 HOTFIX VERSION: 0049 c* _+ m: F5 Z" r0 j
===================================================================================================================================
, P& l7 X0 q- iCCRID PRODUCT PRODUCTLEVEL2 TITLE
1 ~- Q: M. I$ u! E% V8 F1 r===================================================================================================================================2 s. @0 K. Q" T5 C$ a
908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
7 p: A; L) D& u2 W1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)
3 P) `' H/ r" C1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE
5 P' l. p0 |2 @8 U& i* d1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
; A0 |" k. h# L7 H1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets
: n/ W: R+ m5 E+ R# \1326716 ADW DOCUMENTATION Dataexchange documentation correction needed
9 }" \* o0 f4 f- G: `1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large5 c9 {% ~1 T# `; n# l( j& L$ F
1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.
! x% A+ x& h2 B- t0 ]: r1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
9 A, i- J& n; l1 s1410485 CAPTURE SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design- ]; H6 r2 r# A3 ^+ g
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
3 W$ ^8 K+ S% L/ J/ R& D { U1413287 ADW LIBIMPORT Library Import uppercases all Attributes when reading CSV
& S0 {- d, l5 N2 Y1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
, y+ H/ i3 ?' j# \4 Y) Z1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
% _' X- }0 ?/ z& j. o1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room0 k) y1 |5 l2 [3 Z
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option: {5 t9 f/ g. c
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the sym1 view are not saved9 q$ U4 U1 V5 @! i4 s# Y4 z
1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked4 N) ]5 O8 b7 @& b& n1 C" X
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
& k5 l: g, z: J( p* C# Z9 i8 A$ ]1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required' K: S3 g( [# H0 E# m. D
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set8 t1 K* n* y2 N1 A; Q3 _7 `: ^
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
8 e2 |4 _' i% D3 |8 r- @1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties+ d/ }% h$ L k0 J0 o) ], f; S: u/ J
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM9 |+ `4 {+ u! }8 P9 i! X
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
7 I& ?0 T' Z5 p, ?6 u1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
% O* E$ Y0 |: e( Z' g/ h: \+ g( u1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
6 |; t N8 v {$ w1471287 CONCEPT_HDL CONSTRAINT_MGR Importing pages from other designs with different units should inherit the source constraint units
$ v, a( h, r- n% L1 A! }1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
, i5 ], ~5 H' _2 Z% C" e# O8 M; {4 E1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region2 ]( x( D$ c8 V2 |- C$ n) @
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB 054 / ADW 47
; V) W* @' v2 S _" V- V1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design
. {6 S: ^( X/ V1 i1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
/ b' g( j- ]' X* A b/ o( K5 q* @2 [1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian5 i: X8 j \3 @0 B0 O1 S
1474066 ADW DBEDITOR Bulk edit performance lags when parts included have large number of properties
8 s$ }) [, u v' A T1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
1 G% N: b4 V$ s, b1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.& Y0 s q7 Y9 J# a+ @; A
1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_', _$ m5 X- R+ G
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown5 i8 O! v9 _" v* G8 O' W0 f
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
& R7 w! Y1 y. S* V# E1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
# F# Y9 }8 M- f- W' g1 u1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
9 ?9 b( G" r8 m- S) n: `1 n1478200 GRE IFP_INTERACTIVE Allegro give error "Low On Availlable Menory" and then crash
, p; i+ C8 x1 @6 B1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys
9 ] L+ S. c; K" W0 T& i ~ [1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy
: Y0 Q+ C# V8 k1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon
9 I0 b# v6 `0 x# [. W: a! @- x% W1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
0 B+ b5 D, y; T G6 v9 [1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
4 T/ z+ t! J. Q# e7 c1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053
8 P1 ^. Q" G4 w+ q; k) K1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO
" y7 Z" ?5 V/ z; i/ I2 @1480005 ADW DBEDITOR DBEditor/DBAdmin GUI do not allow the same characters in Property as LibImport CSV Files' t! y/ `0 V: C4 X
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'
0 _* B6 }$ O/ ?6 V" Q* K( p1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition3 N. u* G! W X& v2 G6 d
1482544 ADW DBADMIN Hierarchical PPL not functioning correctly
+ ~. T/ n) @' q1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode& s: ^9 j3 l7 U% ~/ h, \
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles
" T, t" b+ f; B, Q7 v4 a4 ?5 a1484100 SIP_LAYOUT INTERACTIVE Tool crashes when copying and rotating a symbol
. `, r! [1 c3 {( \& @9 n1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues4 A9 }0 }7 v: A
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
9 h1 K! ~- ^2 a% o; L/ i1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
/ {5 M5 G: g( z8 `1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project! r( f* |" }# ? o
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.* \' I) V. m4 d7 @) x
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager.
( z8 _6 R* T, a' N5 K t- Z1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
- S- j3 Y/ Y9 Q3 x5 v& N3 X1487125 ADW COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated9 a; b0 J0 a5 ^$ B% s: A
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior" W0 V8 I6 C, }0 E- N
1487496 ADW DATAEXCHANGE DX Changes checkout ownership when override action is set to remove existing relationships, e- h$ u+ O) h' [( Y
1487656 ADW LIBIMPORT PreAnalyze reporting false warnings: j( S0 N6 G/ J5 [ h Q
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board h# @* k4 ^. u4 o3 S
1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
$ T9 N& W) X% b' @3 D; P1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
6 F% i% D6 `" u4 I1490299 SCM OTHER ASA does not update revision properly: T! m C; I; s: I; r
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer5 g0 }" n1 w4 N+ r' i) u
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
" X- Q0 Z: V# K& @/ j7 a6 T, [1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
9 Z2 T0 _7 Z, X/ C/ f) v0 y1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)! B# G5 ^, v; w* i" w: J
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
/ z, u6 R" q- \1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
/ x5 z# I8 e* G; p% M1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash0 o1 n1 S- ~' \1 W2 U& E9 e
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
6 M! @( A U) Z1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
0 e U4 k, {/ u0 n" F4 H1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size' B4 m) J; z# I
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root% {# n' O: B. j1 O
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file# ]8 s: f' s, Q3 j0 Y3 T
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
, @/ s- J) [# A9 @1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch5 G; g6 ~$ O- o1 Q$ Z2 h1 s6 W
1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts) p% s3 [' h4 K1 w
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
0 J2 p& J! S5 z7 p) S1 V% S1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out0 \5 r5 w- g4 W
1501294 ADW COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration
9 g2 a; u3 D2 _/ ^1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL2 S; q; W; J2 i+ |5 i& |
1502282 ADW CONF What does Message: 3 > 2 means?* K( Z6 \3 ]/ v: w/ R
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
* N. b; i: @, _# g1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized7 i* U" S3 ?0 X
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
0 |: N/ Q! I: e* }* Z5 x1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
; q2 { x& Y" ^, y. e! ~# m. @1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
+ b3 V p% g- M% z2 B1507497 ADW COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol5 M: G% b; q% G. _
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
r! Z! c, Q- e* v5 G) }1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain6 ?3 f+ z7 j) m: P: l. y- p
1510570 ADW DATABASE ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa; D# z9 Y7 v; b" `
1511180 ADW DBEDITOR The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri1 ?2 l3 E7 |( Y1 x" @3 h
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6: F' p' Q2 f. }2 g/ _# s
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance. ~+ A4 t' U5 r0 c) c7 H
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.+ Q7 }8 ^0 s, i
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
) h% q4 X( I* T5 k/ |, @3 r! }1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
7 p& w9 b( d' ?/ R Z z$ e0 m1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib/ Q- R2 d3 E6 q2 d- ^- K. a
1513737 ADW CONF DesignerServer from a different network domain does not show distribution data5 P$ \! A: L8 B! c8 Y5 F+ f
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property0 n" b/ c: d0 Q+ N; P
1514942 SIP_LAYOUT CROSS_SECTION Why is AIR not permitted in stackup in 17.0?9 z2 @) z+ L0 I/ H+ ~; F3 Q) R3 }) z
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly7 b( Y7 @- h- ~. \
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol& P- I9 D: m/ ~: J/ u% |0 m
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
: O! S2 m5 w8 |7 K! e/ {1 ?1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'7 I4 A1 L4 [$ ~' u& K* y
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes2 R4 B: o8 y* o* e5 `
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.2 b' Y/ Q3 D4 ]! ?* |) E
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
( H6 y: k% V$ @) a1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
% B F! P' s" a+ L, _" m& m9 p, L1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
3 m) G! ~. _; @& D f% b, g1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net4 m% E/ S& Q/ t' P
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist: i6 [$ e4 z, y2 u& |+ P9 g7 H
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports- ~& h3 o r, K% I3 n
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
' `9 m) |% b! F) l( ^/ C" j1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor' b1 \ A5 u+ _6 y# G
1521871 CONSTRAINT_MGR CONCEPT_HDL CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning
! q2 d' Q( d( j& y) g q1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.$ ?: ~0 D# {! p
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design0 S0 W' u }5 b
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash
- R" @2 A8 P' A. s @1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated) p+ m" D7 U; t$ j$ a# W3 _. [6 m
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine. g1 f% ~; x4 h% {2 G x
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor
+ P k6 l, o/ X1525883 ADW DATABASE invoking libimport on an existing DB should verify that the libimp_su variable is set correctly
# y! Q3 ^2 N* R8 Y! o- l5 A1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
$ s8 F! O6 ^* w% E1526914 ADW LIBIMPORT Can not import to new library DB
3 V( P8 j! T& n0 c( n1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 639 X6 \7 R1 o2 a5 c3 Q! \
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'1 F; m' F$ F( r; R1 x! o8 Y& {
1528235 ADW DBEDITOR About the rule "Validate Classification Property and Property Values" of Release/Pre-Release
- N1 Q H7 ]4 O8 w6 G( ?1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
6 f! P) t, X- W! s: n7 t' d. q! n1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property, z( V" U" p+ R5 J5 ^
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design4 {7 e: G" G% l
1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents Part's release
- F' O7 s% R; k' T4 y" c" D1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
8 e Y+ ]* Z, g5 z8 D- ?- N6 W1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
3 O7 l V5 y, ^, o1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file6 r; q! u& u$ j) m
1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used
( J$ H3 Y8 v$ i! @1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes& { F1 ]/ Y( K, E
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
% u6 {' @) G. B8 [" a1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
9 c. b9 j# Y. h5 t8 f s# {1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists5 i4 \( W3 G; R7 w4 C' W
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue% k# q* y! l5 D) |, [
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
3 F* |& j4 n) d9 g2 n+ g2 |1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
! S! U+ C( W* I" I' \( d9 U# d2 F1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform7 }: p8 D! C3 B+ o9 i% I# y! ] C
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'# o& l+ t8 g3 b+ }
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
& R9 U) o5 b6 A0 B2 U1 e5 J) p1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run% w# g2 L4 t! Q" v
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error+ U, @5 b; _9 o0 L
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
: X4 O' X: ?* O" N) `1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
" B8 b- Y! Q- I0 W5 E1542949 ASDA EXPORT_PCB Export to PCB Layout Fails to Accept Entered Output Layout File Name) `0 m5 A4 U( S" Y
1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer: S: J7 k' J; O" X
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
* ~. E# l6 @* f3 s3 i1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash3 z4 ~ U3 C2 L& R- B+ h: C
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked1 e5 C% \. a. x& e
1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.5 P$ w) V6 ]1 f3 _
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
9 x/ p3 t0 u8 L" x3 J1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information8 r# s/ n) N; U U: k6 F& M
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
" y/ g! F9 K0 i8 x6 S( ` R1549658 ADW TDA Unmapped network folder in TDA4 h- Q+ x) _0 d9 N9 O
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols5 v% u* I+ `- S7 _( C
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects
/ S, z0 T# q+ A( U1553027 ALLEGRO_EDITOR UI_GENERAL Beta - Allegro display freezing very frequently - canvas not resposive and turns white.
" _; h5 N1 H0 c, s4 V* ?; C6 u7 i1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.1 e# ]! ^& t, I6 k: g# O1 M. H
1555254 ADW DBEDITOR Loose focus on Free Text search Window removes the text.
& E6 N y5 i2 s t7 m4 d1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
! a: M) u+ S& p( Z1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export
% E P% }% C" w3 W1580571 ADW DBEDITOR xml files for released FP and padstacks are left in flatlib area.3 C( f# ^9 V' `8 e( g5 s. G+ w* R
1580580 ADW LIBDISTRIBUTION list files are not getting cleaned up for custom models if they are purged.
3 M+ V0 f( f& g2 o( G) }: n2 l. ?1582064 ALLEGRO_EDITOR UI_GENERAL User defined menus not working in 17.2
4 f/ f. ~6 V5 P7 k& U1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes7 V. |9 t: V9 s9 O( N
1582856 PSPICE MODELEDITOR Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created/ L, T, t( \, y% a
1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
6 |; I5 B5 Z9 n1 g4 w1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file
* P# A. d ~! v% h1 T1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option( l2 U+ p+ Q- w! z: @3 b
1588736 PSPICE MODELEDITOR Model Import wizard says "Invalid configuration" when lib opened in Modeled R" ]: S5 U+ |5 T7 B+ _8 b5 Q
1588742 PSPICE PROBE Browse icon is missing from Pspice File > Export > text( Q7 P1 O; ^! L0 p$ g& r u& j, d
1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened
4 m) Z; }. ]9 x+ p1 r G1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons
0 F* {5 }) N3 u! h$ L1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork
% k9 J' k6 I( H- p" S1592089 PSPICE MODELEDITOR Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator
; Z2 [0 q' n. K3 L+ N7 Y1593436 ADW DBEDITOR new Model type form does not focus cursor in window, User must select the Model Name before any text shows up0 p/ w/ d8 G+ m$ i2 d. c& G0 p7 _: g
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
! O }; ]8 [8 G4 x* Q$ Z1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode
0 ^5 m3 d m7 V; T$ ?8 M1596162 ASDA IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well2 i5 _) {# x7 b: H" W0 A" o$ b4 F& J
1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names
& A. ] u4 V4 ?% Y1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas4 s9 K. w6 K1 S
1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated1 O% k/ ~2 ?0 ^. Y
1600194 ALLEGRO_EDITOR DRC_CONSTR Update drc command changes the amount of DRC count when using 8 threads! Y- t! x1 M5 F
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating
8 z( |0 T; F- `# d1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
2 d2 y* g2 A9 e% m1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.$ D9 y5 t, l# ?9 l8 S% h2 S
1603377 PSPICE ENVIRONMENT At Markers Only option does not generate .dat file
. y7 [6 C" i7 T7 ?1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header
& L; o' D, K! ~) [ c, P j. n1604741 ASDA CANVAS_EDIT tcl console changes the present working directory (pwd) when you open the proj preferences & close it.
7 e3 b9 N' ?7 g' h2 @1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard
) M/ w( p) W g n% m+ V1606861 CONCEPT_HDL CORE Crash on Linux during Generate View
1 S: I3 b3 M3 X( V q1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset+ T* I" _/ b& U: `
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
0 [( `* P( b# v- H# d1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set& |4 a; K) S) _0 K7 k
1607568 ALLEGRO_EDITOR NC Allegro shows wrong drill legend Top to Top drill.# D& t! s2 v% R- N8 |8 O
1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath skill command in SPB 17.2
3 [/ o0 u: d ~$ [) O7 s* J1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.
# D7 \" Y4 d/ i2 `6 w. X1609400 ASDA CANVAS_EDIT RMB > Assign Differential Pair should be grayed out when a single net is selected) M' ]# z4 b% |6 Y/ v7 u5 ?6 q; f
1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux
/ D4 L/ a3 Q0 r% d C' p1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.5 `9 r7 s# h5 x; I$ y
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only6 k) ~, I3 ~, f. ]. f
1611226 ALLEGRO_EDITOR SYMBOL Allegro shows crash message while saving flash symbol.6 |# o+ v4 V0 w- B! T
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.
9 P2 M0 C: Z6 c1613123 ALLEGRO_EDITOR SKILL drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT! ^# R+ a8 o4 w7 `6 b
1614000 ADW LIBDISTRIBUTION lib_dist does not complete and does not allow to delete the .lck file.: {" ]' b7 S B5 r. H
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp4 M8 P- i# {0 ?7 A* d
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error
; Q$ \: O" f# j( o1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import doesn't map layers correctly6 H2 T$ E5 z7 b: d) M
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update1 M! [% z2 }6 p: E
1616733 ALLEGRO_EDITOR INTERFACES Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated
8 b* Y3 f6 {" t8 ]# ^3 a9 ^1618751 ASDA DRC SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file.
9 j0 C" _4 _, I% d" v3 }' C1618797 ADW FLOW_MGR Flowmgr fails to execute command
( q' `5 x, S1 W7 ]+ a1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.
. K' e; ]. Z( U2 C6 B% g2 a8 H! w1620350 ASDA EDIT_OPERATIONS Uupdating version for a connector pin looses the pin number
* E8 R A* M7 \( ^0 ?! @1 S1621963 ASDA SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol.
6 O+ G9 k, c/ ]8 h, A) _- Z1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet crashes the tool9 S0 _! \( {* g& k7 O4 `% n
1625209 ASDA IMPORT_PCB File Import from Allegro shows board differences) C+ m* r; `; X" H: [& K* h* N
DATE: 07-28-2016 HOTFIX VERSION: 003
5 v. B8 |8 @: i: {; F! l1 P! p===================================================================================================================================+ I! c0 M1 u' I
CCRID PRODUCT PRODUCTLEVEL2 TITLE" [: S; [( @, Q# T* N
===================================================================================================================================2 {. A9 H( X6 j' f
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
; |* z# \1 d6 Q" r1461626 CONCEPT_HDL CREFER CREFER shown to each instance of block pin though net changes
' G( L: M, D) P1 U$ T3 z1472456 CONCEPT_HDL CORE XCON and design are out of sync
- L# L& G& D" b8 h* ?3 b$ u& f ~1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
9 q. \$ Z. p' x1 _$ S( K/ t% Z# j1 c1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
4 E3 J; ~& D* I4 n4 ~8 u1560102 ADW FLOW_MGR 172BETA: eval in command string does not work
+ {8 l6 v/ w5 ] j1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View
8 H* f- P1 ^7 E; X1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
6 E+ I2 H) [' V% G1578876 ADW ADWSERVER Component Browser crashes when trying to show details on a part number
7 a2 N. k0 @/ H5 E2 y$ q1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
7 b1 `3 c9 A( o7 _8 J4 |1582863 CONCEPT_HDL CORE Generate View creates non existent ports' l0 O( s; M% P+ G
1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window.
6 j3 P, W# i# T/ \. H1 u1587018 ADW FLOW_MGR Project Update at Ericsson in ADW 17.2 asks to specify flow name.
3 a4 Y) p1 C, `: L1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties' k+ G# L, I: O; h
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed# l5 B' ?/ \* H! j- U9 `
1587718 ADW LIBIMPORT Library Import Pre-analyze report is not being written
$ g- X' X" h7 B8 l4 {6 c1588197 ALLEGRO_EDITOR INTERFACES STEP output fails when External copper selected on Win10-17.2
& v6 y. S4 K, e) O1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"$ k: v* t% U6 Y: ?
1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component0 K c: g. R G. \1 n- m$ ]
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC between Embedded pin and via which do not share layers5 |! H0 k$ H3 V" A2 O) w
1589979 ADW FLOW_MGR Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project
7 ^ o8 j# f2 E% F/ p" m" y8 |3 N3 v1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior
9 n. j+ @3 Y' [5 ^" p; S1590639 CONCEPT_HDL OTHER DEHDL crash when importing design
5 F4 M7 x( c6 r# o0 r) a1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM* k; s R+ a% J# S' Q% F% ~( a
1590720 ALLEGRO_EDITOR INTERFACES Text Size Parameter file does load names into the text table
/ l9 M" W4 p$ W; u9 i1591070 PSPICE PROBE PSpice crash while evaluating measurement from trace>measurements
6 V9 y5 O% I$ S6 I1 x1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic9 M; ?; `: l2 W$ s% N# R
1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived1 z& |% K/ m9 q5 b2 N+ ?; Z7 R
1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crash in 17.2
' l2 p+ C% Z4 D T1596615 ADW DBEDITOR Component Browser didnt come up to search parts, also the database editor didnt return search results
) I. Y- J3 }/ ^* h1 _6 _6 a1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
; O, s5 N0 j/ _( `- P1 B8 C- ]1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor1 n i6 [$ D4 ~3 A6 ?. p
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI0 `) V# B) A4 J* J% m; v3 N: [
1598629 F2B PACKAGERXL Export Physical crashes `% X+ f" H7 N: V
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
5 e( `$ k3 Y' c/ {" w- [5 {/ }& x7 B1599744 ADW FLOW_MGR Few flow manager buttons are not working in EDM 17.2
6 b! J/ \# C( N) \8 g+ I1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
. b( ]8 V% m- f1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group, ]! a; q% z$ J# X8 l4 w6 u5 V
1600618 ALLEGRO_EDITOR DRC_CONSTR case sensitive issue with Physical Constraint Set; \5 D4 I _: c: u. L
1600914 ALLEGRO_EDITOR INTERFACES File > Export > PDF shows the shape as unfilled.
( e! K6 ~1 T; C4 A- [. X2 W/ O1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad2 M2 z l8 }* W4 q1 Z
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol; ?) J5 F8 p/ Y; L# x
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name." D) b$ f7 ~3 H9 `; Q. H( `! X$ _
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
0 @( y. D# i1 |1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command. R" T* A1 A D
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
5 w& V1 w' x6 ?, x# s* N2 ?5 n1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error3 j( [, V% q: {0 Z
1604746 ALLEGRO_EDITOR OTHER In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools.9 q( g5 |; U5 m. M' v
1605322 ALLEGRO_EDITOR TECHFILE Cadence SPB17.2 Issue - Long duration in Tech File generation
( P# J2 B- i! b; ~DATE: 06-31-2016 HOTFIX VERSION: 002+ W1 y J0 V" ~1 w
===================================================================================================================================
2 ]9 M/ V' G3 w" y2 i' LCCRID PRODUCT PRODUCTLEVEL2 TITLE/ h) M- O/ O1 h3 j+ t$ v1 } {
===================================================================================================================================
; j! [1 P, `7 d) Q+ K: {+ Y, b9 T6 h) `, A4 K1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets2 o: v7 o7 T6 n6 U+ L( Y4 R+ C
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package# X4 A: ^8 R7 I) h
1481802 ORBITIO ALLEGRO_SIP_IF import of oio to an existing sip offsets the results incorrectly7 K7 a' ?. n2 ^! j: C8 C( D
1518957 APD SHAPE Shape void result incorrect: n# ]' B" o+ N& }2 S
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
F6 Q0 E# u. f, r1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly) G5 L w/ {/ v. O4 l/ N
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
2 W3 k8 E& b4 D: ]8 W6 [1 Q K1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.& O3 C$ M0 O8 j6 p/ x
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)5 G( J( I& ?& V5 U/ A
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
% ^( h, d* t& A7 T1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
" {9 D& u7 Z+ ]1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library4 E! ]- W5 T8 }- Q* t( C5 I A
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
1 a4 m |5 H" b* A. C# Q1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets7 C6 T0 o$ T4 }4 F5 X. Q& N M+ n4 X- W
1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation0 |: G0 @* D1 x
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
& O; z. t% h& B1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
' f' L4 _/ Y4 z. d; [. g# x* D( `1561501 ORBITIO OTHER oio -> SiP refresh seems to hang# s* L! H8 ?$ r5 b4 I% e" ?
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
( E! X! r" b. q5 q1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins3 c5 s: b* v' R& A
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
2 t, l. W7 h0 A0 L( z3 X, j1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions
3 s$ h0 x' } V- t% D1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete( Q5 O/ n* G( [$ O
1566942 ASDA MISCELLANEOUS SDA172: A lot of files in /tmp/ on Linux
4 f/ A* v$ I+ M! I0 i9 ~: s1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
$ J6 p+ p- L: J' O7 L4 _1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
& K. N6 f, J/ x$ O9 F% D1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window. ~: o& [ D6 U! s d7 n
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
) Z% t _8 G5 t0 G {! D! Y1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed- ^/ m1 F a; C
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2. B2 c# Q( y) n( M( T7 t
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...* R; d$ A* M* z
1570398 SIP_LAYOUT DATABASE Diestack layers can't be deleted if there are unplaced symbols in the design
( i! D# F: V' @; M+ G3 j1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager$ q! S' H8 K4 h" a
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
2 v: m% [# }6 _% j, h8 L# n& X) a1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property
& n9 P8 m1 h7 t! S1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
/ P/ Y! x- b8 Q8 y b/ C4 q1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display2 I3 ]9 v' p7 G1 D+ t! ]
1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry
! Y9 I" J; H! u& |% \+ {1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
! S, i6 |7 t7 |0 ]1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2
8 S8 T2 Q& F& ^7 p+ A$ P* A1573755 ALLEGRO_EDITOR CROSS_SECTION Switching between plane and conductor changes material in Cross Section.& p. C/ [9 C3 M( j
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
4 ]& B- b3 h b" s( J! x1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
" Z+ t( m7 O+ g' v& D U1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'/ p0 h- v8 E; U# x
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure8 c# a4 i( a u8 ^2 n
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files& Y7 M, ^. Y9 T, V
1580891 SCM REPORTS Dsreportgen crashes on different scenarios/ \2 n* w" c7 r% R7 H1 B
1581254 SIP_LAYOUT CROSS_SECTION "Apply" or "Ok" crashes XSection9 l: @0 | T; w+ C; Q q( Y
1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error' V9 N! E9 j0 l4 K" R6 _
1588823 ADW FLOW_MGR UNC paths have stopped working in Flowmanager in 17.26 j! h9 S4 r8 m" |9 F$ @/ p
1590064 ADW LRM EDM 17.2 gives LRM unnecessarily.; S; c2 G. k+ q8 Q
DATE: 05-06-2016 HOTFIX VERSION: 001
6 ^! }" L, r! }=================================================================================================================================== k. e# [/ Y; L( S6 z, h$ X
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( P+ F/ z, B! |===================================================================================================================================% \( A o" R& V3 h" u- f
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output' i* z2 [; { J5 {( V5 ^
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
. g+ E( J4 S, {$ X, _1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
3 K: ]: ~. H# D! ]' l9 S1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
' L* i/ i! u, Q! E9 W1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
- f5 J& A- ^, M* c& t2 X1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
" [! y; G6 J. `& {( W+ W1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing B. X: @6 S& w" r: s
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
) P3 ^6 Q$ ~8 p M1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute0 }8 K& D( D; G9 h
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals& P& V1 m' i) [2 l( B
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes7 d* v1 B( a5 o. }
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork( r( Y' }& y, n0 x
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
8 H9 e) ?5 |" {1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.* Z% C3 }5 X3 ]0 D. f
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder, f/ N: ~ P4 H7 p7 n$ c
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
( g- V! @$ }1 \( B* h4 v9 j9 f1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work; A% J( I; e" G$ O
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
) _, l/ _5 A4 Y5 \* l$ x0 y6 c1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
/ U1 B' M' t+ K7 f" C0 a1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license1 }$ Y) C! e- X( q! W0 c$ [9 l1 H7 k1 \
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork, C" w; q& j6 L8 Q" w& j
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message$ e2 k8 ~% z1 w$ x
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system2 M1 Y2 e1 o3 s2 }* f
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.1 d+ C" `# f& ^2 K& U$ P
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
- n" w- n2 S% q) n* L- H1 j Q1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
. [9 m% c9 P1 d4 t* E% v' F" d1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report
: `* I0 y0 p$ R6 n( X1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines
' _3 @5 [3 U4 }- n# }1549662 ALLEGRO_EDITOR OTHER Import Parameters Path' fails if parampath does not have the current directory ('.') set
. f2 K, R# e1 G1 K$ I0 C# \8 r1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
1 G! Q: y4 x! F& y, a/ p: p1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
' J" l0 a+ _2 d6 H- f+ w! a) S1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to hole drc between Via and pin5 R, r, o" a/ G7 X& V3 }
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
" m7 w# Y5 D5 H; z6 C: @1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
4 u; w& W2 z1 j* E: k: I1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons" @1 Z, x) e" X
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
. e3 g( u( O/ }" j# R% b, a1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
" j2 o3 c& q$ c- s1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die
: ]3 l! t$ P v- U+ _1 Q7 |4 m8 ^1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM
5 C3 y1 Q) x, y. u" P7 k1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux3 k& k" \. N: h% P; f; c: E; c
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error6 K# Y( ^& x5 ]# e; Z3 |- n* e
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.3 O9 N9 k2 P/ T8 v8 F% ^4 R( Q
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发表于 2016-9-7 01:03
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