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' V4 e8 U& M* d5 N3 i% \DATE: 08-14-2016 HOTFIX VERSION: 004* U k: t1 {. X
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CCRID PRODUCT PRODUCTLEVEL2 TITLE! z" p4 j8 Z, E" g
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908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked
% `) @ ], K+ t: V7 `7 S& A. J1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)
' O7 m. U) e, A' w1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE
+ C5 B" k* o, ~! T2 K& E7 i1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
* B+ ]9 s; y* I0 H9 a. B1 ^1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets
, i7 S# {, b2 b1 a" l1326716 ADW DOCUMENTATION Dataexchange documentation correction needed4 ^% d S& G/ z" m1 p$ j
1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large2 R9 a4 ^5 Z# F. Z5 i& _% h
1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.2 s" o, E* U' h; G: I
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
- c( |/ T/ t' ^4 u% _1410485 CAPTURE SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design4 t/ d# h" ?! i/ q
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only
% }8 L8 u# f+ }% [+ g1413287 ADW LIBIMPORT Library Import uppercases all Attributes when reading CSV
7 x7 }3 d7 a* y, _- l% ^2 ?1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle7 W9 W c" b1 i" H& V' b
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins9 i2 g" e. D8 M
1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room7 Y3 k8 f. m* B$ x& P W
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option8 x% [/ d; l: A
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the sym1 view are not saved
5 b" H1 ]" X$ }& |. v9 @' s$ ^7 q1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked
3 c& ~0 S+ h: T( n1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
+ c* U' L; \3 {. G, s) a1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required
9 m0 A! \, V7 a/ x0 R, a; ?1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set6 r8 ^7 ]* [% O1 i' s
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
1 \* x: ]. N) M6 b3 ^' ]8 [; U1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties
" J% l* _! q! j; Q1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM* c ^" ?# ?2 K& A* Z6 z9 S
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
. C$ O7 S0 w' I; ~7 ~+ |3 M1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename& h) ^+ o. F- B% ~) w/ H& Z
1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
9 o- l' q5 r5 X2 T4 b3 I1471287 CONCEPT_HDL CONSTRAINT_MGR Importing pages from other designs with different units should inherit the source constraint units
8 q7 \/ p7 f1 q1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack
1 S2 {9 s; k) v: E) x5 K' V3 Q9 W* z1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region2 h/ @5 P6 A3 c F: X9 I) F
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB 054 / ADW 47/ t' p1 w' y. p" ]/ ^$ g1 ?
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design
! ~, X' B1 B# b) S1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
: z9 W# E/ Z V& H1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian6 g6 ?1 a z& `3 O/ s( p% }8 m
1474066 ADW DBEDITOR Bulk edit performance lags when parts included have large number of properties
: ]' j' d3 R( s1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked
/ Y3 f$ D; H3 i2 A1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.% D7 I# w3 z- N: _8 i
1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'" t7 ` B" y# x3 T2 ~! v% D
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown
+ J2 S5 E! N5 m- A1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.
( i$ _4 @- g/ [1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups3 r! q' a5 L3 m! ?
1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
) N) q% H6 ~5 b, c9 e) X! m1478200 GRE IFP_INTERACTIVE Allegro give error "Low On Availlable Menory" and then crash- u5 r- U3 W$ |8 Q
1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys( }4 w3 S3 H+ |+ j6 l: W
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy/ \) u& Z. f+ \4 h( f0 ?' l3 t/ U
1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon
) D: z- @. u3 g% N! g* r1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
' ~# s2 _: X* \& ^. k2 k$ o d6 P4 [8 Z1 f1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
( K' T0 J( s* k+ `) l1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053
2 i+ S3 G+ H& f8 W9 s, E1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO+ H# G( n$ v; }: G3 X
1480005 ADW DBEDITOR DBEditor/DBAdmin GUI do not allow the same characters in Property as LibImport CSV Files
) E5 P9 _9 E' F9 h1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'( N3 |9 t) X" s9 Q: I
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition
- {; E7 E# y0 }2 p) _1482544 ADW DBADMIN Hierarchical PPL not functioning correctly! o# A" x2 m2 f
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode8 g* ^3 N: h4 c% e6 V
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles/ z% Y1 [3 I" j. g# x
1484100 SIP_LAYOUT INTERACTIVE Tool crashes when copying and rotating a symbol1 b1 T) H$ {. O' S b: \4 l
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues5 r$ w' `6 b o3 \0 ~5 d, c" q
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
) A: k) w- A! I2 S- @1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
4 A& \# q5 ]; u2 ?! m5 F& s1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project+ _6 s2 L$ k" ?+ p5 r# t1 n
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.- ?; H. z& I0 d: ]% n( _
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager.. }4 S: F2 x/ q) G
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems; B4 _9 Y) ?6 A6 Z" z8 f# v
1487125 ADW COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated
7 k8 O/ Y0 ]7 {( ]) z; C9 B1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior, `% P, }( n4 e9 `* ]+ A! m
1487496 ADW DATAEXCHANGE DX Changes checkout ownership when override action is set to remove existing relationships5 T* n8 H' i# K. G5 Z, ?
1487656 ADW LIBIMPORT PreAnalyze reporting false warnings
$ \3 p4 h7 e8 e, `1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
' [: K; O# i/ t+ H- b1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
+ k, M7 R6 z k) ?1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager+ B# X8 y; Z! H- D0 p2 ^
1490299 SCM OTHER ASA does not update revision properly0 ^. F( S2 Q8 F# ^
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer5 \& O8 f/ \1 n
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints8 ~6 C+ N; a% r6 x0 d
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
- ~% |7 _& k: D! S0 ^% s/ D4 a4 E q8 n1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
0 H, z' O0 `# [$ P* h7 }1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong& i( V) k* K- P. [( f/ m$ Z/ \1 t
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit& F+ q$ e" D4 j
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash" H9 }) ]1 C# k( F
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
* Z: C: |1 F( b7 q3 k" Q) W1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs
3 `; O; K+ v1 i& _2 g7 s! z1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size" p# w; C0 s3 Q) X- B
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root9 p; P1 y) j0 o, F# U
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file" R2 v+ c H1 U7 U' _
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60: f, r3 ~ u) S2 _$ R0 U% h) ~
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
5 h0 @5 u$ [9 ~$ r2 W+ ~1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts
) `. f: L; y5 u2 y* [' O2 p1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
5 p# Q2 v( E: F& g! A0 z1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
" N: T3 l1 a7 {; g! }) B# K- I1 g1501294 ADW COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration
. @, P" Q: _% f3 b! s. Z$ @1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL9 \4 Y2 v2 C: A
1502282 ADW CONF What does Message: 3 > 2 means?
5 p' H5 i, M' X) I1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
1 V" H: s: H8 I; |) ?& k4 V1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
" A0 N x8 p/ ?0 o |$ o' V7 h1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary+ G1 q. i5 K2 @# s! b
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
* C. v$ J u* d, L) s9 N1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
) I) X; h' t7 }2 _1507497 ADW COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol
& R! l8 u" G' n. L# D% a2 D6 t. D5 f1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork* p/ W0 H* I5 F$ H6 b
1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
4 `9 D/ p4 e* G$ ~% J1 z+ B! ]1510570 ADW DATABASE ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa
- h& z8 ]- _$ v% O8 r) A1511180 ADW DBEDITOR The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri( _. [' {; k8 q( b8 G* V
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6- t) Y2 u# I; Z
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance k- b6 y& j1 N. T. ^. E, e
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.
! ]. _& N( @' a9 A4 I1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
% c+ ]' I4 K) b1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
' |- } t6 h( R& u) L D1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib' b' b) u+ T1 d& y
1513737 ADW CONF DesignerServer from a different network domain does not show distribution data
% o: T2 i9 b2 A1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property4 s, s2 ]' y) W2 v+ e
1514942 SIP_LAYOUT CROSS_SECTION Why is AIR not permitted in stackup in 17.0?
% x& ^7 J! ~, p, U Q1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly
$ F% W* J" V8 a: k# C1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
# Y, r$ U* {, f: ^1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
7 B) T& e3 ?0 B3 f- Q/ b1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'2 T2 g: G# ]; L% B
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
. D! i H5 ^4 w8 s$ w6 \1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.1 G/ \0 c7 P, s; w1 F
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
0 J' E) t, `9 b. b0 ]1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas
4 W/ v7 Q+ q# P- e4 ^" X* J1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
, v4 M! V5 ?0 P0 C* ?3 \: `1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net
3 X, ]4 B; W0 ^0 y- W% ]; I1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
( y4 i5 {0 r( s1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
% B. F% w. N1 X( h% }1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
' E6 ~7 s- q" O7 t. c' p7 |/ F4 m1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor W$ _, B3 S& v& F3 J
1521871 CONSTRAINT_MGR CONCEPT_HDL CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning/ `! l) S, g4 J0 U- O
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents., g3 f c6 Q; O9 l
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design
6 p( m# ] y8 l4 ~$ V, l N1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash, C ^: n" D( M2 z/ w5 w: O
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated. O' ^6 P% d6 `- ^
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine3 F+ Y% R9 D& d, G$ Z3 J1 ]
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor7 ~2 u9 H+ V$ e) g% N2 a/ {
1525883 ADW DATABASE invoking libimport on an existing DB should verify that the libimp_su variable is set correctly% b$ m5 }" L0 O, t
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct, |* |$ }- z$ D3 A+ m+ Q. w
1526914 ADW LIBIMPORT Can not import to new library DB4 s x: K+ h7 h% b; b0 Y
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
5 z& @ z$ t- x! i0 Q6 @1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'2 M: V. S0 e) z' M
1528235 ADW DBEDITOR About the rule "Validate Classification Property and Property Values" of Release/Pre-Release
2 Q1 ?# G5 x- k+ L3 Y1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
% o2 p* e- h+ m# Q C1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property
( H" R: Z- D2 B* i! L1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
* Z5 Z- K# n3 d+ o- Q7 C$ d# E1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents Part's release, q. T+ |# j9 T( A( F/ i
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net
# L; R! N4 P3 \# I; F$ j# p1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
: ?& q3 e. m6 T3 Q, h1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file( N# g" U( f& y' x( _
1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used U2 Y: K! t) _$ b% U+ k9 {) z
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
. P/ V8 K" G6 R; I" |1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
$ Y$ W1 r0 K0 O2 c' U: P6 I1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
1 o {( d5 c% o8 @1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists+ b0 z: `5 G8 I+ F% _/ E2 c
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue8 a& p) `! t- W# j* [4 [
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties; I# [. V3 N. v: l
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
7 d+ C9 x! Q/ |" t: Y/ t' g( U/ k( w1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform- f* b) T2 ?$ m4 s, E' _
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'. Y! e* }- w) m) \
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor. F$ Z) g1 H) z8 g( K
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run: ?6 |( m; I4 {
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error5 g, B6 p1 |! g* B! D
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
0 p; T, \( D) P; |$ j0 Y1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board
, v+ _+ s# P1 f3 b8 ~ l2 E1542949 ASDA EXPORT_PCB Export to PCB Layout Fails to Accept Entered Output Layout File Name
& f* C7 A9 S1 e5 h" P1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer7 |& s- i4 Z* l- e/ Z& W; q4 J
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash( v6 }) M# t5 H/ @* I i) z9 F% A
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash% X a4 h. I s! n b. r7 H8 [
1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked* G6 E, T9 ^5 v; p: P. R
1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.
9 t6 S; s6 v6 ~3 J, T6 k1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
% e1 w7 E5 P5 u M8 w1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information
# G% w# {* ~& Q0 z. L7 X1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'2 d/ T% t. y0 W$ b. M2 ?+ m$ `
1549658 ADW TDA Unmapped network folder in TDA; f w9 C& x! O3 W# T6 C
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols c6 Z7 e) U" ~& ?/ Z- j
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects; s' ]( _/ S8 h
1553027 ALLEGRO_EDITOR UI_GENERAL Beta - Allegro display freezing very frequently - canvas not resposive and turns white.9 ~5 w: c" Q) |4 O$ S' ?
1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
/ e- ~& p( c/ c2 \1555254 ADW DBEDITOR Loose focus on Free Text search Window removes the text.
5 x% w. A7 r% W d7 E) C0 r1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
: Q. l2 l: F6 G% ]1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export# W0 l5 a8 R/ Z A! p
1580571 ADW DBEDITOR xml files for released FP and padstacks are left in flatlib area.' F q: U- b& h Z- a
1580580 ADW LIBDISTRIBUTION list files are not getting cleaned up for custom models if they are purged.
3 l* @8 n9 V3 ]+ ^, y( L. V5 q0 ~: L7 C& q1582064 ALLEGRO_EDITOR UI_GENERAL User defined menus not working in 17.2
6 ~0 L) X0 @# Z4 D- `1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
( R- {9 _7 @- U( a( ~! G* N: |1582856 PSPICE MODELEDITOR Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created: W* |5 p6 A* q' y& J4 }
1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
: T' w" `) G# D; N4 R5 I1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file3 i4 |, p" f5 D, k
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option
+ u- P4 y# F, W, B D% q& i- W& J* b1588736 PSPICE MODELEDITOR Model Import wizard says "Invalid configuration" when lib opened in Modeled
% _5 o2 W: Y8 y2 g/ g% a1588742 PSPICE PROBE Browse icon is missing from Pspice File > Export > text
i& u+ x- }/ _4 e$ x1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened7 p* r, Y: z" K- N
1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons/ ^2 n3 R. M+ ]0 O/ s! y1 Y* V& ^
1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork
d; p9 ?7 y! R- W' \) M8 P4 n1592089 PSPICE MODELEDITOR Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator0 J+ _/ m( z4 ^0 E
1593436 ADW DBEDITOR new Model type form does not focus cursor in window, User must select the Model Name before any text shows up
& B3 k" a# V c: L0 F0 Q1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
1 m0 t9 s8 p& g! T* u. K1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode( t$ v" h5 x2 t8 d9 i
1596162 ASDA IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well
0 X# B7 ^/ C3 e1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names
" q* [+ P7 ?) a% w0 Y4 [; S: T0 d1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas
, T+ E) x9 q. i7 Z$ d! H1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated
! L6 m* l: S. D3 ?; C4 U }6 A1600194 ALLEGRO_EDITOR DRC_CONSTR Update drc command changes the amount of DRC count when using 8 threads1 ^1 n* _2 e' s: ?* V c
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating! B) W2 Q! J4 B8 G# u" X% o
1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
$ g: W2 j+ ` R( {2 K8 _1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.0 L6 ?- E$ H, r3 q
1603377 PSPICE ENVIRONMENT At Markers Only option does not generate .dat file
: F5 [0 m w# N: U1 P# [- h1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header% Z6 M S& R5 C$ t+ ]7 ~" W
1604741 ASDA CANVAS_EDIT tcl console changes the present working directory (pwd) when you open the proj preferences & close it., d. o+ r8 Q2 {6 q p% c
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard- G3 d" p- A! L" ]0 m
1606861 CONCEPT_HDL CORE Crash on Linux during Generate View
" r; _5 d- y9 q/ @2 p1 {1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset
2 x! ^' J8 ]; c+ ^! D; p4 x+ r1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons
1 ?7 U4 [; h7 ? F- ]1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set
8 Y; F' B# d$ P' U1 @1607568 ALLEGRO_EDITOR NC Allegro shows wrong drill legend Top to Top drill.& Z5 b% P# r! t+ K
1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath skill command in SPB 17.2
* |9 c: Y2 \1 z: Q2 S4 I$ C8 u8 ]1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.! q9 Z# ~- e) W2 v
1609400 ASDA CANVAS_EDIT RMB > Assign Differential Pair should be grayed out when a single net is selected
V# S7 U( o" d3 Z1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux
0 U- W' w7 z" P* r0 v, H8 d [1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.6 V* Q& _: ] I* f* c* P, J
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only5 F5 W! K" c6 S& x% r& s: a
1611226 ALLEGRO_EDITOR SYMBOL Allegro shows crash message while saving flash symbol.
# S. T/ s. g' u k# P4 v& D* F% Q/ U9 z1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.3 ~7 S: f8 a7 b7 j/ k% j# u
1613123 ALLEGRO_EDITOR SKILL drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT. O/ Y4 L- ^% }- o3 ]5 |
1614000 ADW LIBDISTRIBUTION lib_dist does not complete and does not allow to delete the .lck file.5 s2 i3 f7 H; n7 H- U
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp
( }0 r+ k6 x9 w' _% d& _1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error4 a" ?% s4 P: d1 O! i
1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import doesn't map layers correctly$ S8 \1 ~, d, x8 v
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update
8 o1 U8 x/ g' U! |3 H1616733 ALLEGRO_EDITOR INTERFACES Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated
, m0 t/ X" E E5 C$ x1618751 ASDA DRC SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file./ R/ o7 X# L- r. Q# d8 q- d
1618797 ADW FLOW_MGR Flowmgr fails to execute command- F0 r) v* [+ M% L& \
1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.
( f3 H! y( z$ G% P! M& S1620350 ASDA EDIT_OPERATIONS Uupdating version for a connector pin looses the pin number
J* J2 h3 p, f: X- y5 k1621963 ASDA SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol.
5 a( v: q$ @ M2 V6 d) ~1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet crashes the tool& [" j* K1 S2 k. I" B" l
1625209 ASDA IMPORT_PCB File Import from Allegro shows board differences- G" B5 _) r4 r
DATE: 07-28-2016 HOTFIX VERSION: 003" \- e- s4 g: P. }+ C
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CCRID PRODUCT PRODUCTLEVEL2 TITLE3 L- r% D1 J2 j
===================================================================================================================================
4 X' |. g* ], _+ _. h1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result
8 A$ q; s/ x- c$ g6 K) R8 {% }6 E1461626 CONCEPT_HDL CREFER CREFER shown to each instance of block pin though net changes* r) g1 y- ^' C3 h; l. i7 r4 n0 I7 L
1472456 CONCEPT_HDL CORE XCON and design are out of sync
|/ W: p9 T# q: A1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
, |( q3 G" [6 Z- H$ ^9 x1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066: i! \# r) m/ W5 h% X5 E
1560102 ADW FLOW_MGR 172BETA: eval in command string does not work) }2 [, R4 V) M- s
1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View
8 S2 {1 K* J @" H1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
5 {- f. v' T. M1578876 ADW ADWSERVER Component Browser crashes when trying to show details on a part number1 {: F1 k! K( Q0 O4 Q, k6 e5 {, c
1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found
* w: X) X+ f- C4 {# C. t3 f1582863 CONCEPT_HDL CORE Generate View creates non existent ports/ ^: }) y3 f* j, D
1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window.+ `" ]* e( O: X. @! E6 Q8 b5 u
1587018 ADW FLOW_MGR Project Update at Ericsson in ADW 17.2 asks to specify flow name.7 Z ]# L+ v1 R F. l
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties( F( w6 P1 u( A! p; L7 d3 g
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed
g9 T: C) V. Z, V# p3 J1587718 ADW LIBIMPORT Library Import Pre-analyze report is not being written
; X7 V$ s- o7 T/ L( B* Z, z1588197 ALLEGRO_EDITOR INTERFACES STEP output fails when External copper selected on Win10-17.2
5 N; O- M/ F" E! s: j1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
# Q5 E% V; k8 G4 ~6 }2 m1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component: @% \- S3 d8 v2 e, Y @ N
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC between Embedded pin and via which do not share layers
9 r$ o) s% q0 W/ b$ [4 a1589979 ADW FLOW_MGR Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project
$ e9 a7 Z5 B4 X6 n1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior8 w8 w: a5 B; G
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design
2 T7 e& [ e9 {2 g1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
+ ?6 l8 l$ f, y0 I' P/ I1590720 ALLEGRO_EDITOR INTERFACES Text Size Parameter file does load names into the text table7 y* d' s, C" t+ _5 I6 Z
1591070 PSPICE PROBE PSpice crash while evaluating measurement from trace>measurements% e4 e( _0 h* E% s
1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic M3 M$ Z! H" g; {
1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived
) s% {* s( U: m' L# g1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crash in 17.22 s) z, e0 s, U+ u2 \
1596615 ADW DBEDITOR Component Browser didnt come up to search parts, also the database editor didnt return search results$ Q. i# [9 M. @4 m" H* ^# E3 z
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
9 F2 C- c5 o" }, s, U c1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
* @3 n$ x+ C/ ^7 }% B& e M1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI: ?$ Y* c, K6 U' E- o$ D5 _
1598629 F2B PACKAGERXL Export Physical crashes
" n" z6 {: j" U# Y6 W6 x1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
. J0 l2 F( D2 d1 b1599744 ADW FLOW_MGR Few flow manager buttons are not working in EDM 17.28 `7 i, k, Q4 j4 ~' r5 D/ h
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.* Q) V9 u7 o/ h3 Z( p0 F* r& p
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group
- R+ a$ o! C$ |+ v4 Q3 y1600618 ALLEGRO_EDITOR DRC_CONSTR case sensitive issue with Physical Constraint Set' F1 R# v' \+ z1 C. y
1600914 ALLEGRO_EDITOR INTERFACES File > Export > PDF shows the shape as unfilled.
6 l. t: l; ~) _3 P3 `1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad
4 k7 @, a& D3 G: H0 O1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
4 _$ s! q" m8 Y1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
. J, a9 I6 l& t9 ^1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
( W: c6 x( A i: D) m5 ^" G1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command
- [4 X) S# y( E/ D6 v1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.+ v1 `" Q" @4 q' k6 _$ K) W
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
/ M: |; C7 N8 A& X9 Y1604746 ALLEGRO_EDITOR OTHER In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools.% @, C' B W7 e, u: _
1605322 ALLEGRO_EDITOR TECHFILE Cadence SPB17.2 Issue - Long duration in Tech File generation3 k5 F. g" K4 g$ W* x! Z3 ^& @! L
DATE: 06-31-2016 HOTFIX VERSION: 002# E4 s1 z9 L# {; H+ k
===================================================================================================================================# n* r; V( s7 ]* E
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( t6 g6 Z+ ? y, R! E C1 y===================================================================================================================================9 F7 u/ @, [' W) B. _
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets J' }! t9 r# C0 k
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package
9 t' x/ J& n! Q R6 I1481802 ORBITIO ALLEGRO_SIP_IF import of oio to an existing sip offsets the results incorrectly
+ t1 B0 k) a$ p% }# j1518957 APD SHAPE Shape void result incorrect3 \$ }/ K' n" n7 {
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error* y4 |% U. r# ~: {& L% s3 e' g2 K
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
$ j1 x0 k4 A0 c1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
" D! n4 i" \5 k" h. w9 O* N1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.) {, \* J6 z$ I
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)2 b9 Z: d% [1 I8 r" _( u
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set
( x4 e2 c7 d& r( O% n2 W- J+ z1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
% b* s# W( K# u1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library7 B" y3 }- R) q0 V/ t
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
; b- d; B( _# T4 H1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets. [4 X! X/ l# A
1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation
% Z! O: U( g6 K* X1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
& |. Q! H0 p& o# e+ ^1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
* \3 H q: B" }6 V6 ~0 m6 v1561501 ORBITIO OTHER oio -> SiP refresh seems to hang
# z5 N4 m* z7 M- N1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
: e: r# ^+ j" W- f6 i6 t( g1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins
& t C, I! I, C: t2 ~% a$ r, i1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas% l# A; p* v( I: D3 o% R; b9 u
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions7 ~) D) [' J: w. O* S& x
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
; a# b) ]* ]: v. [( s7 D1566942 ASDA MISCELLANEOUS SDA172: A lot of files in /tmp/ on Linux
: J+ E1 O5 `$ b1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
0 r( f0 X- t$ S. z- h2 k$ q# Q1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct. q5 ]' Y* n; W3 k7 C
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window4 C2 f# w& B" G3 k
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
1 }" l& h8 L7 b1 I; v1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed. n2 k& g6 Q4 O M3 X! X2 Q6 H* L
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2
8 J- Y* n, O, { \! b4 C) n8 b1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...
/ \* w8 L9 ~( _1 Z: T( Z" u1570398 SIP_LAYOUT DATABASE Diestack layers can't be deleted if there are unplaced symbols in the design8 x- I, D! u+ P
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
6 c! Q+ o+ R) T' y, ?+ _# T( U1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short' g1 i" m) p9 [4 y& } x# z
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property; ?0 ^3 Q E6 a
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only
]( p/ [1 ?+ \5 l* o6 f1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
: a( p! M5 E4 s5 `0 F6 ^/ o4 f& Q1 K1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry
8 O; e1 r4 Q! h1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
: n* d7 k6 _* B1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2. f2 X% [# N. M2 i- x4 f5 ]+ }
1573755 ALLEGRO_EDITOR CROSS_SECTION Switching between plane and conductor changes material in Cross Section.8 K i2 Q& N4 D% o5 Y
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
4 s% P. ]6 {" |1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings& H. T2 n. b& j x: T
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'8 X8 P) ^4 B7 O
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure# G% U. z0 J( M1 I, g4 v& f
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files9 X6 a P) e" p
1580891 SCM REPORTS Dsreportgen crashes on different scenarios, v' l9 m/ `) ]) ?$ Z$ E$ b9 c
1581254 SIP_LAYOUT CROSS_SECTION "Apply" or "Ok" crashes XSection
0 k' n$ j3 L( e% b& v1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error0 J1 H- Z3 N4 Z. o- c
1588823 ADW FLOW_MGR UNC paths have stopped working in Flowmanager in 17.2
3 Q, E3 D) w( W! L5 e3 L1590064 ADW LRM EDM 17.2 gives LRM unnecessarily.
: w9 Q0 Y+ Q) bDATE: 05-06-2016 HOTFIX VERSION: 001% l8 Y# M1 K) W/ S9 @3 W
===================================================================================================================================
& _: Y# |% e" H- {8 ?: Y: oCCRID PRODUCT PRODUCTLEVEL2 TITLE7 c( ^! {1 c1 k. K. l2 N
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output
3 A& L* t# R# \5 {# k1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
% j r6 c2 e2 {$ Z1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
! s7 P8 H& P e }1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail
6 t U6 E' f2 s/ _9 H" z& M6 R/ w1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol# y- a k k) U5 f: R6 n
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser0 m, h% a6 h, N
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing7 I D. m$ s+ J6 E4 ^, @* i
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager1 O5 e9 J& f' d# q5 R: V1 @1 J# A1 c9 O
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute3 ?; y t! O$ R+ d k5 C: D5 ~
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
$ D- y/ ?+ L8 m2 G1 B1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
; L7 }# T* |3 v) B/ _' }1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork. n# S$ t$ F* S4 R
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed( x/ H; e' a- H
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.1 h' R) T @3 |9 d
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
9 Q G4 H' Y$ i* F1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols' e$ f/ J+ P% R7 {
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work
& Z8 I! u4 m) W! v$ x& ]1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file6 M- B' X; M9 E7 A
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design, s8 [ J# J* v [: f9 h
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license+ r1 b7 I- S. E G- l( Z U
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork/ J [. E, O4 v; \5 U
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message- q% h5 V1 n( B' ^
1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system" ?$ O6 y8 a/ q) [
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.
' e! i1 I% c" n7 B1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol& l" @5 B# t: g0 s8 i' k
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file
: r+ T# F/ ?! j2 f# O1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report- _5 U' Y! _3 X5 |" z
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines( M6 h! j$ x: U" k5 y) p9 Z
1549662 ALLEGRO_EDITOR OTHER Import Parameters Path' fails if parampath does not have the current directory ('.') set
+ C+ c) M/ R. e. j4 a- }" `1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts
0 t! z! P/ U# [/ p$ s; v# ?4 M2 U9 R1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems+ @) [3 U, P8 F/ j# Y
1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to hole drc between Via and pin4 @" g' ^0 H/ M4 q6 a$ M
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro
f* `% f% i' r4 S/ y- D1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups
$ P4 w1 _! |3 E7 F7 x7 }( ^6 d1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons
[& G! w# m* l# K# ?- r1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes1 h: r9 @: F3 ?# h6 {+ [
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted! V% h. G! O" Q8 N4 @0 L8 E
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die* ], Y5 ]9 R$ k) }" e* X% A$ f
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM+ X' E- V5 ~3 ^1 {9 ~7 C
1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
g/ D: A. h; ]: ]% g1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error
2 K, \4 p; Y5 z1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.7 @0 g( \8 d; U/ [, z/ ]9 p
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发表于 2016-9-7 01:03
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