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DATE: 07-31-2015 HOTFIX VERSION: 054
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694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL" w, c/ A3 l- J* d; g) {: B+ y
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions
* c8 K/ d& @6 u7 w* R6 i; u& j1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List$ G* A1 \: v) i
1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate6 D; ~0 ?( A+ T$ a
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees' x- E/ s2 V( ?
1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias
- b# \( l1 l; T. P3 r Z1412635 APD DATABASE APD crashes on saving design) j$ _" D2 b3 b: }2 Q
1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices
+ y0 G6 D+ b# I* ~+ q2 |3 x1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation% v$ R' P$ w& _
1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.; Y) b1 I, Y* u* E
1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50
& S* b: C, j1 r' W1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
. w1 t% q& ~9 {+ Q9 n0 |1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module# R/ U1 t. s0 V8 B+ y
1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated% s. w6 T \+ B: [1 T% J8 [
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output) h9 L6 C) ~% v6 T% o& J
1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification6 r1 v" h+ O, ^3 {1 s
1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.
* Q8 U; l0 r" ]1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets
- S; S `; d1 u0 d1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor- U& a: j2 o4 R5 r% Y2 V
1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow/ l3 C$ t: r2 N
1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
) m* L' s [) n$ S5 T1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board1 A$ i# Y* N$ a
1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks
% H) x2 B. g- h7 Q1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports! K \5 n% ?9 {9 K- C, p) v' H
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC# `9 D2 M, b: ~. B/ ]
1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary V1 s4 p* }- D: l6 V( Q
1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.: y/ O% V3 e/ ~* Y
1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1
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发表于 2015-8-3 11:54
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