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CADENCE SPB/OrCAD RELEASE 16.3 README --
' K \8 `; J7 kWindows Version 1 z8 h) s0 @" r" y+ h
Installation Guide
8 T$ O H9 }, S- `7 AYou can find the Cadence SPB/OrCAD 16.3 Release Installation Guide for Windows, Version
& i5 l9 [0 B0 t7 k6 n16.3 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD.
& F+ [3 r9 f: ~- n* [Migration Information
4 o# H. [( r; a2 UImportant migration information is contained in the Migration Guide for Allegro® Platform 8 w+ \& g7 F% B( c8 B K+ ` J
Products Release 16.3, which is available when you install this software or on Cadence Online
& O, j1 _7 X K& l4 F$ ~Support (http://support.cadence.com). & Q: D7 D. C4 Y$ g. K8 G! L, I
, [& ?) F; r' W- c' K7 W2 \NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners * j: `/ \9 y( m* o5 {
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
; t- O0 U' t& D/ [System Requirements - h' q+ ~2 W" m" M9 ?
Information about minimum and recommended system requirements can be found in the
7 r' _; ^0 @$ BDocuments folder of the Disk 1 folder in the Allegro Platform System Requirements document ; Y. Q" X2 Y, B# {
(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com). " k+ f1 t# D* J0 ?& Z
4 d( H0 x/ r. m+ j$ S: j' lNOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
# n; t! R5 N# [! Ware listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. * R p. R/ ]( E( R) P
What’s New
( c6 w, ~# P3 o5 [4 p% FProduct release notes are available at: 0 }6 k g3 v8 K* i$ ]
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin ocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi[/url]
% Z7 X( B, Z" P0 \" o: n5 Zng/spb163/prodList.html 7 M+ G1 h+ B# v; ?# R+ D. f
KPNS
3 P/ }' ]- l: A2 W8 J7 b8 U. D6 aThe Known Problems and Solutions (KPNS) document is located at: ! T+ W, p2 t8 X8 a5 q' f' C
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi[/url]; b2 a- w2 s9 o) U( L0 G; v4 J. u
ng/spb163/kpnsList.html + I- J* k. ^' b6 g1 z
Allegro® /SigXplorer® ABIML Libraries for Default Trace Models
' X4 `) o( m4 i8 lwith Surface Roughness Effect " f$ V0 G8 D* Q9 ]6 @) @ p
The Allegro /SigXplorer ABIML Library is a free library that includes ABIML libraries for + W2 G4 j, @ c6 ~
SigXplorer default trace models with surface roughness effect. It is designed to provide accurate . y0 @2 r" r4 |" ?+ b
trace models in Allegro /SigXplorer without time consuming EMS2D solver runs. The libraries # Y; G, _9 y' C
can be found at: ! }, R0 u3 \. s0 N/ y
http://www.cadence.com/products/pcb/pages/Downloads.aspx ) Q$ f1 y" s3 Y, P, K. n
This ABIML library is provided free of charge for use with Allegro and SigXplorer. The library
7 r+ v' J% p( a6 T& T7 |' wis provided as a zipped archive, with installation instructions included.
4 K# N0 \: s- G: T0 f, T5 vCustom Environments 9 L. Z8 e1 m) x- ^' K) C
Customers using custom batch files or scripts to set up their environments must add the following . {& Q6 r! @( g* W: Z# c" ?) j
to their path. There is the potential that some Allegro products may not launch without this 1 e7 i. b: ?) O( ]' k
setting.
3 ^, P4 _: U7 Y2 n! M/ S%CDSROOT%\OpenAccess\bin\win32\opt Downloading and installing SPB Software ' Z$ u- o( d* v% {: Y7 r
Cadence software can be downloaded from: 6 K+ `* O3 w7 g6 P) t# b! F2 j3 B
http://downloads.cadence.com 7 S/ V8 U, Q" o0 B- R$ _' F- Q
4 f1 e( e+ _8 S! [6 g/ t3 vNOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software.
. n# g6 @$ y/ o; V3 ?: bCadence Channel Partners are listed at:
& S% |# }& U5 w+ `5 Z8 n6 lhttp://www.cadence.com/Alliances/channel_partner/pages/default.aspx. ' Z9 M# m: D0 g; |/ a% r* q7 r+ U
1 @- K! k4 b+ B+ G, ]Download Disks 1 through 3 and then extract the zip files into a temporary directory such as ( C4 R' U) ?' Z9 i8 i3 A
cdnstemp. This will leave you with a directory structure that looks like:
' z# ~- I* k" {2 L$ O
( K) _8 E+ ~1 G; [/ }$ fDisk1 folder ; q8 N) t* z3 v
Disk2 folder 8 L) g) {# l0 e. }
Disk3 folder / d Q8 B6 k4 O0 Y' s6 k
autorun.inf
3 h% l0 g/ l& K9 qsetup.exe # K/ c5 f: a) S8 Y/ X/ n# |. u5 @8 u
setup.ini
$ P* f# b1 X2 r: X3 p, L! ~- q& B . D& H0 [1 ], z
Complete the installation by running setup.exe from the temporary directory or consult 7 K3 Y( I& w! X" ` d. U* {: D- R
the installation guide for more detailed information. ; N; n1 l% [2 {; q- I8 m2 C
5 o; m/ Q5 v- F) P# s, cWARNING: The installer will automatically add the programs in this release to the Windows
# ~, A0 \/ ]! o. k! g3 PFirewall Exceptions list for Windows XP and Service Pack 2 at the end of the installation $ A) _% e0 A( F# X) |
process. If you do NOT want the installer to do this, you must run setup.exe from a DOS ' ^& z$ H; N" A9 [5 w' Z' f
command prompt window with the following switch:
' j1 v" Y, @7 C0 ~ & G$ r1 b* U, o
setup.exe -nofirewallexceptions 3 e2 }% I ^7 U" L% D
0 \1 j6 A' M* k4 i- o! lWhen the license manager installation is complete, continue by installing the Cadence
8 m, F& B& q1 Z- ~ g3 \products. 7 L$ _1 q: Q, D! J5 t! K
/ r# F; ^3 d6 ]: W3 \
NOTE: If you are prompted to reboot, reboot the machine and log in with the administrator _* a) ^! t6 Y+ R0 k
privileges login id to successfully complete the installation. List of Fixed CCRs 8 B, r7 A0 S/ r7 V0 Y
• Enhancement CCRs 9 }" ^7 `3 e! Q2 o" V
• Bug CCRs
$ V5 Q( r3 W W' q7 x0 u; Y3 ZEnhancement CCRs: ( s: g2 s3 Q L' X
7 U: m: }+ M! }" ^# i3 N: J H
CCR ID Description 0 X, A+ k* G- I* d
7419 Customer menu options added to Allegro menus
( x" s0 I0 G2 g8230 Use via in area constraint does not work
" l6 o) X4 \+ ~6 ? W. k ^3 B10658 Modify default formatting for Label texts and linewidths
: {6 J+ m5 ] R2 g1 G2 T# Z6 t: ^12216 Cannot set color or line width for wires on net-by net basis / \ d! V6 v3 Z9 D9 E+ ~
13083 flip/mirror design to back side
8 @9 ?! W" | {8 A( I W4 p! o13373 Select length of pin graphics
- x- V p$ M7 N9 }. K- p' L4 m; o6 B18072 Add docking option for probe cursor box.
4 _4 B; ~1 }; x0 w5 Q' a4 {, x21451 Change Probe print trace color yellow to alternate.
* o6 s% h7 j$ Z1 }; v) P! Z32798 pxllite complex hierarchy netname enhancement
8 V% J2 C" Y. G33896 Option for changing the PSpice probe cursor : Z4 b( {( H8 d( t( D
39600 Option to see time spent on allegro database + y* {! c1 K0 X( D! N
40754 Linux OS support for PSpice & f2 m7 {- |' i
60427 Add different subclasses for pin_number top and bottom ) I, V6 G) t5 T7 {9 t5 Q" C; I" I
77555 Capability to export PSpice probe data points in csv format
% s0 _( H5 U9 g107219 Capture.ini switch is needed as a Registry entry like PSpice 5 v% N/ S; n6 P' N! r$ }% U! l
132769 Footprint viewer in CIS should also show pad spacing info
& G/ w0 M4 r# s& P- \158838 Need easy way to delete marker
( {$ ]9 |5 x# R2 C( f% a: H* M159977 need attribute mapping capability in mbs2lib and mbs2brd
# e) \3 p% o& i- w+ l162382 Enhance quickplace using schematic page from ORCAD 9 s, H d. `5 |4 O1 S7 g0 O4 ]1 G
164790 Improve autorouting quality on diff pair w/match length rule
C, ~" d$ M& F205909 Constraint Manager displays in Allegro no graphic mode + ?8 k- n/ `7 |; n$ a
210027 Delete dynamic shape removes net name from copied vias , S! x2 \4 g+ \# c0 m" o
222127 PADS_IN: Constraints are not imported with the design. + x9 B! n8 ^. b
236698 Report Unused parts in multiple parts package should be DRC . A, o+ g2 D; o& f9 n% [
240525 Add ability to change cursor color in PSpice Probe window
2 [6 q! v! Q2 s8 L3 _: V) ^245193 export dxf height information when blocks are unchecked ' n- K8 \7 w1 v- h C5 E5 @
254183 Multithreading for DRC and CM analysis in Allegro
2 D! M9 C# j0 B282027 Problem with Split Part and part graphics
) R" m) s, s% n7 y8 R0 N282507 request to import IBIS file directly , r& G( Y1 y z& S, @/ C" O* D8 t
283698 place by schematic page number window need enhancement
- n, y. D: B, w2 W288540 Schematic page# display order request for Quick place
8 L( C# q* J" g1 Z% U$ J. |' C290283 PSpice - Probe - setting background color from UI
. a. A j3 k7 W4 {- F/ G. j2 h290641 Option to copy paste cursor value
! l h D4 y/ i! ?2 P) u: \) j298081 Models from Funtion.olb need more explanation & C+ e: q7 d! ]+ V
323813 Need negation and exclusion function in ADE reports ; ^: Z) D( z$ ?! h x
341484 Wirebond: Tools to generate wirebond manufacturing outputs 7 s; S8 r( P7 D! `
353212 Variant Name is not coming in Standard BOM
8 ]# i0 O& B& ~+ Q360602 Enhancement to Show element on a via
' z! e4 ^% W5 k2 t8 @. @# ]362934 Enhancement for Allegro to utilize Dual Processors.
; K* S# Q+ p M* a364850 change the font properties of Label Text
& k' P: k# d% h' m# }367468 Need a real DML_PATH environment variable : j& Y) k0 R3 j% k1 r
380714 Ability to have Power pin set to Not Connect 9 W: \- K1 H! t/ _3 q9 ?: L* p) O8 E
382860 Display parts and nets in different colors ! M9 t& w3 ~1 E( J
384488 Add DEVICE and REFDES filter to Signal Model Browser
5 k7 |, b2 i7 M+ c7 f3 r391487 Ability to have user defined directory for storing distribution files for MC analysis 5 w7 n4 O+ W4 U3 }( D( [/ ~
420008 The renamed differential pair names are different in CM of ConceptHDL and CM of 6 r2 f1 ]+ ?! H
Allegro.
( `. F& T/ l5 H O420023 It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on 6 m1 i3 q: b! I) O9 p0 I
CM. 420648 Need to get RF Elements to retain previously entered values : F( J+ {! x. `6 a4 X
429280 ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
% v' [, G+ o, h4 u3 Z430549 GUI for ADRC XML Rule files
& \7 U2 ^/ ]1 c; W( D" E! M K430558 Store last used ADRC rule check ini and check values in .sip database
. f( w1 A" o0 |1 d' l( I452606 Can we have last plot as a default
& l" B, X) ]9 @454452 Allow neighboring/overlapping die pads on same net to go to same finger during wirebond
+ f, \/ Q( @* }) Wadd. , W/ }% g6 B+ ]" q2 C
456854 full AMS Simulator menu without pspice.ini in registry
" o, _5 s: ~7 z! j0 E5 \: q4 ?3 V464056 Setup option to always prompt to baseline a new part ) [7 c: O* X% q; Y1 `: h5 x
469378 Enhancement : Hide/Unhide feature for trace # q+ j4 M$ u% `
475077 Schematic Generation Setup form is missing the Port symbol selection. It was there in the
5 b, Z/ Z& X2 N2 d% M; u15.7 release. # P5 e8 ]8 q7 [+ b3 k& b
475714 User Guide should mention that Temp Sweep is not honored in AA Flow? - Z3 [5 k: v: S* l
480843 Requesting ability to View > Zoom Mirror current view.
/ B' s2 x' }% A7 t/ \. h484632 Request for Bond finger to snap to Guide in Free placement of Bond pads ) G( H8 F% S) x& l, y5 W- c
490948 Provide a sketch line and text property form
& ~2 n2 y1 g! q. Y- g500550 CRef's should be preserved with the next run of the schgen in the preserve mode. 4 k4 Y: t6 l" o$ W; R( G
505284 Enhance The ConceptHDL can set the color for $XR0 property. 1 F: E+ x. `5 ` l, }. b
512748 improving arc routing
2 {, ]) S/ D. L- J* }513967 staggered C-line via arrays
) f: f: J( |$ f6 S4 O4 Z515333 Option to specify spacing between Components in the Generated Schematic
4 W' w2 y# E, d, D- a524924 Add PSpice enabled part gnd to standard library folder & Q- ?% s+ s' T. W i0 N
525748 Why is MC Analysis Sigma value 1/3rd of 15.7 version value? ' c2 B8 D7 `' W1 T! h4 m3 z' E
526818 Retain Hard Packaging Information option does not work for SECs. * X5 N! Z% L2 n6 X
528391 SigXplorer measurement is wrong
6 R0 `8 G9 O6 p1 e% y) N" z& @533844 Allegro password not encrypted in the .brd file. 0 X! [* E |- E
536681 In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge 4 o, I, c8 |, ?% n( r2 _5 A
Spacing
4 y/ W. l+ c5 U- |6 @536948 Allow sorting of power symbols 0 ~. t# T' q9 {* M
539407 In ADRC Minimum Shape Check requesting individual "Layer" option / M7 X, p& ?% N2 ^0 ^& }& m! J- N6 Z1 U* F
541145 slide command does not support to keeping the existing arc
' T N3 r5 h$ f( |2 z541214 about supporting OpenDrain Model in Quad2signoise
( J" N% J+ D* Y% Y3 \0 S4 I0 A542414 A function to force diff pair spacing to primary gap.
1 \1 z4 x' v" u- p e4 w2 \542803 A "Minimum Shape Check Soldermask" entry is needed in ADRC
! S) ^$ j9 M6 \+ E543470 Provide rectangle and line width thickness for Drill legend in NC drill Param
" [7 |( t; d: O5 u543766 Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks
( E5 V: j3 a1 f# O5 e; v! Q/ \545408 Cursors are toggled off when deleting a plot " } C! F5 f1 P( r8 m" o
546891 Enhancement: message improvement when expand design action in Concept
1 [4 w" g" i; }) \- ~546985 XOR function to allow to compare layers within different or same designs 8 h! f! R3 d/ Y# u1 T* ]0 Y
548920 Add a document of which properties can be synced and which cannot be and the files
8 o4 V5 t4 J- `& b1 V7 Xrequired
3 j9 q7 [: C7 F( b553669 Add a 3D viewer to Allegro : b Y, Y8 Y: \; C
555183 Wire Bond Report --- Report field should have save function for reuse / Q# ^/ s5 U/ p' v, v( C: ~5 z* c9 u6 U7 G
556200 Need listing of DE HDL command names and switches. 3 o! V: A) m4 W2 e2 v0 y3 w4 X0 [
556883 Grid point for Origin to be highlighted . p j, X/ L1 m; p$ o
559638 Enhancement for importing height from PADS in allegro # o5 H+ `4 q. p
559724 Request cline via arrays to be applied to diffpair nets ( C5 `0 H. X) g1 r) e. `# J- Y8 L4 _' B
560134 Show Element Customized Display
# `& k- E6 q5 {: ]563957 Enhance Color Dialog form Class/Subclass section to expand vertically when the form size " y2 t6 W: J( \3 s1 c
increases.
! d; M S( i' N% c6 V- L! |568058 Request to have component information available through the context menus
8 j' E1 ]. l, ]# Q568273 documentation of variables in Capture.ini
3 o: h9 ^ _ {# X569615 Enhancement to import constraints from Mentor Board Station to Allegro PCB
1 z/ j2 O) N9 T) F569680 BOMHDL defaults to the wrong file type when html report type is selected
K: O7 i7 h W569784 Request ability to assign netname to via during copy
# S: X3 B1 d8 @9 r1 g569863 User would like to set a larger default trace width # }! H) }# v* |1 K
570128 Enhancement : Packager setup for subdesign drop down 6 l( ^4 N4 D! L8 @! ~2 M. f1 Y
570195 SiP - Provide option to create/combine BF labeling with additional text required for Bond 6 W, p9 J. E/ u7 u9 M8 r3 m: \
diagrams 570861 Unconnected mark does not be removed even after wire is connected to the pin.
5 {% { V1 v2 Q" w575211 Web links in CIS explorer are not working when Firefox 3 as a default Browser
2 d$ q9 T+ O% ^- y; T0 \2 D577944 Enhancement request to have the drill legend for thru holes and slots to be separated without 6 \7 T5 m! u* b* j% `& n
being on top of each other : B7 C6 u1 }8 c6 Z( K/ L' r2 A
583630 Can Multiple Section pop up box be disabled? 3 {3 h8 k" Q# Q$ _: W5 h
583712 Ability to have string values for SCHEMATIC_GROUP property
! x4 K5 @, `- a! }4 e% N$ Z2 ^1 X585904 Find a schematic page with help of nets / y; d6 F. e! o6 ^% Z
589316 Document change in Gaussian distribution for PSpice MC from 3 sigma to 1 sigma
; @$ E! o' p" l' `589512 RF component snap is 'too clever'
: t5 r& n: l! W1 V. f% `590246 CIS to Allegro flow to include or ignore constraints same as HDL to Allegro
8 l+ d& l9 M: p& x7 u. z: n+ ^591306 Suppress RF edit window when changing RF Element properties / k+ {* J. z2 S6 ^- ~4 ]- N2 Q
591318 Use RF setup values or retain changed values in RF Element forms 1 j. t5 {& b) `- y- U$ E
591443 Temporary highlighting is lost when using the Copy command
9 Z0 L0 z' O, i. a' `9 _. o" c2 N591450 Provide a dynamic tapering option to RF PCB Route
5 g: V5 v, ^! `- Y591489 Would like to suppress RF Snap windowing around the user pick automatically 5 V. h! E5 [7 M' w
591812 Provide move options for the RF Snap command
1 t U0 q8 U# q! ^" z591817 Provide easy group and element ID in repackage form 1 J. F! m" B6 S+ S" a* z% z- e
591825 Quickplace for RF Elements
% Y2 I4 x% |, \ u+ _591865 Request for more information on 'Other' Netlist formats
4 j) C2 R9 b7 E# n j# r( ?0 W596392 Publish PDF needs improved error messages for missing installation. 3 T! q6 u# \3 _0 q8 d+ [$ S
596555 Request alias symbols documentation to include and clarify when necessary to rotate 180
& ]& l: q4 \- ^2 A; }6 Gdegrees ( m9 w. s C7 q; [* u/ `/ n4 i, u
596843 Cannot do global search after importing read-only schematic block 6 F/ e' m1 H* `8 ]7 Z8 e
597808 Option to increase the default thickness of all traces in Probe 3 Z6 ~8 w7 u, Q& g9 n7 |8 J/ C3 Y
599499 Plotting from within Allegro does not find path to stipple file
- h( |* @6 @( _1 \! Y) v; @4 n5 u604125 Manufacture>Create Bond finger Soldermask.
$ j+ @! Q" R7 t$ X `2 I& Z2 H605023 Need rats by layer function for Free Viewer 1 G" d O& R2 X
605112 Dies should not be counted as conductor layers in Design Summary Report of SiP
( q" Y, M+ D3 y( w605373 importing and Exporting BondWires , M; u, i# j7 ^/ O' ]
609035 Voltage_bus part - Make pin number invisible
3 C$ d: _* f4 h2 g5 ~609561 Enhance Circuit Replicate to support coppers shapes connect lines and vias
- s6 t* p; p' R& l8 j& y610934 Retain user input values in RF PCB forms
8 X' Q1 b; x1 z612008 Mirror Rules need to be documented for axlTransformObject. 8 k7 r* v$ F) M7 f; C) Z3 J
613639 Update Documentation for "split_inst_name" property. 9 n0 G$ E' \% n5 x# b: Z/ s. {
614345 Email facility for Design partition on Solaris does not work $ f1 R# G5 @% B5 I
615139 option DMFACTOR documentation missing in pspcref.pdf
/ K8 l- I9 p/ G: W% \8 S615374 Retain Soldermask Thickness value in 3D Viewer Options 6 p% N1 S* }5 ~! G+ T$ _
615850 Auto Setup should honor device setup parameters if component value is null
& D# m& z3 t3 i$ d& G9 G615988 PDV WHen importing from Mentor does the browser not remember the last location of
3 S0 y4 U0 ]+ y( timport
8 O! `+ O! @ F! Q) [616529 15.7 Design Entry HDL fails with Out of Memory message 0 m. g [# G" L, f7 E/ P
616873 Uppercase characters in design name error should be improved . |4 p+ z% F0 W8 o+ ]9 }1 f
617976 Enhancement for a way to sort user subclass in define subclass form & D. k& s( N h) o
620289 Server 2003 support information in pcbsystemreqs.pdf : J) P: e( l( S, C# g
620303 Enhancement: Shortcut key for "Select Entire Net"
& ?* h2 c- M9 h, F- y, j8 F621054 Renamed net in netlist isolates components from the rest of the net.
, w- t; b* t, g0 t; w3 b( a621955 Offset Via Generator utility should show a warning message if vias are already present.
% ?/ Z- C6 s1 D% f622203 Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar
2 H! K G0 `, t) [! B; Tcommands
, z! r8 c/ I A6 {5 H" ^9 l3 @# I623218 display pin names associated with a net in net Properties . m% d, K$ n9 M# r; m
623908 Mirror Symbols while dynamically moving enhancement & A7 k- q* H! K) K3 U6 f
624817 Display padstack name in data tips when hovering over Pad-stack
! J/ [) |) D+ J8 k1 ^625733 In Netlist Report they are requesting square bracket vs angle bracket
4 V; ?* P5 I+ e p p+ {626605 Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB
$ x, v; a! u$ o9 K: \; VXL and PCB GXL * n. n7 U; U0 A! ~; f$ F5 h6 e
626673 16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows
3 p4 |4 W; k' b" @, Q* lrotation and allows move but , t' s# W, F! _1 X
629008 enhancements for find command ' p1 t! ~- T3 n, L4 Q
629548 Request an Option in Create Plating Bar where it may be directed to a different Subclass 630949 DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire . l1 R( w! `0 ~ k3 f3 g5 P, z( V- Y
profile" % H4 g0 Q# w4 U% \
630955 SCM does not see design difference after update of fixed die/BGA in cdnsip
- Z. ~/ |% f4 w! O630973 SCM should see the net assignment made in CDNSIP for Power and Ground pins 2 b% M# w$ a$ y( K1 m5 f8 S
631609 Clarify how to generate a cref.dat file in Cadence Help
# i/ V: Q" U* D; B" i631697 Want to degass many shapes in succession with custom parameters
/ Q9 p/ A, X' A, k' c0 K632754 pspPN and lib_list should reflect location of new models in 16.2 ) t0 S$ Q3 s3 L8 b
633440 Sensitivity not varying components correctly
& {. B Z! {! D633842 Add note to docs regarding padstack quickview 9 t/ }1 f/ ?! M. K! D
634350 Enhancement suggestions for pop up info boxes.
( O& h2 s+ U: B: X% d8 B634877 Export netlist with properties changes scope from global to local
! ]$ k W* l" n+ G f635118 SKILL variable to obtain list of Classes and user defined subclasses in a database " g2 G. u4 N: P8 _! U ]! c8 B) m
635233 Place hierarchical pin tool tip 9 Z* O: f& k' n* m
635543 Any command to get the current line/lock type information?
( P9 V; z0 k2 K6 r7 J8 W* b3 c0 s0 v635579 Enhancement for Structured format in parameter file 1 S, f/ R5 {9 `3 K7 W$ J5 _0 f
636930 Die Export option to create symbol either from schematic or layout
$ S: e1 c- ]$ b) Z L% `1 Q- x" u637195 Allow for SKill access to backdrill info on padstacks
# W1 q( z/ K" F637768 Enhancement to assign different colors to different net based on a unique property
5 A# J/ ~4 x1 [; {2 W7 ^. [638455 Enhancement: Add some details regarding nomd.lib a. b7 A5 [) l$ k
638581 ENH - Press ESC button Spreadsheet window disappear
4 e, a @1 \, t638622 Add note to CM Spacing Domain Region worksheets regarding shape2element clearance
) [0 }8 j, S- e638910 Enhancement to sort the list of available vias alphabetically in the via list ?
! [8 V b0 Q4 P5 K3 F; A7 Z/ n% E$ ?639630 Does the Net_Short property work with Modules? 1 V: J: o+ _2 @5 O8 _$ z. b
640262 Request object membership count in the status line and forms of CM. # V, @8 M! p- N4 P; `3 X+ b" n
640280 Provide resizable windows in CM and other apps
v' a" z! A: v7 m640668 File>Change Editor needs ability to go from GXL to Performance L or Design L. / L$ g- d6 p- g
642095 Ability to disable the Pop-Up description of elements
+ ^2 h5 s2 P$ y$ g642298 ENH: For license checkout detailed message
- J$ Z, S. n9 I5 W/ a, I0 O/ E642422 After Copy parameters from one part to other in partmanager forgets previously highlighted - ]8 [; J. Q$ k+ }
line % ?& d5 ]1 u. C
642865 Allow format of hyperlinks in ptf files
3 D+ G! [2 c) z$ z- d, i0 W642894 ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help
# w, `& T5 c! b643381 Add an option to ts2dml to allow user specified port ordering.
$ I& ]! j" x5 m, f643390 Request for a switch or button that would allow Properties to be maintained during a shape
3 ^7 ? Y0 S: v2 ]3 S3 H# \1 Qmerge
1 b" e5 g ?6 t9 r" ]643625 Bond Wire export to DXF does not support WYSWYG ! n. Z* h' _8 p/ E5 ]4 q$ ]/ O& u* @
643790 Include Associated Components in the Verilog netlist
6 j+ d3 w& f% o3 `: k644216 Store Filter Row Data and Units Of Measurement in site-specific file.
$ P8 V4 \, @! e1 s644248 Need a better solution to identify and handle unstuffed components
1 ]; N+ w% W$ d% p9 F3 ^644350 Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
3 T7 y$ _, E; c7 e; Z8 {646662 Enhancement to add feature to toggle on/off inter communication tool from within PCB 5 D1 \, O0 V* p$ j' M$ V" I
Editor when using DE CIS.
5 c# C4 C! d& b z8 X. u# l! h: t5 u646981 about the treatment of NO_GLOSS property in Missing Fillets Report
/ u ]' N6 Q) \/ j647480 global setting for adrc settings in sip via techfile
& | h# ?/ u# C" M: ]( [647617 Degassing not suppressing shapes less than size specified
/ u0 F6 D* L% X2 U* p648210 Request for Working Layer (WL) model in all tier Allegro tools.. : D. [7 E) Z/ @
648218 must delete keyword "multiwire" from Doc
; d4 Y1 @* W8 g; M648533 The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented
4 J2 z" P1 t. X648801 Stream Out issue for SPACER 8 R# i$ l1 I, d; u3 e- P% X# ~8 o) s
648930 If two PPT option set names match a given component which one will be used?
* ~5 j, [' o. s* a/ @ ?' u. N649603 about spara import
4 A' ?# s6 h5 m' J' f9 f649607 Management of SiP Technology File and Project Information
, }3 Z# X- B& |% w# q& B* P649610 Management of Part Table (PTF) Files 2 r3 `$ |6 b4 j6 l
649613 Management of Library Lists
+ J' ]8 m3 z( d/ F( H: J4 a) e9 f0 y651684 documentation improvement request on cross-probing in Capture to Allegro to Constraint / V0 ~' h" ^ C8 A0 ?
Manager
( h& ]0 k* A5 b. A2 E% [7 {652335 Tooltips clutter Place Part dialog.Option to switch it OF and ON
, M5 ] y' g" ~" h0 h4 C0 X652511 Unplace Component command
" b) E A0 V+ U9 Z) i4 y! [6 @& { ?652547 Description of ForceDBArg1 should be added to PSpice Users guide 652554 Enhancement request for Allegro to check the vias used to the allowable vias defined in
# x4 F9 F: S$ `* R. V) [" econstraint manager ' U! Z! S! b6 |* i
652939 Is there a way to predefine the values for Sample Start Height and Sample Start Length in
$ R, Q$ Z* X9 T: [$ ^Wire Profile Editor?
@& U0 c2 S- t8 K, n& j5 ?. x653027 Explicit RMB "Done" option is required in Part Developer symbol editor when editing text
6 d1 S! G- ?8 |+ n9 r* g653359 Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using
: F8 h/ ^% j' `0 l, l0 Nthe section command : E1 b6 k* V. B0 e- ` m5 N, s
653420 Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined
/ A4 [% k$ |$ ~% [minimum constraint value
8 X0 C4 x! y* {8 k- Z653471 Request for Die Text In Wizard option to Flip the DIE coordinates
* m2 X: k" ^! b; n1 }4 m- P, U6 ~* @# ]; y653825 sigxp_tier was not reset when installing a new product suite * M5 [3 b1 T3 E; P3 g, v
653902 Enhancement: Print Option? setting in Capture.ini file & r8 ^# p1 d5 H( s. P0 a
657180 Enhancement: Tooltip for DRC markers + d3 @( j+ M; u5 w4 p1 Y
657187 SI model delete enhancement , ]7 u' `+ H) q4 R, Z
657189 SI Model assign enhancement #2
* G: |" S% u* a, `+ g8 z* s! r657501 Negative planes doesn't match with Film View
1 l1 |. n% x' v659543 Need a Report to show which Die Pins have no bond wire attached " P! |# {. p4 t$ S" @
659661 Function needs for setting the rotation angle in finger by group.
; ^7 @. ]- F* y: O, N; }1 {5 j661477 Color192 window sections to be resizable 5 Y) c# C/ |' `' s
662215 Please add the function of renaming net by batch command. 1 D- U7 R! S4 w" n% q
662325 Skill code example axlDBGetProperties.txt not correct " S9 J S4 w* e3 \7 i
662982 When you edit shape, ministat should always enable shape % ^% h1 J3 z1 L4 C7 G/ V
663260 Enhancement: ALG0051 message should be more specific
1 P! p- r/ C9 G' I663754 Enhancement to create Device file when saving dra file on opening another design * v- m( k6 j8 |9 d* k/ j
664240 Add CNVPATH in User Preferences to place default CNV files
0 \9 c: e" L2 G8 d6 ]665798 163BETA - provide graphical examples to show result of Flexible Shape Editor actions & Q7 J+ C) P$ {2 H" t1 o+ d
666186 Enhancement FishEye functionality in Variant View Mode
9 B! L' |2 j! C666768 Temporary graphics for modules / groups do not reflect true size
2 r$ j, T( V7 ]4 Z- |) n/ D666775 Update microvia to microvia DRC markings to avoid upper and lower case confusion ) A3 w! l7 U) x" ^0 w
667773 Request for ability to set grid definition by entering simple formula " T0 q2 K9 M! m* Q
668110 Customer wants to enter the value of radius when editing routes. 8 Q; S( i' B+ C; L* F: q* d) U5 E
669373 Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
# Y6 U. |5 c, H' ~5 T669380 Add options for ts2dml in MI 6 F% N2 p9 |3 {6 ]7 [3 h# f
669798 Add all 5 Dyn_Thermal_Con_Type property options to Via_Array. 3 G2 k; a- n# `* [* ]& Z
670775 Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public # }) Q7 F9 M- N; p# i
671194 Allegro not to crash when opening unsupported files
, ~0 M/ Q2 y0 }& t# p0 n+ O671337 Request performance improvement to access DML libraries from SigXplorer or PCB SI.
: b: g* g8 X% ], q671757 Handling of double quotes in HSPICE subckt. ( x2 y' \, t2 k* D( b: P, r' }
672930 ERROR [DRC0039] Tap may not be connected with the bus Check Entire net + J8 }" L5 e# F4 X) A# I4 M
674666 Report the wirebonds XY coordinates
- ]. ]0 `) Y. o' ]8 f675118 Cline change width command enhancement & X" W z: K) M' D' |
675151 Insert comment option for database elements 9 j! a2 j% j( u/ S+ g
675398 RF PCB setup should automatically point at the project file if Allegro is launched form a
+ C1 e$ |7 | q. v- v- bproject manager 0 }4 W( ^1 b4 A' F
675551 schematic to sip layout fail
0 z# f# ^, B s {( y9 j5 `0 k* @ d5 i676814 Signal Library command with Allegro performance license.
; A3 u$ ^6 I* G% w7 c676906 Add switch -regenerate_xnets to the dbdoctor dUI " M2 c4 u, _0 r: J1 \& v% Y7 M3 ?
677983 about setting of ibis2signoise option "-d" as default 3 r7 o! I% u7 }5 f9 a
678036 Request for a Physical design compare. % _. J- G7 Q% t& p
678798 Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
]) N5 D' o) f- R- k4 J679926 Testprep fails with no route keepin. Message in testprep.log ambigious at best
9 K% ]4 g; Z" l" W/ W680586 Explanation of functions and macros in online help 8 s% w+ s5 p) W+ k4 W3 V0 ?( d+ `) k
682098 Color, font, Text Label in PSpice Probe Window
" H* _4 Y# l: L: K$ @+ i4 g682695 Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs / O' v0 k. z5 f5 o
rephrased 3 J$ F4 i9 A3 n$ p; M
682865 When using PTC format IDF files don't use forward slashes.
! ~1 D `6 o% E- _684409 Add info for non availability of SIGXP on OrCAD Demo version
; k" E4 D% H$ c* G- ^. q684713 pin_count view needed for packages
7 H- j9 K2 r% T! l684796 do not delete all vias with DRC for via array 686103 Replace vias evenly spaced apart
5 F) E) X; s/ V$ a686112 Add Connect and Slide keeps cline length
* T2 e$ ~- E, K+ D$ Y686122 Select objects by polygon
! F0 ]4 v7 h4 `" d3 @687155 License for batch signoise command
, q! v9 ^* D5 k) x687187 BGA Full stagger matrix wizard generation 9 L, K* a+ ]! I+ a8 e5 G
687201 Improvement in Find feature
! h$ M5 ?1 n5 N/ p6 j687685 Documentation of new properties in Variables block + @$ c8 O* d6 ?
688047 Include blank space in pin name as the illegal character in PDV user guide ) c' N; c9 O. C8 E
688830 renaming feature discrete library translator 7 r4 b$ H% L0 _
689720 Need the ability to re-center Vis's in center of Pins when a Die is changed. % w9 U$ X* Z1 }( T4 l9 \
695957 master.tag generated from the table design needs to contain the verilog representation of the # j( Y9 L! y, `6 y: h( H9 Q
sch.
& J7 F$ w0 g2 _' h: x: }% ^& P1 e o696661 Add ability in Offset Via Generator to add vias per a given Net " f1 I2 i" Q) |8 k6 Q
696812 provide description for axlCnsPurgeAll() skill function in doc
# K! p* F: I; _) x* ?697824 Components not installed of variant design should not be extracted into SigXplorer.
' _# I6 p' E( ?4 V5 [" J0 i698097 Color Dialog form (color192) does not resize correctly ! |, e7 d$ N8 K; W, Y
700262 Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the
' y* b2 l- x# _! A. k) XAllegro PCB SI -L tool) ) i! z' q; H2 d$ k* \
700712 Defined pin locations are not used when using Die Text-in Wizard with default option
+ l/ q2 g5 t8 X! G% ZCenter pins on symbol origin
) G) J# Q' Y5 `- N7 U701514 axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap" " U1 i; ~2 ~, b4 d. H8 w9 U; m
701810 Document what all database sources are supported by Capture CIS " |- w K) N6 T
702190 Request support of Windows 2008 Server Editions. * Z6 ]' M$ J0 f3 @; r- t3 Y
702613 Request SaveRefdesModelAssignments support the include original model path option.
3 v& q" C) \) k, ` G703905 Need Hot Fix number Info on Help >> About ; o* A) c0 H6 W1 s- u- J
704594 Update symbol removes the text present on Package_Geometry/Silkscreen
3 Z t# U& d+ l/ L6 n704899 Split Bundle Methodology Should Include a Next Function ' t5 d- p4 e/ h( [, H
704904 via matrix should be available in Allegro L and OrCAD PCB Designer
# U0 V% e$ Z! x- J705601 Please make listnindex a public Skill command # X7 l9 `% D9 Y; X" V3 |
705615 During Updating Symbol the text location and size are changed so Reset Text location is
6 r6 G7 q% V2 I% \! {0 W% S1 Yconfusing & U% z% W) N( @8 b; B5 c2 X a
706165 idf import fails to expand drawing enough to accept text.
, o; H5 U, U+ y/ V) l706457 Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
, ] [3 o& L0 ^706463 Add optional Character in the starting of each line of the file created by axlLogHeader
6 _- D3 z( z! h$ |: I* J2 l706787 Fillet should remain when user slide the segment far from pin/via. " _' n: k$ p: b( r8 N6 c
709119 Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via ' k. U! a$ [% t) h) l: `' s. x
Generator
4 F b* A9 d+ _ e711837 remove the comma from the image of grid value separator
+ h3 d/ m/ A" q8 W8 H714840 Enhancement: Anti-etch can be recognized as Void element.
( Z: a) S+ A9 j& t1 g+ r8 q715454 Option to configure Design Entry HDL for Cadence Help
3 Q a( b* C; M e715713 Enhancement for Wire Short Check during move feature ) v( f) E$ |) Y* r- O; K5 Q
716671 About the log file of the na2 interface. # r f; A0 i) J$ D4 s, ^
717722 Pad designer File > save as should have recent file name in file field + c2 L, A m! M& F
718431 Enhancement request to have DRC checks on negative layers.
3 |- X7 F* Q$ x4 Z# X719050 Log file should contain username date and time while creating or saving .DRA file
# W/ t T* o% J' l0 ?5 p B719514 Request length column be added to the Dangling Line Report : U2 R% o7 |7 i" J9 |7 H& c+ D0 P
720297 about "rip up thermal-relief clines" % h* q4 f# T3 I+ u
722346 DRC checks for mismatches in labeling Net O: \& d+ J* m
723661 Add *.pad in the File of type drop down menu when executing QVUpdate
8 d+ {0 v. X( I! h5 O" I+ z D724832 Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 -
0 e9 o5 c" b. U" m5 l% E1 O8 fnil) $ }/ F8 B- O+ A$ j% M" N6 g
726057 Request incremental DRC update when enabling DFA constraints.
! X- e( `. ~% Z, j5 w# b$ c% a8 }728908 Add Color View Save and Load in Symbol Editor ; u- ?3 m' Y- ` Y% @) |$ {4 ?
729947 User would like a metal usage report
: {( {" D! O2 S- ]9 R( ~
! i' K% W; o) D2 A x' Z5 ~ 8 }& F, E/ h2 i
% s2 e$ C2 R3 ~: [. g1 k! M/ B9 N
Bug CCRs: ' I1 z' S! S: p
, c" N( F4 S0 g3 d/ o- ]CCR ID Description
. z: X0 X" m( J' B$ o% X10116 Add Intersheet references does not work in Complex Hierarchy
/ n$ p- U# R! P, E+ X( L11833 Junction not automatically placed when it should be. 1 y: a! x9 B2 L& Q: U
16310 Simple hierarchy, intersheet refs not refering to H-block
- L3 @) U7 A6 K) v19343 Request for intersheet reference to show grid reference zone
) F D' T: D) ]9 t+ f/ k22424 Intersheet refs wont work on imported off-page connectors 6 N+ _7 ]1 W: a# T" D7 C
34275 Ibis2signoise fails with legal characters in file 9 N9 z$ I2 B- l& O% w1 F& j# V
85735 Cref annotations of the P_ID+00 Bus were missing
1 k. N4 x6 Q4 H2 E8 x( \ Y/ D118279 PSpice command line options problem 4 H% h* m. d3 ?3 D
134692 DDB_WARN: POWER_GROUP prop. not allowed wrongly coming + k# }9 K% N. B# O- B
136260 Problem with netlisting the design in PSpice
( {- D F+ I# k199343 Stackup-Aware SigXplorer
1 a: j! M+ f' L; d207620 Part in MISC2.OLB has incorrect pin out ( y: t& T: W3 Z3 j
270347 Changes to AXL SKILL must be Documented.
* x$ e1 J, w3 U, i) r2 x8 C283839 lm117 dropout voltage is too large , B; B$ R7 [( Q, h/ U6 E
296826 Variant view displays library property % U+ n; N$ u/ l
299384 Part rotation resets the text to default position
! ]% Z' r4 M0 g' L" i$ Q* ]328647 Replace Cache takes time for network libraries
: V4 M; i+ K$ q- A8 }340323 Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
. @, B, r- D% b) ?7 A341035 Dynamic shape fails to fill in design that has cline arcs
! y6 X; u- N- a! |1 G# X- z390692 Via not getting transferred through the Area Constraint from Allegro to Specctra ( x% K* Z! P* p) |( X
405611 Environment variable for SIGNAL_INSTALL_DIR is resolved.
3 `+ p4 w& [6 v# l" F! k$ f428261 spaces at end of pin name Could not create new pin inst library correction utility
K* b, q7 T+ x h2 w4 h+ X436908 The color dialog window will loose the vertical scroll bar after being minimized.
s! L& t: b$ J$ q2 V437369 Menu selection of Export > Libraries fails to issue the dlib command.
: m K' \9 M5 J6 p; j U) q462783 Busname is too long + a: g1 b$ L6 T2 m* m& t
495671 Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE / } `6 }9 y6 Y
Props. 4 j+ ~& C) I' b
509393 NC drill legend copies null nc_param.txt to current dir. 2 J Y% Q. X: c2 l8 d
512809 Window Prt.part.ptf shrinks by 30% and I have to maximize it.
( h4 M* W! u6 h* _" W520802 Global Navigate Zoom to Object needs to remember last setting 5 a2 d" U4 e) E& H8 G- s
528686 During text edit the cursor overlaps a letter rather than in between 6 ]" L a: @$ i
531555 The diode BAV99 from library works inverted in compare with the graphical 4 ^8 W% _: Y- q" z9 w( P
representation. 7 q a3 l8 M, m% P) [
532603 Specifying TC1 and TC2 properties does not seem to have effect + f: s/ S4 | Q8 }( J: a: G, S6 u8 ^% S
547339 CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor
% I3 ?9 d2 p$ \548143 Dynamic shape on Etch TOP will not void properly.
/ o, _) D/ U) L6 ~, g4 z8 q% l550657 Importing registries do not setup printers from MWcontrol
6 f5 B+ x6 t& Z2 N) ~552227 about die export padstack layer mapping
, [ i' k' R, o, _8 U3 h8 L$ m553035 Cref Synonym and Netsbypage reports do not match netlist ) c* }* z* E9 k" E7 D' k
557660 Incorrect value for I_sinusoidal of pspice_elem
6 r: O; ~- w$ V) \* i/ L558164 All variants are affected by function regardless of being called for / {+ q; p/ G8 {! j) V. G8 z$ v
558692 Memory leak problem in loading marker files 2 _9 M) \ Y. t
565681 Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it " a% v" g4 c/ P: X
should.
% R$ @" z$ S3 ~9 ?# f6 r567606 PDV selecting pins in symbol editor shows pins off grid during move 0 r a; v( J" ~5 k( P" x
568049 Genview crashes ; \6 i b c* ^' F% q+ }# Z3 |" w
575353 Large box displayed with place manual-h and no RefDes variable set
9 k7 l d! l( V G0 ^9 R/ O1 K581848 not able to edit Padstack Boundary $ \- c; c3 u& { s/ j
591847 Add Intersheet References does not work on simple H design.
! s% b" W: X3 v, s4 E592381 Physical Min/Max line width values not check on internal rows or forms.
- [+ a2 I1 ~/ y; E7 ^/ \593076 Cannot redisplay an invisible OFFPAGE connector's name 9 k' ~ V! V# }, U$ h$ e3 N
598038 Detail button of Markers window with 16.01 2 J! ^1 S$ Z7 Z, [* ~
600967 wrong order of nodes in PSpiceTemplate for part AD8138/AD ' w1 J3 }" W3 E0 k
601415 Allegro Design Entry Tutorial corrections. 2 Z2 b# D) E3 l
601531 When using the place manual command and rotating part a ghost image is left behind 603181 Formula to calculate the Actual Temperature for Smoke is incorrect. # y [! x! ]: M2 X
604965 need to document how tcl cmd addComponent handles property values with spaces / D) p" z) c2 C
605843 Aliased nets do not fully dehighlight when next net is highlighted
! D4 }* B- _/ w( c" e1 o2 ^% _606493 Targeted nets are not remaining targets 9 V) _ D+ ~+ O+ Y
608150 TestPrep generation is creating DRC errors
* q! Z% l5 n1 s608787 Missing Constraints Report + H$ X+ e( }6 s. g3 S+ {. `
608942 PDF Publisher output misaligns text in tables ! Z& {1 \- d c* |9 m( w* [
612511 Error in Flow Tutorial regarding checking default user units
- v% W& o# F b( L* h' q612982 VLIM model giving error that line is too long ! q u7 w: Q# |( k) }; B
613194 Adding wire bonds with current selection does not yield DRC's, mismatching Allow
5 F% z& C1 V9 g9 A1 zDRC violations option. ( x; m Z, r: w2 v6 G& i
613738 Variant BOM report lists identical parts in separate lines due to POWER_GROUP : Q$ r7 s. |" C; G7 q7 H
617146 Symbol fails to place through Component Browser
8 f. T6 w, N$ Z3 c# k% b) X3 v; p617327 Change root operation results in SCM crash
* }6 Z! J) t4 ]) B4 _0 X- t+ F) j617784 Trying to open page 2 of the design Capture crashes
' x. a) i, F7 V3 K) |618150 Property Editor Functionality 9 h( |2 L' K' ^% T
618617 Enabling strokes requires checking/unchecking options boxes
( c5 }# n' z/ T" n' |' d3 y618771 PDV error SPLBPD-382 when importing from APD.
+ U+ {& y/ w6 w$ y619053 Diff Pair problem with creating them in DEHDL.
/ u7 d+ K' w' V, j; M619849 Hierarchical Blocks Loosing reference
, Y9 g, q9 s- A, V# x+ o620001 Measurement's Maximum range calculation is not correct 5 `7 }$ t% N/ e+ F! A( `
620343 Bogus error during schematic write
5 C y1 k, i& N8 O* m, v, K) Z620826 Changing the units of dimensions does not work
' H/ w6 z( d4 y/ G+ m621072 Capture CIS Crash while configuring Database
4 v% A) S+ z- y a621163 Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire
* {, n. m9 `1 y% ^to bondfinger optical short
6 y5 T% F/ m$ e6 E V9 n+ D% L622263 Drill Customization sort order for oval oblong slots should account for Size Y
& u! L1 `/ e2 T, a622583 Allegro produces erroneous error msg - symbol not found when the placebound is too
7 n8 c T( N# Z% l+ t, `% blarge for the board. 0 x. n) `0 A0 @% _$ n8 P4 p
622692 Why is VGSR negative for N-channel MOSFETs , O. d0 U8 g) f$ `
624378 Device file content conflict
) A F' C% T6 q0 V5 w' U# C1 i# l624492 Model Editor finds the wrong model definition for BAV99 2 z) e% @, a; ^( u. b
625462 Symbol pins Property are lost when once stretched 5 J( q9 F) o9 G1 Z7 q0 g0 q+ l! \
625519 hspice_mt is not used in Channel Analysis simulation 0 o- N; G& }( q7 s+ k
626674 Allegro CDS_SITE setting don't appear to match documentation c7 a) V& o. M$ g
627018 Find Net in instance mode displays twice 4 ^/ j% N, y+ W' s
627864 EDIF c2esch crashes ( x. Z% _; S, ^ ~0 }, a
628077 Degas not voiding correctly - }4 r1 [1 r; X& @( r
628265 no "Unused Blind/Buried Via"Report in APD products 6 X3 G, c; B) |/ d+ i
628845 Markers> Packager menu is unselectable even after pxl.mkr is created.
8 q4 a5 Q' e" Q4 O9 o( ~* O631344 Mouse Wheel Scroll misses the "along with the Control Button"
! r- \! E* G! `( c631792 Design Compare not working for OrCAD PCB Designer.
% T7 n; I- x/ g5 t! G9 M9 X631910 Capture hangs when working with search option ) D) a6 N6 E, ~+ g! ~$ ^# E
633084 controlfile for OrCAD installation does not work with PO100E and PO200E
/ X1 v, o# ?" v6 u633086 Generate Part for Pspice Model is incorrect 0 e( l, z7 S6 `6 w$ E( M1 j0 X3 R
633130 The Verilog netlis is wrong 6 w8 V. P/ C! v" F/ s% \
633223 Running skill from a HDL script causes segmentation fault.
4 C4 T& i& |. N' c, ]; l/ {" K633473 INPUT_SCRIPT inconsistency when removed from .cpm file 2 |" R5 j- w* U! [# E% ]
634075 draw_etch_outline doesn't work for circular shape/arcs 2 y/ E0 i1 }' L! t6 G# Y [
635779 Allegro OpenGL distorting text at certain zoom levels , Y/ b F3 O9 v$ Q# Y6 t- b
636156 Unable to convert SDT Schematic to Capture Design
& |$ |, H, v$ i; O) H$ v) H636215 Allegro documentation for Export Parameters is incorrect
$ Z8 E& H' b: a+ b636585 Rotating components in Capture reset property position 9 Q1 x$ o3 J8 C9 p( v
636688 Signal Model Assignment UI and Find filter association is broken
9 U3 L& R: ]1 B$ ?5 ^636819 Documentation wrongly indicates that DFA Analysis in unavailable in XL + Z( t% a a0 v) L
637379 No column for ROOM shown in Constraint Manager
U2 |+ z, ]- m3 C4 C638140 Intersheet References not offsetting relative to Port 6 J, Z/ V# Q: K
638670 Testprep parameters - padstack selections - Bottom Side replacement text not entirely , [1 y3 Y9 C8 p7 ]0 c0 B
visible. 638987 Change command hangs on customer?s database
6 d* B$ V6 ^# E, \& J+ J639052 Database Objects Preventing Layer From Being Deleted report fails to run * i) K/ o6 K5 d2 \3 S
639685 Capture crash while deleting a Hierarchical Port from the Design 2 c0 E, i" L% ~0 ^
639698 HOME variable defined with %USERNAME% doesn't use value of variable. 8 e! q2 t) [& A' Z- }3 k& `& [6 H+ S- U
639829 After setting Zoom key(F10) to a new alias Tool Tip is missing the key number
& u& @3 S# \# m s2 X P7 f5 Q640127 Correct IDF documentation regarding UNOWNED objects + z1 Y. x5 g X+ ^0 r! p: Z
640293 performance issues with scm and large pin count devices 3 i) }$ D) i; E
640314 The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
2 F. D7 ~! y6 Z5 H641503 Stop running the VAN check on a PLUMBING body symbol in PDV
A1 U8 U3 C0 R2 a* m2 C( S641676 Incorrect link to assign refdes help ' j, k6 U+ Y9 \ e
642053 Drag Connected Objects icon is always display as on
3 L. y0 w# P! w( u3 q2 O5 A1 s' P642299 Switch the windows mode by set command : z. g, L# ]' R( x3 J8 E4 s
642436 Save As symbol in part editor is not working fine
1 H0 W6 e/ V6 R- J6 X7 C8 w642713 Materials are not refreshed when material name have only numbers. : j% E5 {: w0 a& H8 Y! y
642873 Dynamic shapes out of date message refers to Setup Drawing Options
+ T% [: d4 w4 ~& \1 m643721 Attributes with Null values in symbol.css files are removed when saved in PDV 7 s/ T% C/ f C5 D4 M$ _; r" q
643949 Can not create Region-Class-Class for same net class. % S$ @$ V, u+ q( U q
644016 APD crashes when creating a tile from LEF file ) p) @# M. ?3 G8 t
644733 Import reference text file gives incorrect results 2 U6 l+ B7 n& \
644879 Change forms to enforce naming of lib.defs file
* H0 V) {; S. {* N! r; X645046 SG1525A PWM model is reporting unmodel pins and producing incorrect results
0 a: u3 N. c% p) H" }8 @% b645427 The save button is not enabled on changing the line width ! r o6 a" Y8 y/ u7 [# C/ N
645996 con2con fails to parse ppt file correctly + {" x6 V+ Y& ~5 B
646175 Please modify the limit length of "Allegro PCB Editor Limits" correctly. , t3 y8 g. G. j' X3 N' @
647555 Drill Customization text Non-standard Drill is not readable.
( F0 k X% X9 ^8 n: o# ]647628 Annotate Type should be removed from PPT Option set files and documentation
3 L: w2 `* d" A) |/ g' j3 y648443 Launching SCM without a license is not reported in debug.log 3 y2 U2 f, u( ~
649166 Capture CIS crashes doing Place Database Part with non-admin User rights
$ O+ R: u# r! ?! a649222 Silent install adds extra License Server to CDS_LIC_FILE on the client " L4 s5 i; l" q, j
649570 PSpice COM Wrapper error while opening Capture PSpice project.
) h6 I7 E" X, X, ]: j: a' A650558 Die Pad layer changed after refresh padstack
7 R3 N) D$ x3 c650997 Incorrect Pin Shape in CIS Explorer Footprint window
/ q0 }' R9 Y8 {) M) k651000 "Wire length over parent die" violation is incorrect.
: q% a, s1 ?* W4 N' {651153 Results for imported CSV inconsistent in PDV
% x% o! o' P7 F* y5 W6 B651521 Resizing the display color visibility dialog box corrupts the display
q+ x3 n% j& g3 N; {1 d/ k651526 Parts are missing in a advance analysis library list document and font size issue 0 _& p% Y8 ] l& _/ D9 J6 Z
651532 Scroll bars disappear after minimizing the color visibility form c- u& {) I# p/ p( }/ w v
652050 Append waveform does not work in 16.2 for .dat files created in previous release with
4 q7 g% Y" n5 D9 U8 bimport text format ! O2 e! c: b7 K: Z( b
652904 significantly low performance issues when using edit interface to delete ports of block 0 ]8 f/ C* P' I8 y* ]
653067 Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#?
+ O5 g- U) {! P- j: s3 J& H( @$ d653784 Off-page connector name change to internal starting like "I12345555" 2 B& E# E( c6 L' O @4 E5 `
654580 Save As should update lib.defs without executing the edit die operation
8 x( A3 E) F9 \+ a& O. T1 w7 x656282 BGA Generator adds outline and RefDes to wrong subclass
) v6 L& L5 T3 e656723 visibility of clines in 3d viewer needs ALL instead of just CON field in layers ) N" u' [* e( Z% V+ g* U% s
657836 Text crop on User Preferences Editor form ( [, P5 o- K8 u( P4 x
658347 Rule Continuous Soldermask Coverage Check should not work on Cline Segments 7 ?, z5 e& Z# h* D- o+ ~( \5 q
659437 Move group fails to display anything with Open GL enabled. # q1 J0 @) w1 e& j: ~; i3 l. E
660937 Import techfile fails with etch on layer yet layer has no etch
+ m+ W: i) z- V7 q0 e5 n661369 Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
* a, C9 c9 g2 U5 _661754 Hyperlink publish pdf to correct page but wrong grid location
% l9 L ?) r d0 i% W9 z662622 Export Physical reports error Output Layout Filename contains space $ F" [2 _ p+ T* X3 j4 I
662918 Skill code example for axlReportRegister does not work
& V! w& e4 s3 X% a# M662971 Moving Bondwires disconnect bondfingers. ' {5 `7 K# @, r$ A8 e
663088 Cannot add connect to a C-line in Etch Edit Mode
3 M% f' A& \% v6 z: }663220 IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in
. q9 X2 O8 Y8 |% a9 X$ LDEHDL
* f) |6 \' K) \2 ? N663726 ?Each? menu under RefDes is missing in BOM HDL user guide
* f; M! H: Z: \' j1 _% w664764 Material changes when layer type is changed 664900 Project manager User Preferences Editor form has text crop. ' i8 u) @' Y2 `) E7 Q
665236 Unable to import a Quartus-II version 9.0 pin file. 2 _1 t1 m7 i. V0 l1 i) n7 |
665389 Spread between voids not working for customer design $ I4 ~" r5 r9 j3 H: Y' W9 K2 c1 G
665413 In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
2 H0 ~3 v+ m9 W. b665451 Import - Part logic - information popup window has incorrect user preferences Editor
2 |; s. \5 ^$ P" H: N: X. F$ tCategory
5 L7 f8 K' }. M" }; q; b- J/ g; V" x5 |665661 Wirebond Die Escape Generator failed to generate Clines 0 q9 L" j# [& v& I; B) y
666099 Mandating at least one symbol with sizable pins for using size..1(not for size-1..0)
0 S, C% U% [, u4 Y* E* C' CSPLBPD-310/SPLBPD-309 on reload 4 |% u. m, I$ v, o) @7 [
666667 Relational Table View Browsing Issue
# o6 z1 j( y; `/ W; z0 A, T667286 import IFF No Component Shape Line Via found in IFF file. - l: A' `' Z' i* r, d; w O
667751 db(v(out)) and vdb(out) gives different results for FFT ^3 ]" U2 L1 i& `5 P
668080 Improve handling of curved routes
8 ?5 \' o2 @; p( K! E668081 Capture Crash during Edit options
+ y, o' S0 o6 [8 F668393 Dielectric constant or loss tangent values do not update when changing conductor 3 }, U7 [9 \4 i+ W1 r# Z( W/ f- L
668785 Capture not displaying variant values for Uppercase Display props 3 s) G1 r- p' \8 A& ]; l$ Q
668799 Placing specific part crashes OrCAD Capture
" @" h8 I/ F* `6 N) |8 i* H668876 Text on the Add button is crop on the Edit via list form.
1 x7 R% H2 L* P. F# ^$ v668892 Incorrect Parallel Length data in parallelism report - U+ g. H. G# N
669206 Parallelism rule causing significant performance issues during DRC update 4 r) D! G$ {& Z2 H. T0 M
669238 Unable to use permanent highlighting for groups in version 16.x ( X- R/ E4 n: H' a8 v7 e- S5 t
669323 Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated % [* i' T/ M+ ?2 j8 m& C
669336 Error in documentation of DE HDL Reference Guide 6 f6 ^. u: p6 E
670874 getVersion() function not reporting tool version
4 g8 R" s% Y1 q; t671811 Allegro extracta fails with more than 10 output files
. O+ ~, {# @+ a! ~672420 User defined property added to component instance is a function property in Allegro
' t0 f) q/ x' l( X9 i7 Y672614 translator converts the symbol "\" in the original Spice model to "[url=]\\\\[/url]"
! Y1 M, d! N: T4 ~& |$ V672615 Translator generates 6 external nodes should only have up to 5 nodes 1 e) P8 S; l, z. B# Z
672618 Translator generates statement in the dml file: Language=hspice causing Spectre run - ?* w1 e7 Q# `1 W- ]/ x5 B! i
errors
5 @7 c. L# T$ M' I! V5 ? B672715 Steam_out takes a long time and then fails but the .log file reports a successful export ' f- i n$ r# X# L& R1 f7 x
673279 Same characters are listed as both valid and invalid in naming rules.
' j0 u. Q/ T# G: j9 l673410 search by net name is finding electrical 7 A( G; S* b: m- f& K; I
674058 Incorrect Variant Report ' x% b! A0 S1 l: g! a, o( ^7 h
674291 Library Explorer fails to start and I receive a 'Runtime Error!' pop-up 1 V+ \5 o% L' r+ ^$ _/ p! K6 e
674555 If the DSN filename contains spaces, autobackup will not write any DBK files to 2 ~# p4 H) j6 n0 B( |' i8 f
675192 Adding a second BGA caused dsa_api.c to crash " \1 A) ?, @& C8 _( @& ~
675231 SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess. 6 O( [' m) ?0 E/ v9 D8 A
675562 axlWindowFit() documentation needs to be changed. * r8 t" ]# m. o
675783 SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to
7 ~! k1 r) `- [, a8 n% Nbecome unplaced from alignment option 7 i" H0 B, ~- i
676201 Cross section impedance not calculating with single license
$ q: W9 N) E1 p+ H8 ]! A676601 behavior of launch product from library manager
4 ?' }5 |! B* }# K+ |' |677582 mirror of die component on sip designs ! V& n* {. a: ~2 i
678013 Error: Symbol not found, though symbol is mapped in psmpath
H4 M5 G% }% ]3 Y" P* Z/ N4 ~9 J* F678427 repeatedly placed symbols has strange instance name
0 @& g( |; g* [; \# F678538 Why derive database does not transfer the Schematic Part property to CIS
/ h. P8 L0 \9 k* f9 W678814 Spin a temp group will not rotate the symbol 4 U! {: Z. s- {7 F( l
678851 Difference in lengths in 16.01 and 16.2
. D: j, ]' k6 m678884 dbdoctor fixes corruption and then it's reintroduced - C7 ~* f& o2 f& j' `
679224 dbdoctor states it fixes an error but the error returns 0 U0 Y- C; [ q- p' B7 g! \
679960 Capture crashes from diff pair setup menu
3 m1 {# N2 A3 c# G* i' m/ c0 I5 q. K- d680565 Capture dsn files are not properly associated during install
8 a* E; p+ n) K6 D% p+ r/ f4 ^681197 Report generator Hangs Up Allegro PCB Editor ; n" g* Q( t4 L
682135 Justification of $PN placeholders not working in 16.2 release
1 ` I3 G3 A' f6 R2 R3 _682204 Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows * h# B a0 E0 T) f1 N" a
682331 Incorrect reference to the middle mouse button. ) d1 c* D$ k: t( g% e( p" j
683146 export variant path appears wrong in output folder while two DSN are open
9 i. }3 O& V6 n0 ]% J2 [: t9 zsimultaneously 683182 DRC0037 shows incorrect Alternate Net Alias. 2 N2 s+ V: \3 \. e6 z2 j
683379 ERROR in Measurement ConversionGain_XRange
: b l% @3 p% [( M9 _% t684180 Sizable pins and vector pins cannot reside together in a component.
& N8 w! M& D7 \, i$ O3 y5 J1 p( J684661 via array created wrong results
# U3 b) s3 U1 U$ @684700 via array can not be placed on both sides of the cline
% k' r3 l; K) O/ b! |1 F684912 16.2 documentation is incorrect for axlDeleteFillet
# X( j7 P" W# _0 }9 j2 S684915 Incorrect mention of creating graphics template in the PDV user guide
6 ^4 w1 ^/ _. Z* p0 E, G. y685685 When the customer tried to merge shapes, they disappeared and do not merge. ) S8 Z5 e |# g( H
686338 ERROR #8012 Database Operation Failed with MS SQL database ( y! S, {7 I- i7 G! _3 s/ O
686560 Changing pin group property after pin swap resets pin numbers
9 r7 f- q# [0 @- q! l" s( {686736 Load property does not propagate to the associated MECH part
5 N! y$ H' N. }; d687008 ERROR 8020 after removing Place Icon % f* r. o, a3 Q5 X
687074 Part disappears when you open it
' m# D* w" _) _+ b# A' a( U7 b. ~687354 Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package 5 L$ g) u" q& N
687385 Publish PDF outputs the net name (with underscore) overlaps with wire. . s" n$ z4 c% M. |. ^- \# B
687708 Smoke deration calculations for Capacitor
( R' ]. T. ^2 |* s9 g# P687715 Getting Warning TJL will not be smoke checked
. \6 F. F& H/ o t* F& R0 d( t688606 Inconsistency in synchronization between bias display and icon
, s4 ^4 t1 q1 z: u689542 Comma in ESpice model name causes simulation failure * R! ]! h4 M9 D
690112 Ignored nets are displayed in simulated crosstalk worksheet in CM
" G4 I: ]' i- K691668 Stimulus editor hangs on doing change type
. E* V% }6 O6 M/ L+ D691740 crash when setting coincident uvias in CM beta testing 16.3 3 F" ^+ u7 W7 V/ K8 L
694139 Case difference of net and bus while generating FPGA netlist 9 w5 M0 [, [3 H2 J$ Y7 e3 v8 y
694716 Waveforms are flat when using IO b-element in HSpice 0 c% Z O5 H$ _. D, G+ S
695109 Incorrect Diff-pair topology extracted by Paksi-E field solver 8 [8 ?$ v, \4 b) p; j" ~
695431 csv2ptf fails without providing any error message
" x' f4 B2 F& P) o696273 Shape disappears when updated in CDNSIP 16.01 and not following the constraints 4 A `: u# R9 _' r7 x/ a
696534 Pin Visibility check box doesn't work while creating part from spreadsheet editor ~" G' s7 v3 o C% W A
698494 Shape not getting filled correctly `; x% Z0 z, E8 Y( B8 U/ Q0 l
700160 Error: TVCurve must start at time zero . * j3 _9 I5 O- M& l! ~( X0 q% O
700644 Allegro Crashes on doing Zoom In 2 P; H" l' i$ G1 O
700725 Create Fanout with Via structure add structure from Top to Int. for bottom pins
) [8 P5 N L" p2 P701128 Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
+ ^. N; \( d! B702557 Incorrect Behavior with FSP 2 FPGA Option License $ B3 z; r# D6 m
703324 Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in ) t1 R+ `5 o0 E3 L
704268 remove ARC and TOGGLE rmb options when in add rectangle or add circle command
1 N0 }* b9 C( s+ A, H- f704317 Capture crash when deleting schematic folder 5 R: F8 @7 |; Y% o- z
704475 Allegro SI change editor to Allegro PCB XL causes menu problems
2 o5 G% r( y2 V- z5 k705902 ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor z- m2 ^% l# w" Q% i) K, v
705903 Cannot remove a matrix view after modifying the connections 1 @7 d5 K3 A3 Z, |
706169 IDF in error has spelling mistake
& @+ j/ ]# y3 E" e706613 Diff pair is not extracting properly through design link. / O9 V" j1 ]3 ~' c
706729 Import properties fails with ERROR [IMP0020]
0 V3 x8 u/ w. w6 l x708134 Place > Manually command menus not refreshing the Placement list , k8 {" k# N. U7 M! ]: v3 J9 m) u
708145 Creating a netlist with Rev. 57AQ is not formatting correctly
+ A; v( t% e7 d' ~708634 Shapes getting incorrectly displayed in 16.2 7 b" \& ~# W: u# @: r
710279 ERROR 8020# Place component operation failed. - \. \$ X6 J( J% D- [7 f
710859 Unable to create Diff Pair from Autosetup ! P3 x: [$ D; X Q" x* ^$ z4 k
711739 selecting one component/symbol of class IC can move unrelated component due to
! H5 n+ t$ i, B! vincorrect group membership.
! v# z" I, A# i5 ]$ _* V H8 o" e% ^712299 Internal application error while creating new design
: P* Z% f" S- E1 S712898 Netrev should not read PARENT_PPT_PART property value while importing the logic,
" c% v/ |3 z4 u& Z, o% P8 J9 _due to which import logic fails # T3 A1 C0 C" o
713465 Problems with dynamic shape creation over routed full-arcs diffpairs ' `0 Z5 x% t9 Y& f% o
713480 Display issue when adding a custom property to the first bit of the bus. + n2 S& ~- }' O, N/ @; f) f
714072 Error while linking database part
, H8 U& l4 L5 y. f714156 Capture crash while archiving project for external referenced design
: d3 I$ N0 o) @+ c: C$ V" f7 l716097 Specctra is crash during route. % N3 }! M; D7 R4 O/ X7 z) f: K0 _! E
716212 PACK_SHORT property gives package error for visible POWER pins 717484 Dynamic shape creating voids when moving a symbol # D/ r" t0 l K2 i( M# c$ m
718151 Geometry not selected when we click tab for selection filter in pad designer
$ w% \+ u" Q! f/ H, i. p+ B+ D0 i# }720092 Difference of behavior for slide for segments in options tab & RMB options
! K& D/ D% D0 A6 `- x* b1 ~720191 Delay tune cannot keep the Gap if the diffpair segment is diagonal. # K! P7 i$ n5 W
720482 Include steps to Enable PSpice Menus in Design Entry HDL $ l+ t j2 p# s5 k
721415 Two buses are connected without a warning when moved on top of each other
% g% h5 i) }/ f2 B3 [- `721938 Cross-Section open error
. f0 f0 q0 O! w: l( W$ n. V5 c9 ]& `; [722997 Hyperlink function does not work if zone info. includes hyphen p- s. O6 y3 |9 i7 d
723146 Pb during compilation using predicate getFileStrings
/ X5 }) P- e" b; M: E723159 Typographical Error under "Synchronizing PTF Information" section " V0 s. B; d8 N8 w- x) K5 x2 E
723235 client install results in incorrect, redundant, and problematic cds_lic_file variable : `4 Y) N0 Z+ t
724414 State Wins Over Design does not reset the subdesign_suffix block values
8 h3 T& y& ?9 p5 ~$ p) B724969 Allegro crashes when using place replicate function 2 A+ [0 v# |: F) m# X
725852 Impedance has little difference - BEM2D 4 j! ^) z2 `6 c! S/ ~ A' p5 ~
726731 SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in
3 z' z1 N7 S$ w: bbf not following snap ) b1 r. ? V8 N7 r/ ?
726763 crash during logic import in Allegro CM enabled flow
3 L; R4 j4 w- i2 u7 V# V8 G9 y- l727663 Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly 8 `' _7 p# G2 x1 M& @& R
729496 Build error in 16.3 and 16.4 cdnsip.exe |
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发表于 2009-12-12 17:07
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发表于 2009-12-12 23:20
