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DATE: 02-07-2014 HOTFIX VERSION: 022 x/ F* q" Z2 C4 `4 y
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3 C/ Y7 R8 ]" w$ Z! f- N" _CCRID PRODUCT PRODUCTLEVEL2 TITLE8 Z0 K; k3 C5 H. l! x/ ]
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6 s7 k; q) J+ V192358 ALLEGRO_EDITOR PADS_IN Pad_in does not translate some copper shapes% D- B6 E9 L; l. A2 e: H2 Y0 F
222141 ALLEGRO_EDITOR PADS_IN PADS_IN: Extra shapes are created whenimporting PADS design5 x9 t1 \6 _& T& \- a* k
274314 ALLEGRO_EDITOR PADS_IN PAD_in boundary defined for flooded area be translated DYN
n4 h8 `) ?7 [413919 ALLEGRO_EDITOR PADS_IN pads_in cannot import width of refdes.9 a: ^& K0 ~1 r9 A) t( v
609053 ALLEGRO_EDITOR PADS_IN "Mils to oversize" of "pads in" did not workcorrectly for MM data.
8 s: J$ K9 z4 W2 X666214 CONCEPT_HDL OTHER Option to increase Line thicknessin publishpdf utility
7 ~; Q) F8 o0 Q' s738482 ALLEGRO_EDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
, j6 [! {& M9 n) v' J* C982950 CONCEPT_HDL OTHER change the mouse button for thestroke to have same function with in pcb editor
0 [0 a: T7 b/ O: @1020886 SIP_LAYOUT LEFDEF_IF a quicker way to promote die pins (byimporting macro_pin list)
. k w2 j$ d# ]- C1032678 CIS VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants." v4 ~& s9 N7 l$ Q: @+ c
1033864 ALLEGRO_EDITOR PADS_IN pads_in doesnot translates teardropspresent in design4 |; C5 W; P0 n9 Y u) w
1054862 CONCEPT_HDL OTHER Option to increase Linethickness in publishpdf utility
! ]8 ?% x7 A3 o2 {9 g S% l6 N1055252 FSP PROCESS Add a synthesis option to target agroup to contiguous or consecutive banks
8 s- Z! W1 u& O8 g; z1 y% [, I1100772 CONSTRAINT_MGR OTHER In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.$ g! u3 H. d8 e0 `
1135020 CIS DESIGN_VARIANT Variant list is showing wrong results forhierarchical designs6 |, g6 y$ \3 L X( k+ N
1138951 SIP_LAYOUT DIE_ABSTRACT_IF Fix die abstract r/w to properly supportpinnumbers on ports
5 _6 y8 J, v1 {1140042 CONSTRAINT_MGR OTHER Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
& v; ^* x& ~: G" {1143662 ALLEGRO_EDITOR INTERACTIV Enhancement Request for RMB - Snap Pickto options increased to include Pin edge ~8 v" ~, Z$ O v! y
1147961 PSPICE SIMULATOR Simulation produces no output data$ S! q' u2 u7 C$ \3 F
1150874 ALLEGRO_EDITOR PADS_IN Dimensions in PADS are not translatedcorrectly during pads_in translation1 r5 ~, y5 V: k- x4 l
1154184 CONSTRAINT_MGR CONCEPT_HDL Difference in the way topology isextracted in 16.3 versus 16.64 p# N" s) j. E3 _% U& r
1154770 CAPTURE PROPERTY_EDITOR Variant Name property doesn't show value inVariant View mode
5 T3 B2 X& L# M/ @0 p1158350 CONCEPT_HDL CORE Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design
4 A$ X1 _' p. u) V9 I& Q1162347 ALLEGRO_EDITOR EDIT_ETCH Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly' ]4 v! \5 P, ^9 T
1165553 ALLEGRO_EDITOR INTERACTIV Subclass list invoked from the statuswindow does not represent correct colors.( R0 v5 {) J% I I& S2 k s
1168079 FSP MODEL_EDITOR Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
/ q5 y2 O, C4 H1172043 SCM OTHER : in pin name causes SCM to crash
) D* `/ j; s" B4 d1 p {1172207 CAPTURE STABILITY Capture crash while adding new partfrom Spreadsheet
( f/ r, W: E9 _/ q1172743 ADW TDA Allowed character set for thecheck-in comments is too limited: Q! _( J$ C( I, ^. s$ [' H
1174099 SIP_LAYOUT WIREBOND Option to reconnect wire based on 縫in name� in the Wire Bond Replace
* h/ Q J' w: Y8 b, W0 w6 Z" I* C6 k1177672 APD IMPORT_DATA Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process+ H! E* i4 Q- j) M3 j6 u1 N, b% b, n
1177714 CONCEPT_HDL RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible" `8 X4 F/ [. }, l
1177820 CONSTRAINT_MGR INTERACTIV Done the Allegro command when attemptingto launch CM
0 y1 V0 N: I0 Q1178586 ALLEGRO_EDITOR EDIT_SHAPE Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD4 B+ A8 X, C) p$ }
1179688 PSPICE STABILITY pspice crash for particular HOMEvariable vlaue" p- P- T$ o+ s, K. g, P: a# A$ H
1179827 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
/ T& n# }3 n, g9 v$ q8 }, V1179879 SIP_LAYOUT STREAM_IF Data file corrupt when exporting Streamdata from SiP database.
( w! O' {7 P9 _1180164 F2B BOM BOM csv data format converts toexcel formats
8 {( ~4 T7 G' T3 M/ Y" _* d# l1180477 ALLEGRO_EDITOR INTERFACES IPC-356 output is listing a duplicatelocation in the comment section* _2 G1 s4 N k3 o- D) u {
1180932 SIP_LAYOUT OTHER SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
, w" C& h# z% e' {2 T1181377 ALLEGRO_EDITOR INTERACTIV Pick Releative does not work correctlywith RMB-Move Vertex2 g$ y3 v; I( _- w* G
1181516 ALLEGRO_EDITOR DRC_CONSTR Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one.6 q, g( n/ b; i8 t: S- s
1181739 GRE CORE Running Plan > Spatial crashesGRE& H+ |$ _! q! u$ G9 i0 a3 [, U
1181935 ALLEGRO_EDITOR DATABASE Enh. Property that allows internal C-CDRC errors$ m) N. m% |' j5 f" J! P# c
1182185 SIP_LAYOUT OTHER SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
; X8 X8 T4 h" Q/ \5 e1182566 SIP_LAYOUT OTHER SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap1 r& H0 m. q3 }) k' \: @
1182599 CONSTRAINT_MGR DATABASE CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.
6 h" p( b# p5 v% Z( A1182892 CAPTURE SCHEMATIC_EDITOR Pspice marker rotationbefore placement
$ f7 h, M' X! [: z6 E0 [1183682 ALLEGRO_EDITOR DRC_CONSTR Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level& G8 ?$ V! b" H, \
1185445 SIP_LAYOUT DIE_ABSTRACT_IF Die abstract export needs to be able toselect xda file type when browsing; ^6 h9 q* a+ u4 v- G- D
1185932 ALLEGRO_EDITOR SHAPE Soldermask in solder mask void DRC2 s9 g5 }3 e/ `! ~2 F( |9 a# y
1185946 CONCEPT_HDL CORE Ericsson perfomance testing report5 sept 2013
' b$ a% w, N+ T5 J1187213 FLOWS PROJMGR Unable to lock the directive:backannotate_forward
9 ]; k5 J2 @! ?) |! G* t1187444 ALLEGRO_EDITOR DRC_CONSTR With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC"
8 n- F7 |! L7 c4 @' j% ~& I6 C$ } y1187597 ALLEGRO_EDITOR DRC_CONSTR No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.
+ Y- _& @: ~" g4 k1187723 FSP PROCESS Synthesis can fail depending on componentplacement
( E7 E( ^% d) E8 T" M* V3 C1188164 SIP_LAYOUT OTHER SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
) V2 q4 K* g- ^& @5 ^2 j: l" s1188245 CONCEPT_HDL CORE INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic
5 L9 G9 I3 v2 B$ g+ c e1190927 CONCEPT_HDL CORE Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
7 p3 r6 f9 e) N8 }6 C1191497 ALLEGRO_EDITOR INTERACTIV ENH: Adding names to the text blockparameters numbers
. c8 z' g1 h/ r# k$ u/ i) H! i- Z1 r7 w1192005 SIP_LAYOUT IMPORT_DATA Import SPD2 is missing 1 smart metalshape from file
$ y) S/ z; U3 x' Q# d9 i1192204 ALLEGRO_EDITOR EXTRACT Need ability to extract vias that arelabeled as microvia% E" c3 J! | L
1193063 ALLEGRO_EDITOR MANUFACT TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
8 l7 R) `# F7 L" A! f7 W; P1193418 ALLEGRO_EDITOR GRAPHICS 3D Viewer can`t export image in both SPB166S015 and SPB165S047
$ \& W/ a1 t2 @ b! m1194305 SIP_LAYOUT EXPORT_DATA export package overlay creates file withno package info* p6 U: \9 R. V \' a$ P; v$ r) a
1194418 APD IMPORT_DATA issue when doFile->import->netlist-in wizard
. i# r+ h3 `, g. X0 U1195279 F2B PACKAGERXL Ptf files are not being read whenpackaging with Cache
6 I+ |" C: n2 \5 ? M8 }8 A1195374 ALLEGRO_EDITOR INTERACTIV Modules are not showing up in Tools >Module reports
5 B. T, r5 \. t8 n0 {7 k1196603 SIP_LAYOUT EXPORT_DATA Change form for "Write PackageOverlay..." to better support longer lists of routing layers$ i6 O% S; S8 U1 f: W" U
1197302 CONSTRAINT_MGR UI_FORMS Inconsistancy in selection of objectfor Spacing Constraint Worksheet$ K1 ]0 m- L( X9 U, r2 {6 J1 R
1197399 CAPTURE OTHER Draw toolbar disappears when usingPrint Preview; @) F y9 ^ G8 Y6 l
1197543 ADW TDA TDO does not correctly showdeleted pages
7 d/ w. }- [0 K* ?- M6 y" `' x1 n1198033 CONCEPT_HDL CORE Signals do not get highlightedwhen Show Physical Net Name is option enabled
- C3 P( @3 V2 B3 v- K3 j1198468 ALLEGRO_EDITOR GRAPHICS 3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.3 O8 z/ z0 @4 w
1198617 CIS GEN_BOM Mech parts are showing with Partreference in CIS BOM
7 @- @5 u: K+ P7 w* c. {1199764 ALLEGRO_EDITOR SHAPE Allegro crashes when trying todelete small island on POWER layer.3 u4 d1 L) t5 e k9 R- Y d
1200232 ALLEGRO_EDITOR INTERACTIV Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.. m* M! J/ A$ F3 u
1200748 ALLEGRO_EDITOR INTERACTIV Additional pin edge vertex object tosnap pick( _3 S7 q7 { A- g5 S6 x0 l T
1201056 ALLEGRO_EDITOR DATABASE Unsupported functionality strip designcreates a .SAV file& S/ u/ O e# b+ } f% W: s
1201638 CIS PART_MANAGER Part retains previous linking inside thesubgroup
" [! }& X8 l; [4 ?& f0 Y3 s" B/ G1201834 ALLEGRO_EDITOR PLOTTING Bug: Import Logo command changesresulting imported object% |: u/ K0 b8 l* S. D" g5 [- ]
1202406 SIP_LAYOUT OTHER enable the dynamic display of componentpin names for co-design dies in Sip Layout
& N6 v, T' ]. m% w3 P* F1202431 CONCEPT_HDL PDF The publishpdf -variant optionshould have a "no graphics" option
2 A% t' k; C2 _) e6 N6 k1202717 ALLEGRO_EDITOR DATABASE About Warning(SPMHA1-108):Illegal linesegment ... end points.
. K& N$ X# O' Z, x t6 ~1203459 CONSTRAINT_MGR INTERACTIV Object Report has no mechanism to outputinformation for a specific design.9 D- R/ g9 o1 Y1 ?4 `: P- h
1204544 F2B DESIGNVARI Variant Editor does not warn on save ifno write permissions are on the file
$ k& X8 P0 m: h: t, R1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax
0 m8 ?( i+ i O4 W3 r3 `! |1205952 ALLEGRO_EDITOR GRAPHICS Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
/ y' \+ f9 M: f1 u, @0 I1206103 SIP_LAYOUT IC_IO_EDITING add port name property to pins, and addSkill access I/O driver cell data
4 P( I( o# o$ W! z* V7 \; i1206546 CAPTURE ANNOTATE User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�0 _' {- `) J q4 l0 z" o9 z
1206561 ALLEGRO_EDITOR GRAPHICS Not all mechanical symbols made with Stepfiles are displayed in the 3D View
5 n/ l" t8 B5 W. ~3 f5 \/ U1207125 SIG_INTEGRITY ASSIGN_TOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus& G: h2 G. Y5 Y% y% o
1207386 CAPTURE GENERATE_PART Altera pin file not generating the partproperly8 u" T. J& R( u% L# F
1207629 CAPTURE TCL_INTERFACE Bug: GetMACAddresses tcl command notworking0 k# p3 D' `8 t) Y; W: ?# }0 x
1207994 CAPTURE TCL_INTERFACE TCL pdf export in 16.6 fills DOT type pinswith black color6 c$ C; S) f6 g" {2 s: G5 ?# Z' }
1208017 F2B DESIGNVARI sch name is not same when updatingSchematic View while backannotating Variant4 |. b% \3 r% x0 e- Q
1209363 ALLEGRO_EDITOR INTERFACES When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees.6 B) Y; L) P/ x+ T5 s3 G# g
1209769 CONCEPT_HDL CORE Top DCF gate information missing1 {1 Q( C& t+ E& ^0 y' H& H* _
1210194 CONCEPT_HDL CONSTRAINT_MGR HDL crashes with Edit Via List dialog box
) x# w. J/ p8 c) B4 K- _8 }1210442 CONCEPT_HDL INFRA Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage# o. q4 `' \6 C( ~
1210685 ASI_PI GUI User can't edit padstack inPowerDC-lite9 ?) G. Q3 b) n9 h
1210744 SIG_INTEGRITY SIGWAVE SigWave: FFT Mode Display unit seemsnot to be correct
! d p( ]* M% V: x* C$ S1210829 CAPTURE NETLIST_VERILOG Shorted port is missing from verilog file
" ~3 {9 M0 I+ _ t6 E9 I1210850 CONCEPT_HDL CORE DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library
" k2 h" U+ M3 l1211620 ADW COMPONENT_BROWSE Component BrowserPerformance5 S4 ~/ r2 ?2 {
1212102 ALLEGRO_EDITOR INTERACTIV Shape edit boundary adds arc mirrored tothe highlighted preview.
4 E! O. T# K8 a) T9 q. N1213294 CONCEPT_HDL SECTION DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins1 D2 K7 S" R. B) ?: X/ r" |
1213402 APD DATABASE The old "ix 0 0" fix is now causing the features to lose netsentirely.
/ {6 {4 X. @8 _0 A' S* E( g# P1213694 ALLEGRO_EDITOR PARTITION Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition8 V- k% i# N3 H3 D; A
1214247 CONSTRAINT_MGR UI_FORMS Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting4 q& D( a: K9 N# s% y% J$ i
1214320 SIG_INTEGRITY SIGNOISE signoise command with -L and -k option% V0 U: J. {+ R$ J9 N# [: [% t
1214433 CONCEPT_HDL CORE Genview does not update sym_1 withports added to the schematic8 b- y& t1 J2 P
1214909 ALLEGRO_EDITOR NC NC Drill Legend show extra rowsfor drills9 P1 w- I' _8 R2 M$ d
1214916 SIP_LAYOUT OTHER package design integrity check forvia-pin alignment with fix enabled hangs
. g( k3 h" O6 s1215954 SIG_INTEGRITY SIMULATION Cycle.msm does not exist error whensimulating extracted net& Q( X& ]2 _! I" B/ D
1216328 CAPTURE STABILITY Capture crash) K$ b& Y: ^3 I6 i& x& l7 i# Z
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crash on SPB16.50.049/ e4 X j; j" S' t
1217450 F2B BOM ERROR 233: Output file path doesnot exist+ f+ w2 z& y$ q; z, u. _
1217612 ALLEGRO_EDITOR INTERACTIV Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB37# C V) g, b% e3 Y
1217823 ALLEGRO_EDITOR INTERACTIV Compose shape fails with SPMHIS-4733 v8 l; Y" Q. I3 W
1217887 ALLEGRO_EDITOR INTERFACES An undo option to be made available inthe STEP Package Mapping window
, j; @* _1 f4 `9 a1 ?1218665 ALLEGRO_EDITOR INTERFACES In step viewer, the bottom side partsare placed above the pcb board surface: v* }2 z' O( Q3 f+ @. ~) V& {
1219053 PSPICE PROBE PSpice crash with the attachedDesign
) F/ Z2 N! E: z$ I1219067 ALLEGRO_EDITOR EDIT_ETCH dynamic fillets behavior is unstable0 K2 Q( p/ f* S- p8 x0 ]+ g
1219095 ALLEGRO_EDITOR MANUFACT Design Cross section chart is taperedfor two layer board
) ?) H5 F5 `; ]2 |, h1219126 ALLEGRO_EDITOR SKILL Skill issue with axlRefreshSymbol()
$ ?, \0 [1 H0 P' a1 {8 ? D1220701 ALLEGRO_EDITOR INTERACTIV View > Windows > Worldview(showhide view command) fails with command not found
2 Q" f3 H1 O# p* ^1221057 ALLEGRO_EDITOR REPORTS Units in Cross section report forspacing is not synced with the design, ~4 D. R N% z6 G- z& O; ?
1221139 ALLEGRO_EDITOR EDIT_ETCH Delay tune is not tuning differentialpair
- l( A& `, _* s' {7 V; G1221157 SIP_LAYOUT IMPORT_DATA import spd2/na2 file is not importingdata correctly into sip
! I. K- R0 D7 d6 {$ Q5 V% Y1221163 SIG_INTEGRITY GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.
! s3 F" h5 l- K# e0 b% j7 C6 }1221416 ALLEGRO_EDITOR DATABASE strip design for function type
/ ?, x% B7 o" t3 l+ k1221931 ALLEGRO_EDITOR DATABASE Fatal software error when embeddingcomponent& o6 t: X; k5 V+ R/ B
1222105 CONCEPT_HDL CORE Moving Pins around the edge of aBlock causes the text of the pin to change its text size.; `* W. `" S2 H$ ^2 J( l3 z
1222124 APD DATABASE Same Net DRC's exhibiting inconsistentbehavior.; U2 R+ l1 P3 v/ b
1222272 SIG_EXPLORER EXTRACTTOP Cannot extract net or open SigXplorerafter selecting a netgroup
2 r" M& l, [- B `' r1222329 ALLEGRO_EDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
6 s: H8 m5 D, M( w/ H$ I1223183 SIP_LAYOUT BGA_GENERATOR Getting an incorrect error message whenusing the BGA generator with a long BGA name.
! P# D+ d/ U" T- ?" s- V6 S1223662 ALLEGRO_EDITOR REFRESH Allegro crashes when trying torefresh symbol. r+ ^+ A. V: F
1223932 CONCEPT_HDL CORE DEHDL block desend does not find1st page if its not page18 K4 V! I5 l; w$ ?0 v# O5 H3 ^
1223940 CONSTRAINT_MGR UI_FORMS Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.8 G8 v$ t2 T, |- W7 \
1224127 SIG_INTEGRITY IRDROP Is the old static IRDrop in 16.6officially supported?
) T9 k$ O4 f5 L4 D2 @: |, j1225492 PCB_LIBRARIAN CORE PDV expand vector pins resizessymbol outline to maximum height again* H2 R' m6 S8 O- E& Z' U
1225546 CONSTRAINT_MGR ECS_APPLY nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end, x _: d6 S& ^- E: d
1226405 ALLEGRO_EDITOR INTERFACES File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
3 F( Q" Z( ?: {% |. h% ?1226448 PDN_ANALYSIS PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL+ ~. R% [- G' n' g, E
1228721 SIP_LAYOUT OTHER File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer |
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发表于 2014-2-10 15:09
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