|
zxli36 发表于 2012-12-29 09:04
8 y% i, x+ m+ U6 l& A能不能把你Package时的信息发上来大家看看。
) q, g9 s" o9 T& P% ?Package时的信息如下,总共有二十几个问题,几乎所有器件都有问题,这个问题困扰我很长时间了,麻烦您帮我看看,非常感谢
, j! ]9 f% {1 R: x! {& M: k# {" H3 z% T5 j$ [1 W) O* J3 ?
-------------------------------------------------------------------------------------------------------------------------------------------------------" ~' ^; |! V9 d
Started C:\MentorGraphics\7.9.3EE\SDD_HOME\wv\win32\bin\packagerui.exe F:\demo_dx\demo_dx.prj /d Board1 /nobrowse /config "C:\MentorGraphics"
$ F2 j ?% z ^9 |( r) r7 s7 d6 {1 p: B2 y" {2 @6 ~( C
Packager Version: 020806.00
$ h1 X/ @/ Z! }, X4 F( J6 E& |4 c7 D) Q
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"& v( G7 p- i1 b T c) ]/ d3 _
4 v0 Q' m2 i' y k! d' nThe Common Database is at "F:\demo_dx\database".5 L! y e/ o! f) |- n) e) x
$ Y* a% Q! c; D" ?. |3 tThe Root of this design is "Deme_Root_1".+ x: Q7 k v& ~- T
7 v* T' V2 q5 _& z5 m
The Front End Snapshot of this design is "DxD".
/ L9 Q1 j, j F' W6 y, X! P9 b' i2 y Q5 y- u+ l
The PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
% `$ e- h3 S* s, [2 v7 m3 l" v7 H
The Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
- s$ B9 L. @, p. k+ h& R
4 W3 ~% G1 r6 m7 Q0 K4 \0 I, K( wUnable to determine the Disable Repackage status.
( m; s, o4 Q, p, M8 g!Repackaging will be allowed!
2 a1 P/ G' o2 y. u4 T* M$ l7 J C+ O# G4 S9 f( n9 _$ r
The PDBs listed in the project file will be searched to satisfy the parts
. s4 T) M- h# E7 ] r- m- Jrequirements of the iCDB only for parts not already found in the7 \/ X2 k# c! a) P' x
Target PDB.
$ V/ w. b" m& c* d0 ]: g( Q+ S: \, O) F/ n& j* r2 F, m
The AllowAlphaRefDes status indicates that reference
: o' t' N9 m$ D1 |" r+ x, D; u1 a odesignators containing all alpha characters should be deleted
- a- I* C7 z( t1 ^! l' K5 a2 ^and the relevant symbols repackaged.1 U% T9 H& y) K4 X0 b& ?
3 _- S' {/ z& \" ^: l0 M, q
The cross mapping of symbol pin names to Part Number pin
3 n" t) X) ?" Tnumbers will be checked for packaged symbols and mapped correctly
. {4 I; G [' p o, S0 p, }for unpackaged symbols.+ S/ P( ?- Y1 f
5 [3 U% m" R( t4 n& D2 zProperties that have been checked off in the Property Definition Editor; t( \0 ^, }% @! L1 E' x" D
found at Library Manager/Common Properties will be checked for value5 E$ l7 @ l- I: ~) A x% H
differences between the PartsDB and the non-null properties on symbols.% ^3 \" B! Q# _- a& \ a7 W, a, D( a9 p
Those properties checked off (other than Part Number) C8 G/ [; \4 d" g" N3 n2 w
will not be transferred from the PartsDB to symbols.
3 F; G# u, d9 K7 s" cThe following properties were checked off in the Property Definition Editor:0 Q k$ E6 k; y7 S& e. |6 ?
"EPFIXEDWIDTH". T/ w" v, j7 O6 J W) a
"EPFIXEDLENGTH"7 Z2 b0 Z$ ~" |- t1 X( C. J
"Term"1 ^5 L7 H% H- q/ p9 r; m
"SIM_MODEL", E. Z0 ?/ T! n9 E
"SIM_MODEL_FILE"( m7 i, d' X: z% E
"Array Component", l- G5 ?8 n: H8 D+ b& ]
"ICX_PART_MODEL" l1 t5 q6 Q/ [
"Use Verilog") ^% K7 `) z- c c, e
"Order"
5 l9 p& H2 o0 | q"Parametric"
3 E9 `% R3 c, F! A"Value2"
$ d# T4 E8 G) t, N& G% N, T1 {"Tech"
+ b5 z! [; m7 K4 D"IBIS"3 n! V) ~( P$ X$ ?4 b+ G5 {
"Part Label"* S* a& x, x1 d7 i/ Q
"VHDL Model"
: w1 R) z& n( p: B8 ^( P8 ?" u"Verilog Model"
( l8 N( J: B Y0 ]$ J* P2 S"Cost"
0 e2 p. ~! R g9 J0 ~ V"Tolerance"2 O' o L% F8 z- L+ X6 j9 n
"Part Number"8 q, K& r: P' o) A7 B
"Value"
& u$ K; ^- t5 \, ?"Part Name"+ q+ H0 l2 t0 z5 a. y4 r9 l
) j$ m" v& }- T. P! ]$ u& n3 t
6 S! J; l( d5 S1 D: m! j% c8 BTesting of Packaging is being terminated with 22 errors and 1 warnings.2 j. _9 j) @9 E: i8 i
Design has NOT been packaged.
7 C1 m; B. Q" Y: A8 ?2 A. v/ g3 P" c; Q! m3 X/ |$ z
Writing to Log File: Integration\PartPkg.log% p" Y) ?" q$ {" B
# a/ M9 ]7 T: c
There have been 22 errors and 1 warnings.
3 B" q+ h: e; X& y0 _& N1 y) H3 O. D8 l6 V+ f6 K
///////////////////////////////////////////////////////////
; Q* Z& ^1 k( G///////////////////////////////////////////////////////////
' ]' |. n+ v9 y6 O///// The Log File will now be copied to this window. /////
8 A: A( X: {3 N4 f: U///// Therefore the data above will also appear below /////7 R- G$ I* }# t. }+ I0 z8 E# [* `8 c
///// with more specific error and warning messages. /////
- C; K1 G, h) C+ w///////////////////////////////////////////////////////////
) J, [7 E/ R( P7 X+ W6 f. j///////////////////////////////////////////////////////////2 O4 d6 C( t( b9 I& d
( F- I- u" N9 R
5 x' x& G5 r0 t' l$ j2 m2 Q
Packager" c& C8 \+ u9 ~/ F7 x9 F
--------
: D3 Z$ {% Q3 v8 ?: u& v) B* |3 ~9 V$ d& }5 U& _
09:27 AM Saturday, December 29, 2012. H6 M' k" |5 E( R+ f
Job Name: F:\demo_dx\demo_dx.prj8 t- ?( o$ U( {4 n6 a
( u5 x) W, ?: V& j8 e7 Q
- z7 ?: Q8 X+ D8 J% D% ?Packager Version: 020806.00
$ N O |- A# M+ e7 ^+ f' F' ^! {* T. O3 w/ V4 G# t# ?
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"# ~+ S4 l5 U/ e5 `6 b
8 b) z% k8 ~- o. j/ v' sThe Common Database is at "F:\demo_dx\database".( E8 u8 f6 T6 q" @' ^8 }* B
8 g) d0 {' ~( @/ ~6 fThe Root of this design is "Deme_Root_1".2 ~- O4 U, _9 D. Q( w5 C
0 }$ `8 `1 Y0 m
The Front End Snapshot of this design is "DxD".1 Q' D7 i) Z+ `* u
( C# E- S W" h' t0 @3 B+ e
The PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
5 B% E' m) c2 o7 w) U" ?! E7 W
4 V* Y) c0 T, o, ]: e F2 FThe Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
; J5 ^3 ]7 e7 c- w6 E1 }7 C, B8 e. A% n7 I! z. H: Q
Unable to determine the Disable Repackage status.
1 r0 A$ L, l( T k* H!Repackaging will be allowed!) @7 }6 |1 E' i3 U/ E3 y% O$ x
4 e! \8 p4 w, ]6 o; i3 f
The PDBs listed in the project file will be searched to satisfy the parts: }2 A- |& l7 O: z Z r) c
requirements of the iCDB only for parts not already found in the
6 G' q4 B( }+ KTarget PDB.
# [! b/ q% Y) M' `7 H5 U1 Y" W5 y1 q
The AllowAlphaRefDes status indicates that reference
/ s' N) `; w" q7 z4 d6 Mdesignators containing all alpha characters should be deleted& h* x" H1 S) I7 m! |
and the relevant symbols repackaged.
0 e: E& `/ ^3 Y4 ]( F" [6 `7 X* i3 o4 I. u8 f8 \/ C2 Y [9 m) i$ x
The cross mapping of symbol pin names to Part Number pin
" r" I* s$ z" a. `4 xnumbers will be checked for packaged symbols and mapped correctly
- B8 i6 U% ]* H3 O# O* z0 Y* \for unpackaged symbols.
7 Z: d+ B& S3 m" l" @* E. B/ `) m
, [) F; C! v2 W; S4 aProperties that have been checked off in the Property Definition Editor
2 c2 a1 J8 F+ } a+ {# Mfound at Library Manager/Common Properties will be checked for value
* _, h8 c& Z$ ?5 Kdifferences between the PartsDB and the non-null properties on symbols. u# `3 _: X' A
Those properties checked off (other than Part Number)- E; a5 w5 k( I, I
will not be transferred from the PartsDB to symbols.9 i: h% ^: E# H2 ]' X$ e1 F% z+ s
The following properties were checked off in the Property Definition Editor:) C. m, `9 ~ B9 z% D
"EPFIXEDWIDTH"
5 U9 V) G9 {6 k( ["EPFIXEDLENGTH"
' [: n& k @8 Q"Term"8 H( S1 K3 z [! g4 ~& d
"SIM_MODEL"
, U4 D$ V8 k! Y. k% s. U# F( x5 I"SIM_MODEL_FILE"
5 D! ~* \* P5 Q. L"Array Component"
/ \& {9 B- l9 D4 s* @"ICX_PART_MODEL"; q9 j! b5 x' V7 K. Z
"Use Verilog"
; E8 X/ c8 n# |3 K) E"Order"; g' K* N8 }) h0 J$ B
"Parametric"1 @5 a* J7 k ~: N- i
"Value2". c0 z) |$ |$ J, Z
"Tech". I7 R9 x) K( E) `
"IBIS"1 C- n6 i: Y) P3 [/ d* h
"Part Label"- Z0 G( p9 F0 J7 [3 l' \* O$ }
"VHDL Model"% v |0 B* | L; `! m" h
"Verilog Model"
$ c3 h: c0 \6 G/ n8 r2 o"Cost"
' C. F ~' F J6 n"Tolerance"
9 t0 l7 t9 U* A5 @" w# H"Part Number"
& n% @# K' N8 _- w; `* p$ G. S"Value"& e0 Q# h& C& u; c
"Part Name"
0 a* N$ s& o$ ]& Z7 ^/ k' _# X1 g2 b" L6 U! J2 B% {+ o
Checking for errors in the ICDB...
, o( q5 F. Z0 t- z# E
7 x( x) Z7 m0 K4 c: [$ Y7 B: O# O5 mNo errors found. Proceeding with packaging...
) F3 e- z9 r5 C3 N/ V7 S5 @7 |$ {' `' K' T
+ {2 B1 Z B( s# ^9 w3 |4 z1 F
7 ^+ N, @1 L4 \) d V. cCommon Data Base has been read$ K6 n& ]+ F" ^ c8 c
5 r+ n; |6 r( F$ P
Target PDB Name: Integration\LocalPartsDB.pdb+ y! I8 S$ \" @$ c D) e3 C
. q1 i" G3 z% a( S6 K/ ^
WARNING: There are no PartsDB partitions from which to extract parts.
" G) x) P _( t6 U+ ZProceeding using the data in the local PartsDB "Integration\LocalPartsDB.pdb".4 b; M, T: B1 f: p+ G( A
. L) L3 @+ q* W- @5 D
Number of Part Numbers: 21
; v4 S; n: O x+ Q) MPart Numb: BNC_1 -> Vend Part: & p: i5 a7 H! N' p
Part Numb: CON_EDG_64 -> Vend Part:
8 K% F' b* |8 S: CPart Numb: C_P0.01pF -> Vend Part:
" i& m1 r# a2 {" s; FPart Numb: C_P3.3uF -> Vend Part:
7 s1 |% @. B8 `* bPart Numb: C_P47pF -> Vend Part: * k% ^) e9 s3 [, `$ G/ }" D( _/ t
Part Numb: C_0.1uF -> Vend Part: ! h& u" Z& u# N* A, [/ ?
Part Numb: DG419AK -> Vend Part: + l" g3 A: g4 q. m* d; a9 a
Part Numb: EPC1064 -> Vend Part:
+ Z7 ^7 W( P* J) a2 z' vPart Numb: EPF8282A -> Vend Part:
$ N! D0 E! k- aPart Numb: FCT16245 -> Vend Part: 3 l7 P* L9 d- p3 D5 h: x z7 C
Part Numb: LED -> Vend Part:
7 k4 w. l$ A8 w3 LPart Numb: L_50uH -> Vend Part: ; j$ u5 g, }( z( `8 e
Part Numb: R_2K -> Vend Part: 3 o5 v$ U6 |" a0 K1 v B' P% X
Part Numb: R_10K -> Vend Part:
0 p# ^7 L4 o- y3 V; }. vPart Numb: R_100 -> Vend Part: * e0 X9 |1 L' j
Part Numb: R_220 -> Vend Part:
* e8 r" x9 ?9 J- [* K: iPart Numb: R_510 -> Vend Part: - r/ @ @, X% w# p A- _9 h6 ^0 {, S
Part Numb: TC55B4257 -> Vend Part:
2 T7 I2 \5 b2 R n% t. WPart Numb: TLC5602A -> Vend Part:
, |1 \8 f/ L- ]) ]Part Numb: 20L10 -> Vend Part:
. H9 H m4 M3 { z' EPart Numb: 74ACT574 -> Vend Part: ; l8 H& E& T1 {& J2 u
. f" e" q0 ]* l7 E$ V# O; T6 j
Number of Part Names: 1$ ^( @8 Q# o$ K2 T) D; S: s) l) p
Part Name: TLE2037A -> Part Number:
, j: L" S' C* h3 l
; n- i- s( z& [Number of Part Labels: 0
: e! d, d0 e6 t: B
* I; ^3 Y! y, W" o, s+ M
& J. Y" j/ \( i2 J5 e" n! |Checking for value differences between non-null symbol properties and PartsDB properties,
5 h& V7 Z& m9 ^$ O$ Cbut only for those properties checked off in the Property Definition Editor
7 T0 L. J/ K9 ~! ]" x ~. R4 g9 M
- k3 [! H- l- f/ oChecking the validity of the packaging of prepackaged schematic& J1 @2 V$ L7 W- J" ~- E
symbols. Only the first error in symbols having the same' R! n! \! a& r' {: B: }6 z
Reference Designator will be reported.
' Y6 Z7 j" r3 e
' F1 H* V: i; ?4 ]1 f/ |7 E( TERROR: There is no Part Number: CON_EDG_64 in the Parts
0 |! q! F/ J$ a' |DataBase for symbols with Part Name: CON_EDG_64 and Part Label: (null).
" s; H6 C/ p4 E- ~[Please add the Part Number to the PDB either directly
- b" a- x7 z v% i5 Z& [or by having the project file point to a PDB that contains it.]2 q; F& w' ^& s% ]9 \
The relevant symbols are:
6 E- z! B. `7 j0 [9 w' i2 P. A
, s# U. {9 |. R' ^ _3 K Block Deme_Root_1, Page 1, Symbol $1I41
& p* `+ `" ~( x8 o: V' a& m: e# N& A i# Q' g
ERROR: There is no Part Number: FCT16245 in the Parts/ E/ i" \6 s7 F4 }# e% k
DataBase for symbols with Part Name: FCT16245 and Part Label: FCT16245.
1 m1 z9 R7 m. z2 U2 j+ T[Please add the Part Number to the PDB either directly$ A' ]: Y* P# R: C2 D0 S7 I
or by having the project file point to a PDB that contains it.]
1 F' \- J6 t. f- N! ~' s6 j4 tThe relevant symbols are:
8 f! y( V! K% h3 M5 ~
3 P- a$ }% M. m& Y8 S Block Deme_Root_1, Page 1, Symbol $1I1277 9 I: K: V% m9 O' {+ M
Block Deme_Root_1, Page 1, Symbol $1I1424
. \# X$ Z( n" m& d+ F Block Deme_Root_1, Page 1, Symbol $1I1395 8 d4 M0 d: G( C7 k9 l4 `5 o! M# f
Block Deme_Root_1, Page 1, Symbol $1I1366
* N2 q6 Z" j U1 ~3 ^ Block Deme_Root_1, Page 1, Symbol $1I1337 1 _' Q6 G3 H {
Block Deme_Root_1, Page 1, Symbol $1I1308 |
|