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DATE: 05-24-2013 HOTFIX VERSION: 010/ g+ S$ ?3 B; y
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, c; R0 C8 l V, j7 vCCRID PRODUCT PRODUCTLEVEL2 TITLE
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1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
9 J' y/ o- b- g3 p1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border1 F& N% f9 X0 k& n/ n9 d) z0 h
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files
$ O, \( B: I; `9 b# i1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor" X. R$ z2 `, c' d4 Y
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6
* k& W% I) g0 K/ ^' Q* _1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border. y3 O9 R% I! _8 N
1131775 ADW LRM LRM error with local libs & TDA# @) d. j8 A5 g
1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4
6 B2 `5 ?$ h- ]! \2 J8 E: Z1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo
7 L; t. c8 L6 q+ J7 }1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
+ x0 D& I" W9 o1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur+ g3 | ~/ V& r9 ?! s
1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?; {( m' |) I2 s' Y( D) T2 H5 k
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.
4 t, y1 V& o# k5 o0 Q' @1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor; x( ?% I; N3 M9 O& i0 Z
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
. ]# T+ j! I) M& F1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
5 W' H; [5 \: k$ b% e1 y1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
! x. R' D B. V- o7 e1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash' ]# O. \5 |1 [: t7 B1 A, w5 j
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
$ Y* {. G3 G" D, i8 z1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering% |) C# P% S8 _3 E& y# Z8 r- b; J4 w9 I
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor
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发表于 2013-5-25 09:24
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