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本人Layout之后分割好地和电源层,灌铜时出现这些错误:
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THERMAL RELIEF ERRORS REPORT -- FPGA2.pcb -- Fri Jan 11 21:44:01 2013
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Drilled pads with Nondrilled pads with
; j' f0 D5 Y1 A2 n+ Wless than 50% thermal extensions less than 50% thermal extensions
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/ M6 N, h% F! H4 I) r4 `2 o: cReport of Thermal Spokes Generator.# t: v$ E( v7 y
8 P& Z% Q6 i) y$ t" o; ~On GND3:
, t6 a: _+ T/ S- W4 z6 y (2506, 775) # = 02 j) \, v/ s& d( i* F# e' S* g" |4 d
(807, 454) # = 0
5 k" d" B6 d- l (3125, 750) # = 05 m: L1 G1 p H
(418, 189) # = 08 p5 U% s! W, t) B2 v
(2199, 749) # = 0
* g" q- Z4 _' _0 L6 Q (1178, 648) # = 0$ Q& C" ?/ p, w q- q' Y
(1295, 800) # = 0
; h0 t$ L9 m. A6 n1 O0 c (1256, 839) # = 0% b5 E' O( U9 E% T% }7 d, c0 d
(1763, 878) # = 08 S3 S; S* j! b: H* j
(1646, 878) # = 04 j% \8 I' y; z1 X0 P
(1295, 878) # = 0
& @( a# {$ \6 W* ~' P9 n (1295, 917) # = 0# O) K+ V8 }! X; T1 E, V
(1256, 956) # = 0
5 C! j: H: ?1 I/ f/ @( `+ w (1685, 1034) # = 0
3 S' r% c! o: q/ p5 x (1295, 1034) # = 0
c# C4 R: i+ S8 R (1646, 1073) # = 09 W* U$ {$ ?$ G3 l8 j4 }( A( L
(1295, 1151) # = 0
& m9 K) o! L% o1 c (1490, 1231) # = 0. N0 [0 ^! o* j" C
9 q: @. B+ }8 }: {2 }6 E* Q2 s2 vTotal Drilled pads: 18 Total Nondrilled pads: 0
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Report of Violating Thermal Spokes Remover.( s9 @+ B e: H5 W" @1 D
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On GND3:
8 A6 M) k9 v g: _$ h- Q- d! x (1373, 1151) # = 0/ @9 U2 z: o$ |) _+ ^
(1490, 1151) # = 0
. { c1 F; m4 `: T' Z6 Y k (1529, 1151) # = 0
7 A- Y' V' t3 x (1568, 1151) # = 0
4 G C8 m( h+ S! P5 j' P5 W7 S (1373, 1307) # = 0% f* {7 g5 R2 G
' v, R0 I E& q' e& | mOn Power:
( X, D. }5 y* _1 M4 u (2086, 1220) # = 0
4 k0 W6 m) m& x) r (2334, 760) # = 09 I! b8 n& i F- a# E3 }$ z
(1178, 683) # = 06 i; {% |/ O+ P) x) ?7 ]2 a
(1139, 683) # = 0
6 `2 T! A5 t) @: t! J (1728, 882) # = 0* X( n }7 @' u
(1143, 761) # = 1
" o% _' n* G7 w* p (1218, 1181) # = 0
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4 n M, G! G9 w _6 d STotal Drilled pads: 12 Total Nondrilled pads: 0
$ `# w% k- {* m4 h* c不知道 这是什么问题,如何解决? |
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