|
|
EDA365欢迎您！
您需要 登录 才可以下载或查看，没有帐号？注册
x
下载：http://pan.baidu.com/s/1gdhBNzl
/ _1 e: n, `$ Y! n1 o& r, M7 m4 Y& B7 l5 k0 p$ y/ i% G
DATE: 05-01-2015 HOTFIX VERSION: 002
' ~5 T& T% B- Z% p ===================================================================================================================================
& H R: W, L5 l5 _$ @# N# r CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ c$ Q0 M/ ~8 I0 C1 w$ I' m5 R0 j ===================================================================================================================================" o& b+ f% ~! Y; [& v+ b9 d* G/ F
1315048 ALLEGRO_EDITOR INTERFACES IPC2581 translation inconsistency on negative layer5 S9 d$ }; [ `2 ^- O( O$ D% i0 H% q
1362745 CONSTRAINT_MGR OTHER Allegro PCB Editor crashes on opening Constraint Manager with any design
5 k4 S, M) Y" p& y3 }0 F# a 1373412 ALLEGRO_EDITOR GRAPHICS SigXP Print Canvas : Via model seems to be filled by black Via box.
1 d# h7 L! o Q6 o4 d. g0 t 1376765 CONSTRAINT_MGR ANALYSIS SETUP/Hold spreadsheet lists only one pin pair4 D/ C+ p$ k4 Q) x' r
1399646 ASI_SI OTHER Should be able to run mbs2brd with SI/PI base licenses! A+ l) R1 S# r7 j
1400215 SIG_INTEGRITY REPORTS cross talk failure on certain nets in PCB SI 16.6
; V7 w: ?- ~3 _9 v 1400302 ALLEGRO_EDITOR MANUFACT Copper Thieving is working differently in SPB16.6 as compared to SPB16.5
; G7 ^, r6 c T9 V9 a 1400755 ALLEGRO_EDITOR SHAPE Updating the shapes on the ATTACHED deisgn causes a short to a pad.& R: d) z; O/ z; d) a& ^
1400813 ALLEGRO_EDITOR SHAPE PCB Editor crashes when you delete islands from all the layers and save the board
2 H- o) Q0 k. q/ K+ j2 M 1404174 SIP_LAYOUT OTHER Creating bounding shapes generates INCORRECT shapes and DRCs3 t- E7 o( a: e4 t( [$ Y
1404184 ALLEGRO_EDITOR INTERFACES Step package mapping - Save is disabled for certain symbol
& V% M$ @( x+ l S 1406457 ALLEGRO_EDITOR SCRIPTS Unable to launch allegro.exe -orcad after update hotfix 046
: N8 F5 e) ^( V9 B- y% R 1407123 ALLEGRO_EDITOR OTHER Lines with zero line width are not being printed in PDF format
9 C Z o0 q6 d5 v 1407483 ALLEGRO_EDITOR REFRESH The 'refresh symbol' command creates an unrouted connection in a fully routed design
. E5 a6 I$ `- j+ I/ `& y1 Y 1408072 SIP_LAYOUT OTHER Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.
$ [% Q( [. I" P6 a5 b7 G- k 1410857 ALLEGRO_EDITOR DRC_CONSTR Diff Pair Uncoupled length DRC gives different results in SPB16.3, SPB16.5, and SPB16.6." d2 S* r& A1 r. m6 n1 V, d: g
1413235 ALLEGRO_EDITOR INTERACTIV Find by Query with Via Structures: GUI freeze% Y5 x1 u' t. n- X
5 X' m3 v `, T4 s) d, u$ c0 Z
DATE: 04-03-2015 HOTFIX VERSION: 001: f: x) ]+ r9 ~+ l+ N; e
===================================================================================================================================* @# v( L' u+ g3 E( ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE4 |9 x! `* b+ }' ]
===================================================================================================================================
- ]- o) S# D/ N" K7 r p 491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute, r6 S4 K7 H% I8 G& C2 R: _4 p+ y
1205900 ALLEGRO_EDITOR INTERACTIV additional object polygon-rectangle for "snap to pick"+ |' M9 }! o: r O
1327533 SIP_LAYOUT REPORTS Metal Usage Report fails7 ~: \5 e- z3 C% W
1341177 ALLEGRO_EDITOR PLACEMENT "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component"; Q" s' X9 j( q" f! d
1360269 SIP_LAYOUT REPORTS Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set1 P) x, `. s5 h! j$ v
1361281 ALLEGRO_EDITOR INTERACTIV Moving stacked vs non-stacked via's should be the same.6 Z1 @1 |) U1 c% g/ Y
1366525 ALLEGRO_EDITOR INTERACTIV Add replace via with via structure command to Allegro PCB
3 b J& x2 t ^' b/ t/ v 1368091 ALLEGRO_EDITOR INTERACTIV Snap pick to fuction should see fiiled rectangle as a shape b4 O$ Z% S* l( z
1371510 APD DATABASE How to show DRC when tack point of wirebond out of finger boundary
# H" o% X2 l* @* P% Y 1373564 ASI_PI GUI Impedance results are incorrect in PFE" v' u! Z/ v, p- F, H; {, ^
1374703 ALLEGRO_EDITOR SHAPE Inconsistent behavior on shape voiding" }" M( Q8 A/ y* S6 N% O7 H8 R8 z
1376851 CONSTRAINT_MGR UI_FORMS CM workbooks change after simulating
]8 Q6 }0 N* A ?4 Y 1377555 ALLEGRO_EDITOR DRC_CONSTR The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.
% \1 d( g' {# l 1378032 ALLEGRO_EDITOR REPORTS Report command and batch mode give different Waived DRC Report results in PCB Editor. t! M; d9 H% a3 k3 b" Q' X1 X
1378611 ALLEGRO_EDITOR INTERFACES Enable STEP export to convert the mixed unit into one single unit) {' J4 x+ t Q9 [$ w8 t, z [
1379240 APD PLACEMENT Placement gives error regarding the difference in units between the database and symbol, which is not the case) n8 \; q7 c& z# ~. U
1394908 ALLEGRO_EDITOR DATABASE Database crashes on doing "Show Element" on selected net; U0 a3 j3 b4 M3 ~* L8 A1 b
1395541 ALLEGRO_EDITOR PLOTTING Export PDF not correct for Phantom lines& S0 i: q1 T# M+ G7 m
1395747 CONSTRAINT_MGR INTERACTIV Rename refdes causes Allegro to crash. Possibly due to CM being open./ z# b+ b$ H& M! C0 E4 q
1396915 APD STREAM_IF The question about MIRROR geometry function from stream out
7 D2 E6 ]. V$ P& t 1398184 ALLEGRO_EDITOR MANUFACT Mismatch in backdrill data with IPC-2581 export |
|
/1 
发表于 2015-5-7 02:28
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主
/ J7 C/ ?$ W/ p
发表于 2015-5-8 11:30
謝謝分享喔
