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CADENCE SPB/OrCAD RELEASE 16.3 README -- ' k3 T& V1 s* J: q* q
Windows Version , A) ~9 A( ~- b7 r
Installation Guide
+ l$ h' z6 F4 D. qYou can find the Cadence SPB/OrCAD 16.3 Release Installation Guide for Windows, Version 4 K1 d1 S# \0 I2 Q9 }, ?! ^6 x/ I ?8 S% m
16.3 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD. F+ i8 u: @' u( f/ p
Migration Information 9 i+ z$ T8 Y2 F. `" w
Important migration information is contained in the Migration Guide for Allegro® Platform ) i0 V) R% g, w( v8 [- r1 G
Products Release 16.3, which is available when you install this software or on Cadence Online
8 O9 M$ o2 D4 s hSupport (http://support.cadence.com). ; A+ M2 X7 M& Q7 M' d# o7 ?
; s4 v. X( }3 [6 {9 _+ y
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
; F( C, H9 R0 ^( l$ g1 _are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. $ A1 {- A! W' }8 z$ A" C
System Requirements
, v" }! ~7 M0 A- r! j5 G: YInformation about minimum and recommended system requirements can be found in the , w: p* i0 x1 s
Documents folder of the Disk 1 folder in the Allegro Platform System Requirements document 0 [6 d( k1 G& V. v
(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com).
+ S* }9 N4 U$ w 4 M: \" U/ R9 }% \% I
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners $ M( Z, V% f) T5 g
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. ) S) ~( I) L' ~- g* V
What’s New
' a A6 S6 r/ T! [Product release notes are available at: M* t. _) O d7 @) v% V) z
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin ocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi[/url]
, I+ Y- ^" I2 R; |ng/spb163/prodList.html
. s( J3 e1 B1 Y9 d' T- f, XKPNS 3 S) Q+ F9 I" u b
The Known Problems and Solutions (KPNS) document is located at:
" Z7 [& p. W/ d% c7 F9 \[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi[/url]
" ~/ m9 o9 X# tng/spb163/kpnsList.html : Z# _3 X Z Y4 z: u& O6 {9 p6 [$ ?
Allegro® /SigXplorer® ABIML Libraries for Default Trace Models
; r0 X, B; X) D" S0 B8 ?% `with Surface Roughness Effect
& Y3 |$ m% V5 s9 gThe Allegro /SigXplorer ABIML Library is a free library that includes ABIML libraries for
1 _. B: t; G7 nSigXplorer default trace models with surface roughness effect. It is designed to provide accurate
* q3 _; ]. z( n8 I2 ~5 I# [( o% wtrace models in Allegro /SigXplorer without time consuming EMS2D solver runs. The libraries , K# R5 k7 W# T) g5 d
can be found at: ) A* \) f' J/ S: u* v2 v; l
http://www.cadence.com/products/pcb/pages/Downloads.aspx
0 ^1 Q8 N/ I) c- K: S& ~This ABIML library is provided free of charge for use with Allegro and SigXplorer. The library 8 r/ q# y: t; ]5 \
is provided as a zipped archive, with installation instructions included. 6 n3 p' ? Z. B2 ?. M+ J
Custom Environments
& `$ J$ O+ e+ D- f4 l& C. Z- WCustomers using custom batch files or scripts to set up their environments must add the following ( q! L6 s$ ~: n( V: P- i
to their path. There is the potential that some Allegro products may not launch without this
! A4 U) [7 [ ?" R( Dsetting.
. f% D* M" J' E( k# U5 Q# E%CDSROOT%\OpenAccess\bin\win32\opt Downloading and installing SPB Software
7 k2 N8 o1 C' s: WCadence software can be downloaded from:
& q1 U8 S+ j0 O+ T" k2 {http://downloads.cadence.com : U3 s1 a4 t* k8 f
# d, c; [. I- z* R# f7 q! P# bNOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software. 2 O9 ` q- `& J6 ^
Cadence Channel Partners are listed at: # A7 H1 z2 {# q) v5 H
http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
4 `/ e7 r. j7 ?3 B3 _7 J" i ' M" `( Q3 `! I: j* h8 v( T
Download Disks 1 through 3 and then extract the zip files into a temporary directory such as
7 U" f; E( b! X2 hcdnstemp. This will leave you with a directory structure that looks like:
. e+ v0 n2 b H- I# M+ D3 H) m
& Y$ L+ ^- N" o- a% y sDisk1 folder * k) X1 `9 j8 n( T
Disk2 folder
1 u( u5 u) V i; V0 O# cDisk3 folder : _9 L0 T5 \8 Y4 E/ I6 x
autorun.inf
4 n3 A9 I: Z3 x) j$ vsetup.exe
# A+ p: D0 z/ A, E; J, esetup.ini
1 m2 B( B* p8 s3 M/ ?
" B1 w$ F( L0 Q* u3 SComplete the installation by running setup.exe from the temporary directory or consult 3 }8 I# B- a: t. G2 b
the installation guide for more detailed information. 3 Q9 w4 Z% K9 K. h
+ D1 `' h# M' a
WARNING: The installer will automatically add the programs in this release to the Windows 4 O: U) Q# b: _5 T8 _
Firewall Exceptions list for Windows XP and Service Pack 2 at the end of the installation
7 O( t& {/ ~4 }( E6 w* dprocess. If you do NOT want the installer to do this, you must run setup.exe from a DOS
6 E+ e/ n% {( J) j' T, xcommand prompt window with the following switch: ( p# G1 [# d5 @% N+ l
5 i; u; K8 u p: r
setup.exe -nofirewallexceptions " b! @3 {9 K" j. E# W
6 W" @3 K$ H' i, I1 j4 {" s) y. z+ y
When the license manager installation is complete, continue by installing the Cadence ' A! ]9 e/ e5 Z
products.
4 L. J3 ~! M' _! y
. t! [4 A6 e- a% K3 T: HNOTE: If you are prompted to reboot, reboot the machine and log in with the administrator . u+ V( x5 ~, H0 M' o7 U
privileges login id to successfully complete the installation. List of Fixed CCRs
. j. b2 B: ]8 E• Enhancement CCRs ' U7 h: H, e( e9 z
• Bug CCRs " Z. K' a, O4 g u8 P* v
Enhancement CCRs: ( l2 x# \7 e% @7 G$ v# g
# P: }4 ?0 A# X3 ?6 K l9 S; `8 [
CCR ID Description
5 y; {* a' u+ k @5 U7419 Customer menu options added to Allegro menus
: J4 ^" P6 |* I& K8230 Use via in area constraint does not work j. r( p4 U$ |8 N
10658 Modify default formatting for Label texts and linewidths * V8 C) U( s+ \
12216 Cannot set color or line width for wires on net-by net basis
' e; G" Z3 O$ z8 z- Y/ ^. F) u13083 flip/mirror design to back side
7 m8 L. h2 P7 n3 p& b/ @! X13373 Select length of pin graphics ) p2 U, A; Y9 ]1 T- A" ^0 S: X8 B
18072 Add docking option for probe cursor box. 4 U4 W3 t; Q3 `- _, ? n. Z$ V
21451 Change Probe print trace color yellow to alternate.
& H4 F1 D: M/ e' {9 [2 A( i8 G) }) {32798 pxllite complex hierarchy netname enhancement ! m4 o, f% P/ |" D- D
33896 Option for changing the PSpice probe cursor ' L% x( \) ~. F/ u0 i5 ?9 G
39600 Option to see time spent on allegro database
) B- B1 g% Y9 b/ [40754 Linux OS support for PSpice
! [1 @2 ?$ W1 H5 ]* s$ k0 Q60427 Add different subclasses for pin_number top and bottom / {" w, y4 p. Z$ e
77555 Capability to export PSpice probe data points in csv format
% o6 l3 ^( x' D8 f* F107219 Capture.ini switch is needed as a Registry entry like PSpice
9 B) S# W& Z1 W7 x0 w0 h- i, s v3 V132769 Footprint viewer in CIS should also show pad spacing info / r4 P& M0 @' _: N. Z2 P6 x
158838 Need easy way to delete marker ! E1 k! ~$ t- R g5 R4 {6 y
159977 need attribute mapping capability in mbs2lib and mbs2brd
t1 e6 b e7 k- X8 S" @162382 Enhance quickplace using schematic page from ORCAD 7 {$ j T$ ]9 h) U7 j) j" q- {
164790 Improve autorouting quality on diff pair w/match length rule
, o1 q' V' C4 I/ }- {4 s205909 Constraint Manager displays in Allegro no graphic mode
2 b/ s$ q; [) f6 }/ g( V210027 Delete dynamic shape removes net name from copied vias 0 }1 B% v6 _# j% d: J$ P7 V
222127 PADS_IN: Constraints are not imported with the design.
- _' H9 O* Y5 t& {+ `236698 Report Unused parts in multiple parts package should be DRC
2 l) I. K0 d; b. A) f$ q: o/ {; s S9 n240525 Add ability to change cursor color in PSpice Probe window , N" P: v2 u8 e }
245193 export dxf height information when blocks are unchecked
) ^ A" v8 z5 X) P/ f254183 Multithreading for DRC and CM analysis in Allegro
- [0 m5 D% W) O. f& o2 r1 f282027 Problem with Split Part and part graphics 8 G, h( N; g) }4 }, G& I( r& S
282507 request to import IBIS file directly * q" L2 I! \" f
283698 place by schematic page number window need enhancement ' j, k! O ^/ z( L0 m
288540 Schematic page# display order request for Quick place
. G `! n L8 D# N290283 PSpice - Probe - setting background color from UI " s% I+ m) I( p% ~) x5 _5 @& v* J
290641 Option to copy paste cursor value
2 {3 H; S1 C. |! Y. d" f V298081 Models from Funtion.olb need more explanation
4 o3 B) K4 H1 k: c323813 Need negation and exclusion function in ADE reports
; y- |% n; P. B% M+ f+ p9 d& i/ Q341484 Wirebond: Tools to generate wirebond manufacturing outputs
# m+ _. ^7 K2 p- C4 ]353212 Variant Name is not coming in Standard BOM 1 C& j9 ^0 O$ c9 j
360602 Enhancement to Show element on a via
9 [: z& Y [% q) m362934 Enhancement for Allegro to utilize Dual Processors. 6 w4 H5 B! B& u
364850 change the font properties of Label Text $ w h+ [& ?. F# N W
367468 Need a real DML_PATH environment variable ; r* x* S" _/ w: a2 p, j, u: l9 P
380714 Ability to have Power pin set to Not Connect + q6 h/ V6 z; a9 i' e, A
382860 Display parts and nets in different colors
9 D: }: F! w, q' q384488 Add DEVICE and REFDES filter to Signal Model Browser
/ C a5 q1 E$ `2 w; }$ l391487 Ability to have user defined directory for storing distribution files for MC analysis ; X) M& i( v# v: S2 P
420008 The renamed differential pair names are different in CM of ConceptHDL and CM of - M% y6 L0 h& I, X" @" W' ?* O
Allegro.
9 d) w! e, w- ~- i4 o, v420023 It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on
o+ N) {8 V* G0 I' s) w% LCM. 420648 Need to get RF Elements to retain previously entered values
- s c& m8 ^( Q, h4 K429280 ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
8 Y, p. i9 E. u! T* j430549 GUI for ADRC XML Rule files
, e2 _6 |! H: P- f Q3 N430558 Store last used ADRC rule check ini and check values in .sip database ; T3 a& U2 n; o4 Q7 V
452606 Can we have last plot as a default ) b2 D: E2 b2 U$ ^4 _
454452 Allow neighboring/overlapping die pads on same net to go to same finger during wirebond
( C* U( Q9 ~ ?add.
5 _1 e8 e) f/ O: i( m* k4 Q456854 full AMS Simulator menu without pspice.ini in registry
. n1 D" K. I3 E6 E& t464056 Setup option to always prompt to baseline a new part ) h- _& I7 _' `8 l D# x8 k
469378 Enhancement : Hide/Unhide feature for trace
% v: y9 @: P1 j% L$ q" _/ Z0 D, @475077 Schematic Generation Setup form is missing the Port symbol selection. It was there in the
) C" L+ } c E$ y- d15.7 release. 0 M, ]. |# s7 k0 |* n5 r
475714 User Guide should mention that Temp Sweep is not honored in AA Flow? & `" }8 \0 Q# D
480843 Requesting ability to View > Zoom Mirror current view.
* |" K& D0 f7 j( {$ V484632 Request for Bond finger to snap to Guide in Free placement of Bond pads
8 l; {2 r y6 } k3 _' K9 p490948 Provide a sketch line and text property form
3 R; n' _: m% L B$ M. |500550 CRef's should be preserved with the next run of the schgen in the preserve mode.
" u# ~0 B' o2 T3 S" T3 h; ^( N505284 Enhance The ConceptHDL can set the color for $XR0 property. % S$ L# h4 ?1 b ~0 O- H
512748 improving arc routing 1 N. V1 a. q7 O, O- w. A2 G- f
513967 staggered C-line via arrays
. B2 p. c/ p! w$ `! W515333 Option to specify spacing between Components in the Generated Schematic
! {. r8 d2 N1 P( G) ?524924 Add PSpice enabled part gnd to standard library folder
' T9 O9 P: D }6 `2 b525748 Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
c3 j4 d6 ^' R( ?1 \- h526818 Retain Hard Packaging Information option does not work for SECs. - h+ P# |) t- z7 t
528391 SigXplorer measurement is wrong ( D# i) b) k7 {4 b6 x; w- N- K. A
533844 Allegro password not encrypted in the .brd file. # \# j2 [1 h3 D) d) R1 b, m; m6 P
536681 In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge
6 A4 W# C9 J0 v4 p; ESpacing
% H; ?& h/ Q: {# w3 o536948 Allow sorting of power symbols
$ i' k+ z5 `: {, M2 L% s539407 In ADRC Minimum Shape Check requesting individual "Layer" option 4 ~4 y9 O J u) [2 c7 Z( W" g* R. U
541145 slide command does not support to keeping the existing arc
7 ?% S+ ?2 t0 l# @" |0 \' `# Q541214 about supporting OpenDrain Model in Quad2signoise
9 C2 l( a6 s# m1 w& P m542414 A function to force diff pair spacing to primary gap.
$ q; K7 a# U2 k/ T542803 A "Minimum Shape Check Soldermask" entry is needed in ADRC
0 f: V0 q) N% C543470 Provide rectangle and line width thickness for Drill legend in NC drill Param
4 U) w1 h3 g# U8 B$ P: }543766 Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks * R) n- r3 n, Z3 \0 g
545408 Cursors are toggled off when deleting a plot
1 T1 ~+ U3 U4 X: o' D9 G546891 Enhancement: message improvement when expand design action in Concept , ?7 @" F4 F6 v! ]' O0 ~* f/ P5 @
546985 XOR function to allow to compare layers within different or same designs / b6 g3 J+ C$ v- Q. F
548920 Add a document of which properties can be synced and which cannot be and the files
$ h% w) W7 ^8 m4 Irequired
6 w$ X: T; M1 o! R- W553669 Add a 3D viewer to Allegro & o: C) s% Z" s$ c7 c# @
555183 Wire Bond Report --- Report field should have save function for reuse
- P4 S5 b9 j$ Y z7 K) |556200 Need listing of DE HDL command names and switches.
4 Z: R$ [/ v* I2 B556883 Grid point for Origin to be highlighted $ n, M: c& a+ [# ?: I+ h8 K0 n
559638 Enhancement for importing height from PADS in allegro
" s6 H* t3 q/ ]( k( i W& i0 A559724 Request cline via arrays to be applied to diffpair nets
4 A2 Y' \" D1 N1 ~560134 Show Element Customized Display
, m) v* ]7 O: J: ?563957 Enhance Color Dialog form Class/Subclass section to expand vertically when the form size - F* f) t- V6 r# F
increases.
' i7 W' [, j5 U/ J s568058 Request to have component information available through the context menus
; R- Y/ q1 z* b: S9 m3 `% ? ^568273 documentation of variables in Capture.ini % g( a7 t& j" x: { g5 l
569615 Enhancement to import constraints from Mentor Board Station to Allegro PCB
J1 r) @+ s- ?# o- K. L569680 BOMHDL defaults to the wrong file type when html report type is selected 0 O1 G* N6 h7 B' r+ s, K
569784 Request ability to assign netname to via during copy 7 {9 X( u. S" \* f* _, ?) U b% G5 ]! F
569863 User would like to set a larger default trace width
; R ~4 c) R. c5 u570128 Enhancement : Packager setup for subdesign drop down # e7 x5 Z O1 p' y
570195 SiP - Provide option to create/combine BF labeling with additional text required for Bond , c& i9 J* ?& O6 Y
diagrams 570861 Unconnected mark does not be removed even after wire is connected to the pin.
- c) T" B Y7 O; v' Q6 r575211 Web links in CIS explorer are not working when Firefox 3 as a default Browser
7 e8 T: n0 }+ }7 c! @577944 Enhancement request to have the drill legend for thru holes and slots to be separated without
3 `- p. E( p$ u: z1 ~being on top of each other
6 q4 i# @+ q8 d5 [% _$ s583630 Can Multiple Section pop up box be disabled?
! k, E6 t4 ^$ @+ X4 N583712 Ability to have string values for SCHEMATIC_GROUP property
3 }5 J- Q( I: U2 O) L- u585904 Find a schematic page with help of nets
% H" f( Y9 H, {; ~9 G% z589316 Document change in Gaussian distribution for PSpice MC from 3 sigma to 1 sigma
* d4 h: \ O1 e& t' { ?6 i589512 RF component snap is 'too clever'
( @, G6 I2 G; b1 ~590246 CIS to Allegro flow to include or ignore constraints same as HDL to Allegro
4 Z) C* x) Y; a* F& ?! x+ X, [591306 Suppress RF edit window when changing RF Element properties ' J% H; I, Q4 U% n: z. `
591318 Use RF setup values or retain changed values in RF Element forms 4 j9 ~% @7 j( s! C
591443 Temporary highlighting is lost when using the Copy command ; e% G5 I# x* y1 Z& E
591450 Provide a dynamic tapering option to RF PCB Route ! u. o! P4 B/ A' {4 |4 j5 w
591489 Would like to suppress RF Snap windowing around the user pick automatically ! c/ S: n7 ]% G1 E$ O5 r
591812 Provide move options for the RF Snap command
" U+ i5 K! s! q$ a# p) U1 M591817 Provide easy group and element ID in repackage form 0 v1 x: H4 b1 O% F9 r
591825 Quickplace for RF Elements
6 Z+ Z$ F8 @1 q591865 Request for more information on 'Other' Netlist formats % M* `1 G' _0 q- u" @4 r
596392 Publish PDF needs improved error messages for missing installation. % w2 O; b: j2 Z: l! Y3 r
596555 Request alias symbols documentation to include and clarify when necessary to rotate 180 2 D2 v! N8 F4 ~' H
degrees
, F/ e) _7 M% K( _" L, M) I596843 Cannot do global search after importing read-only schematic block " g9 D# R5 K+ T- d. ]7 m' m
597808 Option to increase the default thickness of all traces in Probe " k; P0 v2 T% c# c. }
599499 Plotting from within Allegro does not find path to stipple file
/ i1 l: F. y! o7 Y. z1 d604125 Manufacture>Create Bond finger Soldermask.
0 }& c$ D5 g% x# L# |4 |3 W605023 Need rats by layer function for Free Viewer ( Q. P6 L) C. A! a
605112 Dies should not be counted as conductor layers in Design Summary Report of SiP
) Q* I. x. c) Y7 r+ g0 }605373 importing and Exporting BondWires & c4 w9 ?) f2 F" B+ R
609035 Voltage_bus part - Make pin number invisible
2 o, ]) u' j. K# c! ^1 E; D609561 Enhance Circuit Replicate to support coppers shapes connect lines and vias
: m6 ~3 W' R" P+ q6 @6 k. z+ V610934 Retain user input values in RF PCB forms
* U) l9 t a" A9 \612008 Mirror Rules need to be documented for axlTransformObject.
; o, ~$ _6 k. S. _3 M4 ]6 L( A613639 Update Documentation for "split_inst_name" property. 6 \% A: \. J5 ]- W' K3 ?: V/ ]5 g, ~$ t
614345 Email facility for Design partition on Solaris does not work
% M! ?, p9 Q0 F0 T5 C% Z* `( h8 @615139 option DMFACTOR documentation missing in pspcref.pdf % V* C" J2 u W0 L; B
615374 Retain Soldermask Thickness value in 3D Viewer Options # B, p% C7 [' `" ^
615850 Auto Setup should honor device setup parameters if component value is null
! j, I: R( T" I1 }4 ]615988 PDV WHen importing from Mentor does the browser not remember the last location of
6 A! T! H+ c; V# f% b. nimport
+ {, a$ K- ]8 h1 W2 I+ R3 z8 V616529 15.7 Design Entry HDL fails with Out of Memory message
M1 U4 g. @8 K) ]! w+ j616873 Uppercase characters in design name error should be improved
" r2 q+ \$ m4 g4 x617976 Enhancement for a way to sort user subclass in define subclass form ! P- x ? _9 u8 L9 q7 x
620289 Server 2003 support information in pcbsystemreqs.pdf
/ w' _! B6 o1 Y* A# s, S; D620303 Enhancement: Shortcut key for "Select Entire Net"
; |5 P9 i6 k0 @$ F* }. q" E; i3 s621054 Renamed net in netlist isolates components from the rest of the net. * x: i8 `6 p# F7 |3 `( n% n
621955 Offset Via Generator utility should show a warning message if vias are already present.
( N* `8 {/ x# H622203 Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar
, h# d* ~' U0 A/ `: bcommands
, q6 A) {; X" R8 e. b% z623218 display pin names associated with a net in net Properties 5 m$ l, z. o: R( r; G
623908 Mirror Symbols while dynamically moving enhancement # [2 }, N8 d; l" K6 M( `
624817 Display padstack name in data tips when hovering over Pad-stack
+ j; [3 W" [' m4 t% w625733 In Netlist Report they are requesting square bracket vs angle bracket
! K- t" y! v4 W4 I1 o" j626605 Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB 1 D* M8 V. u+ w
XL and PCB GXL
7 K- q& G0 S0 Y. v" d' P626673 16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows
' Q! I: f" [# x" @- m( a& yrotation and allows move but ' C1 h: e5 P; ]) D b, C/ A
629008 enhancements for find command 8 z6 W7 w/ [/ X3 |1 a
629548 Request an Option in Create Plating Bar where it may be directed to a different Subclass 630949 DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire 9 s& H. Q- _/ C! S9 ^4 b
profile"
' ^' ]; L+ v' `' A630955 SCM does not see design difference after update of fixed die/BGA in cdnsip
- E* l9 ]/ ~1 J. R630973 SCM should see the net assignment made in CDNSIP for Power and Ground pins ) w, q8 e; e: c
631609 Clarify how to generate a cref.dat file in Cadence Help 1 x0 A u3 I9 ^0 Z( B
631697 Want to degass many shapes in succession with custom parameters
' S/ Q+ F; _$ g4 t& O8 Z632754 pspPN and lib_list should reflect location of new models in 16.2 4 H3 Q) J) ?( t
633440 Sensitivity not varying components correctly
0 ^$ Z& {/ v/ z633842 Add note to docs regarding padstack quickview & F; R2 c4 q$ \" A
634350 Enhancement suggestions for pop up info boxes. / U: X+ s* [3 t4 y3 _
634877 Export netlist with properties changes scope from global to local
3 q! y& e0 e+ r/ l1 P0 |635118 SKILL variable to obtain list of Classes and user defined subclasses in a database " {/ e5 k" C. g7 j
635233 Place hierarchical pin tool tip $ ^1 f3 F4 a+ ?3 r. R7 n/ B5 C
635543 Any command to get the current line/lock type information?
1 c. I3 F6 q f; A; ~635579 Enhancement for Structured format in parameter file
/ D- t9 b c7 H636930 Die Export option to create symbol either from schematic or layout 8 N2 Q7 X7 p( e- x
637195 Allow for SKill access to backdrill info on padstacks % c' T: o W ^6 d; G# A* w
637768 Enhancement to assign different colors to different net based on a unique property
h* X( ~& p. R) _) Q638455 Enhancement: Add some details regarding nomd.lib + c$ Q W8 x0 }. `6 y. h
638581 ENH - Press ESC button Spreadsheet window disappear
) X/ g& g1 m* a2 h638622 Add note to CM Spacing Domain Region worksheets regarding shape2element clearance & E8 R: G; V5 p- ^9 j/ \
638910 Enhancement to sort the list of available vias alphabetically in the via list ? : }7 ?: X" z" X# c8 Y' C9 d3 D
639630 Does the Net_Short property work with Modules? 2 Z. r4 h$ A# L
640262 Request object membership count in the status line and forms of CM. 5 ?; }" V4 D, l; \8 Z8 U$ S& t
640280 Provide resizable windows in CM and other apps
6 {6 D3 p$ R% g- Q' x$ ^640668 File>Change Editor needs ability to go from GXL to Performance L or Design L.
4 i& a% r1 f: |( P: J9 Q642095 Ability to disable the Pop-Up description of elements
0 r0 _' B2 F1 Z$ V( {: h642298 ENH: For license checkout detailed message ( J3 r! ]' [; @1 X9 A7 k6 {
642422 After Copy parameters from one part to other in partmanager forgets previously highlighted ! |& I, G D( _% Z; X
line 1 c6 W5 z9 c9 s4 J9 ^3 Q9 N3 }
642865 Allow format of hyperlinks in ptf files # z9 W$ Q; h) N9 c) P/ W
642894 ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help / r) u, ]' V3 O& T+ T
643381 Add an option to ts2dml to allow user specified port ordering. $ y, [, f# O2 |! ^
643390 Request for a switch or button that would allow Properties to be maintained during a shape
! L7 s# Y& m6 g5 S0 qmerge % q; @" {7 t" J: u" S$ W: _7 v+ @
643625 Bond Wire export to DXF does not support WYSWYG 0 }6 `; J: _' w
643790 Include Associated Components in the Verilog netlist ( J& X. E4 U3 Q3 u: K" [
644216 Store Filter Row Data and Units Of Measurement in site-specific file. ; q( K# l* `! w. _
644248 Need a better solution to identify and handle unstuffed components
2 W. b0 q" B3 c% M* h* A* T644350 Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual
- Z7 ^! h8 R6 H0 P$ w4 \# _0 J; B1 s646662 Enhancement to add feature to toggle on/off inter communication tool from within PCB % @/ i8 ~' ?8 {4 P* w& k! l! ]
Editor when using DE CIS. # j5 s: P9 B2 S6 A5 T. ?2 s
646981 about the treatment of NO_GLOSS property in Missing Fillets Report 8 L0 J3 S( w* m
647480 global setting for adrc settings in sip via techfile
$ x6 p( x) o: d9 ]& ]$ }647617 Degassing not suppressing shapes less than size specified
& q8 I: y! n0 d/ ]/ \4 A648210 Request for Working Layer (WL) model in all tier Allegro tools.. * U6 R( J/ A' V S/ `, k
648218 must delete keyword "multiwire" from Doc
% `- w' @4 B1 _* O) u648533 The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented
) f% K$ ~2 y& ?- M8 p3 p0 M648801 Stream Out issue for SPACER
2 }5 B) G f \! N: y* r( E648930 If two PPT option set names match a given component which one will be used?
0 v5 Y8 L7 O' }7 L8 p7 B: f b649603 about spara import
! v! w0 D% j4 _' Z, U4 U1 C, _& p1 R6 _649607 Management of SiP Technology File and Project Information
" s" j/ M4 g" k, w! P4 {649610 Management of Part Table (PTF) Files
5 p) ^; }+ S: Q8 ~/ V7 w# h649613 Management of Library Lists + t, l; H" ]% m5 |5 F8 M0 e
651684 documentation improvement request on cross-probing in Capture to Allegro to Constraint 4 L d3 J/ y9 d! V8 q* Q5 ` ]$ n
Manager 7 ]1 e7 x2 p- ]$ t4 S4 [9 Q
652335 Tooltips clutter Place Part dialog.Option to switch it OF and ON
1 s* ~4 d( S7 D6 L: I& T) e' @652511 Unplace Component command ! g: A- w6 [) e) Q+ e+ ]
652547 Description of ForceDBArg1 should be added to PSpice Users guide 652554 Enhancement request for Allegro to check the vias used to the allowable vias defined in : q( v" N; }( C9 @$ w
constraint manager
% x: _( h; O# m' R( W5 p8 i1 B652939 Is there a way to predefine the values for Sample Start Height and Sample Start Length in
9 U/ u {; V. K( M$ C3 D, ^Wire Profile Editor? ' v( Z, ?2 ^; P1 y1 p
653027 Explicit RMB "Done" option is required in Part Developer symbol editor when editing text ! V7 |) `" }! w+ S
653359 Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using
6 E: [9 N4 H+ N8 {' Y' s# B6 [+ k5 mthe section command * z @3 F5 B3 `1 U1 s
653420 Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined ! _6 F& u# e; ^) m; s2 h& ?
minimum constraint value
7 X" I. W9 x$ S653471 Request for Die Text In Wizard option to Flip the DIE coordinates
( Y" j. \, l% j$ U. e653825 sigxp_tier was not reset when installing a new product suite ; ?9 y+ D1 l, f- Y' {9 A( z
653902 Enhancement: Print Option? setting in Capture.ini file ! b- g) Q0 l2 W" y4 I# Z
657180 Enhancement: Tooltip for DRC markers
! c" u; z' S) D! u& z) Q657187 SI model delete enhancement
" g# y' T0 H0 T- H657189 SI Model assign enhancement #2
8 P6 ], v% h- {1 b3 x" I2 x657501 Negative planes doesn't match with Film View 3 C) V" Q5 R7 _' B" o( y
659543 Need a Report to show which Die Pins have no bond wire attached
5 E* P! B& P" O, I& s( V5 b659661 Function needs for setting the rotation angle in finger by group. ' I/ ?+ E6 k: G! r
661477 Color192 window sections to be resizable
6 \( n+ B' G) N" N& [4 c) q662215 Please add the function of renaming net by batch command.
- L) k: R! b2 Y. c$ c662325 Skill code example axlDBGetProperties.txt not correct 4 ?7 I/ j* D q; \0 S. k% `
662982 When you edit shape, ministat should always enable shape : w/ d" ^/ o% r7 w) Z; p$ w! z3 u
663260 Enhancement: ALG0051 message should be more specific + E, ~: ? l" q% R4 v/ j
663754 Enhancement to create Device file when saving dra file on opening another design ; M' G- _3 Z9 ]& h. c
664240 Add CNVPATH in User Preferences to place default CNV files
2 z1 v; }! U, _665798 163BETA - provide graphical examples to show result of Flexible Shape Editor actions " f& q% U1 L* P7 Z( A: ]3 o4 M6 {
666186 Enhancement FishEye functionality in Variant View Mode D* w- n8 F4 o' b- Z4 J
666768 Temporary graphics for modules / groups do not reflect true size
7 j- E5 v9 S2 i5 c5 R. z! Z666775 Update microvia to microvia DRC markings to avoid upper and lower case confusion 9 m* h0 B2 D2 k4 a; D
667773 Request for ability to set grid definition by entering simple formula * O1 Q7 ~) X w7 s8 x, I1 }( N
668110 Customer wants to enter the value of radius when editing routes.
6 n) q: n* C8 u3 d* r( n669373 Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design. # N# V; h1 I, G3 D4 J
669380 Add options for ts2dml in MI 0 ^% \, E. m: p5 e# {( ^4 @
669798 Add all 5 Dyn_Thermal_Con_Type property options to Via_Array. 3 }0 F) Z; O$ g. w1 W8 \9 M5 m
670775 Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public % C R3 v3 a1 ?, \6 j: O
671194 Allegro not to crash when opening unsupported files ' V0 e9 D+ m# \; {
671337 Request performance improvement to access DML libraries from SigXplorer or PCB SI. 8 N1 E: Y6 c, [* W" A
671757 Handling of double quotes in HSPICE subckt.
$ g. P+ H! c' _" G: m672930 ERROR [DRC0039] Tap may not be connected with the bus Check Entire net 7 P" I" F* S6 s' m0 ^# [
674666 Report the wirebonds XY coordinates
' p0 K( ]! b* ~+ c, n# i% M, } r675118 Cline change width command enhancement 6 h1 @: C5 A0 T/ ^3 ?
675151 Insert comment option for database elements * y) E- S$ ~0 L! {. X1 f
675398 RF PCB setup should automatically point at the project file if Allegro is launched form a
: b0 y; a6 `1 f. Zproject manager
2 f; `, N* |6 E. K6 j675551 schematic to sip layout fail 2 k ?& p+ l9 A( Z$ l
676814 Signal Library command with Allegro performance license. 3 d9 T7 p) p. g" U: I
676906 Add switch -regenerate_xnets to the dbdoctor dUI
. r" X, I* J# V4 o4 }' K6 U677983 about setting of ibis2signoise option "-d" as default
2 S) O; q5 O6 J+ j* ?2 _678036 Request for a Physical design compare.
' h4 G5 ?; ` L C8 h, ?+ b678798 Identify DC nets command doesn't remove the RATSNEST_SCHEDULE
- Y# y6 r; U7 v5 N( c$ `679926 Testprep fails with no route keepin. Message in testprep.log ambigious at best
, a8 s' G- W; [' N8 G680586 Explanation of functions and macros in online help 0 J# y, @ k( s4 O# b
682098 Color, font, Text Label in PSpice Probe Window " }7 r) A. _# r3 T7 n0 P
682695 Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs / E* J. J5 ~5 t V7 O6 F1 [
rephrased
: `) @6 h d1 e x5 ?# `" u682865 When using PTC format IDF files don't use forward slashes.
, g) U8 i* |$ l0 l S6 R684409 Add info for non availability of SIGXP on OrCAD Demo version
) T }: s" _% \& |& {684713 pin_count view needed for packages
8 R9 {) q" W: y( Z+ D! q _684796 do not delete all vias with DRC for via array 686103 Replace vias evenly spaced apart + x# ^- J6 b0 @% e$ b+ S e3 U
686112 Add Connect and Slide keeps cline length
% v& j! d, l' g6 i0 Y686122 Select objects by polygon
& I1 _, T; M( F687155 License for batch signoise command
- `( w1 h9 a7 {3 n1 _' i2 q8 S687187 BGA Full stagger matrix wizard generation ; ?* e) r9 W' V( o/ r4 v
687201 Improvement in Find feature
3 h* d7 x* O8 o& O" o/ k9 G, u7 F687685 Documentation of new properties in Variables block 4 w* g+ A; ~: ^5 Z- e0 M4 g+ b
688047 Include blank space in pin name as the illegal character in PDV user guide
5 E$ C- B, J, Y/ e1 L7 b4 i7 R688830 renaming feature discrete library translator
6 e* S% j* [ {! p9 W3 b689720 Need the ability to re-center Vis's in center of Pins when a Die is changed.
K# Z4 ~: S# W. q6 c# {695957 master.tag generated from the table design needs to contain the verilog representation of the ) b0 |8 Y2 P7 `: m5 y2 c2 P2 U
sch.
/ K4 m }' T3 J: @+ `- z696661 Add ability in Offset Via Generator to add vias per a given Net , ^+ D. N$ \* k+ E5 @9 n) z5 @
696812 provide description for axlCnsPurgeAll() skill function in doc
0 i" g I9 f) {, ^- C" S0 D/ m; L697824 Components not installed of variant design should not be extracted into SigXplorer.
4 A. G- k* v$ m9 S! V' P3 {698097 Color Dialog form (color192) does not resize correctly ) x7 q1 T* V8 T( {
700262 Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the 0 U, P, T( c- ?% R+ S9 x+ W8 Z: P
Allegro PCB SI -L tool) P7 b9 b% d7 X" T0 l( n3 _
700712 Defined pin locations are not used when using Die Text-in Wizard with default option
' E0 ?$ {% U. F% Y+ q- wCenter pins on symbol origin
9 e( e: |3 o# b& l5 ]701514 axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap" 6 {$ x1 n- |! w2 i) v" h: Y
701810 Document what all database sources are supported by Capture CIS ) e2 V# L. R( \
702190 Request support of Windows 2008 Server Editions. + P: ?- g& ?9 r; F4 o: g a
702613 Request SaveRefdesModelAssignments support the include original model path option. ) I( {. O7 t" z0 V
703905 Need Hot Fix number Info on Help >> About
7 h! W" b5 X* I: y704594 Update symbol removes the text present on Package_Geometry/Silkscreen & f/ A6 ]* Q; p* _
704899 Split Bundle Methodology Should Include a Next Function # b" P% I5 O1 Y7 E2 f6 E: s
704904 via matrix should be available in Allegro L and OrCAD PCB Designer P- E. |: `, s& l% [$ o
705601 Please make listnindex a public Skill command * Z7 h# ^; {) V
705615 During Updating Symbol the text location and size are changed so Reset Text location is
4 J: H1 O4 w: a V- q' econfusing
; j' J, e- I, L9 ?% l9 i, }706165 idf import fails to expand drawing enough to accept text.
% e$ p/ _1 ?4 X+ Z3 K' H; h; k706457 Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
9 e) u* F4 {! }+ g/ m6 _2 l! R6 }706463 Add optional Character in the starting of each line of the file created by axlLogHeader ( P. g* x0 U% B
706787 Fillet should remain when user slide the segment far from pin/via.
( o8 v; y( J! D1 q% {* ~' n709119 Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via ^7 i) p$ r4 t. ^. s d. \4 p
Generator , p' x( B2 Y' T0 c
711837 remove the comma from the image of grid value separator
( V* ]) Z( W% g5 C u; w8 P714840 Enhancement: Anti-etch can be recognized as Void element.
$ d& ^, _2 q: S4 a1 ~# o715454 Option to configure Design Entry HDL for Cadence Help / j4 Q5 W. x% n5 I2 O4 U
715713 Enhancement for Wire Short Check during move feature
6 K1 y: J; Y; W716671 About the log file of the na2 interface.
" I9 y6 A% s3 L' A9 b7 w5 R717722 Pad designer File > save as should have recent file name in file field
1 }9 Y7 e" L/ n, {& F6 T1 V4 j718431 Enhancement request to have DRC checks on negative layers.
0 k0 c' V7 r3 d1 j; T, x7 t719050 Log file should contain username date and time while creating or saving .DRA file
+ _$ L9 w* T& C719514 Request length column be added to the Dangling Line Report $ f; B: Y$ v. o( i$ u
720297 about "rip up thermal-relief clines" " l! m8 j# W( @/ D6 T
722346 DRC checks for mismatches in labeling Net
4 c) i3 ~. F, K0 ~0 X, A723661 Add *.pad in the File of type drop down menu when executing QVUpdate # h; F1 }& H0 P2 | u \! _4 e
724832 Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 -
p$ J2 v/ {! }nil)
5 [9 @) Q3 s- z5 w) V9 f726057 Request incremental DRC update when enabling DFA constraints. : p6 K) }' q( y+ d) {
728908 Add Color View Save and Load in Symbol Editor + k" u# o- o2 B
729947 User would like a metal usage report
# n7 \& q* d: }2 X5 v( W! Q
5 |. X, P! J! W" G% m& ] * Y3 M3 {8 @) a+ c
$ M" I. F/ l7 W. P' y( j7 R7 D Bug CCRs: 3 f! s# v' `% b2 ]1 I
) S' y o+ L( o7 B2 |6 H
CCR ID Description " \+ n, @+ _8 @3 ?+ o
10116 Add Intersheet references does not work in Complex Hierarchy $ D' _' c! C8 x6 n( i1 J3 c
11833 Junction not automatically placed when it should be.
5 k7 V1 m5 c. s16310 Simple hierarchy, intersheet refs not refering to H-block
- p( \ h& f& Y3 s/ n19343 Request for intersheet reference to show grid reference zone
, H$ F5 M% E- f8 r, X# a2 v22424 Intersheet refs wont work on imported off-page connectors & a l" ^6 C# O( ]( o8 K- Y$ u
34275 Ibis2signoise fails with legal characters in file ) L6 b0 f) ^6 x) f7 M
85735 Cref annotations of the P_ID+00 Bus were missing
% U7 w: B9 J% u9 U+ N8 d% p118279 PSpice command line options problem ) j* O8 v3 d% `$ r* w3 w4 s; C
134692 DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
9 v0 P' f& [5 K% m6 \" T" n136260 Problem with netlisting the design in PSpice
& `+ M. O/ h+ t8 A" ?199343 Stackup-Aware SigXplorer - n/ V+ [( B+ d9 H6 ~- Y
207620 Part in MISC2.OLB has incorrect pin out
' C# S) M" e) ^& Q270347 Changes to AXL SKILL must be Documented. ! N8 v2 V* d- [- g" n1 e6 b7 o: `
283839 lm117 dropout voltage is too large
3 ^; H9 }7 _; f) O V; [. U5 }296826 Variant view displays library property
3 t# [5 {" ` f+ ?# I. v; v299384 Part rotation resets the text to default position
2 A4 Q5 G2 |7 n: |( X5 J328647 Replace Cache takes time for network libraries
( p! I" f. r+ Y7 B& @% E340323 Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill
, N: y5 [3 i% ~4 T6 K9 l5 S341035 Dynamic shape fails to fill in design that has cline arcs . g8 ]- C5 V# r8 n
390692 Via not getting transferred through the Area Constraint from Allegro to Specctra
" E( p" }; g& L7 E2 ?( q405611 Environment variable for SIGNAL_INSTALL_DIR is resolved. ! y$ r9 w' G. a1 j
428261 spaces at end of pin name Could not create new pin inst library correction utility
) Z) _+ B& h3 W, F8 E5 O436908 The color dialog window will loose the vertical scroll bar after being minimized. " Z% j1 v: x" s$ o# E6 t- F; X7 k$ }
437369 Menu selection of Export > Libraries fails to issue the dlib command. 3 G+ n. A2 m3 _! s
462783 Busname is too long
1 ~' }! |1 Z7 E5 {495671 Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE ' f& [" d" _7 P: L) J# j' I. U, w
Props. ) T4 L% s( g: w, ~; X8 `
509393 NC drill legend copies null nc_param.txt to current dir.
8 G* L: m N t- _& r, X512809 Window Prt.part.ptf shrinks by 30% and I have to maximize it. , J) F6 _8 y0 _7 K0 ]; V+ K3 E
520802 Global Navigate Zoom to Object needs to remember last setting 1 t5 M" @: l/ {3 R& w
528686 During text edit the cursor overlaps a letter rather than in between 0 H# r* `8 D% W1 U. a- |5 T6 g
531555 The diode BAV99 from library works inverted in compare with the graphical : h! h F$ Y: n
representation.
. ]1 ~3 I6 N* w9 L+ m& \9 T; L( w532603 Specifying TC1 and TC2 properties does not seem to have effect
# w" q, j6 g% w$ ~8 X547339 CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor 0 G U4 C5 q) Z: w$ o
548143 Dynamic shape on Etch TOP will not void properly. ) y8 }" l- T2 X& ~/ T3 @7 F
550657 Importing registries do not setup printers from MWcontrol - K* c8 y! m$ i1 R) _9 [, |
552227 about die export padstack layer mapping
3 N. k, D* u% V& w8 V& \4 w553035 Cref Synonym and Netsbypage reports do not match netlist
$ C% {* Q7 Z( K: ]- o; @: l557660 Incorrect value for I_sinusoidal of pspice_elem 6 E' `+ N% O# h* z' B* r
558164 All variants are affected by function regardless of being called for
" L8 N6 I3 ]3 A* _" H' K4 H558692 Memory leak problem in loading marker files
Q, Y) @1 L4 O$ K b* ]) x1 A565681 Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it
3 t4 l, \* s7 j8 \$ U# mshould. 4 w' F3 G$ Q; c" R2 o6 L! x6 |3 N
567606 PDV selecting pins in symbol editor shows pins off grid during move ! u- X# N e9 L' I
568049 Genview crashes & s6 L: [8 g) c! p8 t5 n! i0 s* [# h
575353 Large box displayed with place manual-h and no RefDes variable set
5 {$ p9 y P; B- Q" G581848 not able to edit Padstack Boundary
" A8 a6 J- v5 y! C591847 Add Intersheet References does not work on simple H design. 2 {6 G) |9 K1 Q1 ]
592381 Physical Min/Max line width values not check on internal rows or forms.
2 s! [* X( m/ X" Z B1 t593076 Cannot redisplay an invisible OFFPAGE connector's name
1 L4 W6 b4 B& g5 m2 o3 S2 w2 r598038 Detail button of Markers window with 16.01 " H! p, J& r8 u( m; _1 v! F
600967 wrong order of nodes in PSpiceTemplate for part AD8138/AD $ d6 h: v0 c& r
601415 Allegro Design Entry Tutorial corrections. $ i% ~2 O! l( C' a! E" O$ c
601531 When using the place manual command and rotating part a ghost image is left behind 603181 Formula to calculate the Actual Temperature for Smoke is incorrect. % L. t6 ]7 X* b& I7 Y
604965 need to document how tcl cmd addComponent handles property values with spaces 9 i; d- M* z8 b6 V2 M) Y
605843 Aliased nets do not fully dehighlight when next net is highlighted & w+ R) w. f9 c7 n; g
606493 Targeted nets are not remaining targets + t3 Q4 d; I. T, g& T" @% s/ s
608150 TestPrep generation is creating DRC errors
/ Z( a- L. v n3 L' A9 H5 W) P608787 Missing Constraints Report
0 q! }# |& o r+ l5 m, Z4 v608942 PDF Publisher output misaligns text in tables 5 c D5 l/ p2 A5 N4 i* u: ]
612511 Error in Flow Tutorial regarding checking default user units
3 S/ u+ {: X$ f# m+ q) S612982 VLIM model giving error that line is too long
9 A+ G; u4 A1 o. A1 G5 v613194 Adding wire bonds with current selection does not yield DRC's, mismatching Allow ) G+ T! V) s4 O0 j4 R! p6 [9 B
DRC violations option.
% b% @% b* U4 J; s. A* d9 |; t613738 Variant BOM report lists identical parts in separate lines due to POWER_GROUP # V- _4 |. n- H+ z' d
617146 Symbol fails to place through Component Browser
: K4 P$ w( D7 v& D3 p617327 Change root operation results in SCM crash
9 I3 X2 P$ g1 Q: M* e7 v3 O$ C617784 Trying to open page 2 of the design Capture crashes
& \1 v9 N* T8 A( T3 C4 m9 S/ {& Q618150 Property Editor Functionality
- M# I* b/ G* j. ]+ G! ~618617 Enabling strokes requires checking/unchecking options boxes
, L+ ^( P9 i: x# ^618771 PDV error SPLBPD-382 when importing from APD.
" ?; \2 R9 Z* d. ^/ @619053 Diff Pair problem with creating them in DEHDL. a9 W" K% t5 z5 m2 t
619849 Hierarchical Blocks Loosing reference
8 K0 t. C! e& a620001 Measurement's Maximum range calculation is not correct
" C; |0 w: ^( T0 O$ n. O620343 Bogus error during schematic write
$ K3 k) Q* u% V3 E J3 ~, Y620826 Changing the units of dimensions does not work
+ c, U4 _* P9 W3 E621072 Capture CIS Crash while configuring Database ' G0 n4 N" M v
621163 Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire # `1 D/ Q# c8 o$ n/ m6 m1 Z
to bondfinger optical short
7 @* V& J3 d( A$ h) J* D622263 Drill Customization sort order for oval oblong slots should account for Size Y & b" j! Q+ d/ K$ E+ m
622583 Allegro produces erroneous error msg - symbol not found when the placebound is too 5 [' ^' S3 w4 n7 a
large for the board.
- l. T; R v5 _; K% K622692 Why is VGSR negative for N-channel MOSFETs ! w# h( j: a5 J) `! N
624378 Device file content conflict + G. \4 E, o. N* v8 r$ }
624492 Model Editor finds the wrong model definition for BAV99 5 o3 k. e! x D' [7 q) ^, p J
625462 Symbol pins Property are lost when once stretched ' p8 Y; P, b$ ^, u$ y% q q
625519 hspice_mt is not used in Channel Analysis simulation
: q& n$ _3 M3 _# U626674 Allegro CDS_SITE setting don't appear to match documentation 2 u, X2 N$ I" b& s5 u( V
627018 Find Net in instance mode displays twice % a# S$ z: Z6 U% T* n G' Y
627864 EDIF c2esch crashes & L" [9 F9 v7 ^& g& ^
628077 Degas not voiding correctly
' u/ j! Y, g. u: \628265 no "Unused Blind/Buried Via"Report in APD products
, F- V8 U+ i/ u) n' ?8 n! s+ X g( ~. B628845 Markers> Packager menu is unselectable even after pxl.mkr is created. k Z- N c7 y: n3 ?0 ~: W
631344 Mouse Wheel Scroll misses the "along with the Control Button" * g9 X! t/ \- c* M
631792 Design Compare not working for OrCAD PCB Designer.
+ P4 }- V$ e) i1 Z631910 Capture hangs when working with search option
, |$ Y$ T8 K7 C* X633084 controlfile for OrCAD installation does not work with PO100E and PO200E
3 O. T! w6 }6 C1 L633086 Generate Part for Pspice Model is incorrect 6 i: h5 K1 ]; k( @
633130 The Verilog netlis is wrong - W4 J4 v" A. Z" B; n; z1 k
633223 Running skill from a HDL script causes segmentation fault. ! y/ }8 P0 o" @! q9 N. m
633473 INPUT_SCRIPT inconsistency when removed from .cpm file
9 H: ~# y- D1 u634075 draw_etch_outline doesn't work for circular shape/arcs " _- o1 L. t# m- @5 V
635779 Allegro OpenGL distorting text at certain zoom levels % Z6 p' `! z5 T: ^9 c: P0 E: t) U
636156 Unable to convert SDT Schematic to Capture Design
9 C! E* r% w7 U3 ~; ?# ^8 ~636215 Allegro documentation for Export Parameters is incorrect + F# g# q+ S3 f3 D: T
636585 Rotating components in Capture reset property position 9 Z) _: Z( Q7 I+ P0 g
636688 Signal Model Assignment UI and Find filter association is broken
& }9 S; Q6 q1 Z5 d6 V, x636819 Documentation wrongly indicates that DFA Analysis in unavailable in XL
: X, f: T1 Z& @$ ~! M* v637379 No column for ROOM shown in Constraint Manager
! P* s% [1 Z8 g' q638140 Intersheet References not offsetting relative to Port 8 U/ z1 g& [; S% Q3 W
638670 Testprep parameters - padstack selections - Bottom Side replacement text not entirely % b7 u8 p2 y( g8 ?# Z+ k
visible. 638987 Change command hangs on customer?s database
3 B7 V! R% z2 j& _639052 Database Objects Preventing Layer From Being Deleted report fails to run
! f6 {4 ^' o. C2 D, W5 z639685 Capture crash while deleting a Hierarchical Port from the Design ' p4 X& H% y0 |0 }9 G& D, Y2 c
639698 HOME variable defined with %USERNAME% doesn't use value of variable. % K8 s0 {1 h9 N
639829 After setting Zoom key(F10) to a new alias Tool Tip is missing the key number 6 C( E. Q' f: p- y" [4 t4 [
640127 Correct IDF documentation regarding UNOWNED objects S# C; `& J: [. P
640293 performance issues with scm and large pin count devices * ]5 K& j( s& [0 z7 ~* s
640314 The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users.
& }7 N$ w' ?3 e d! h! i$ z. C641503 Stop running the VAN check on a PLUMBING body symbol in PDV & O5 ] n# U) p% e) Z& \4 {
641676 Incorrect link to assign refdes help
; \: B8 i- _! V: M0 L642053 Drag Connected Objects icon is always display as on
: i* W$ @! q2 y! n0 r* w# p% P1 G642299 Switch the windows mode by set command
; w: s- ]' N1 p! h" Z& T( X642436 Save As symbol in part editor is not working fine $ ?4 _( s( V/ K
642713 Materials are not refreshed when material name have only numbers. 1 c) p/ l: J# Z; u/ d, q
642873 Dynamic shapes out of date message refers to Setup Drawing Options
6 |* u. P8 u, L7 W, i643721 Attributes with Null values in symbol.css files are removed when saved in PDV + Y r% f9 n8 _1 P
643949 Can not create Region-Class-Class for same net class.
5 a/ o6 o" M5 g3 y644016 APD crashes when creating a tile from LEF file
( K5 R' N7 E6 X- d644733 Import reference text file gives incorrect results
1 ?7 b2 N# y1 w9 o+ A( z8 U644879 Change forms to enforce naming of lib.defs file ; i% t! k5 E# I9 B6 K
645046 SG1525A PWM model is reporting unmodel pins and producing incorrect results
2 f3 h6 L$ F$ R; x645427 The save button is not enabled on changing the line width 7 Q+ m0 Q+ j; x1 t# b/ `
645996 con2con fails to parse ppt file correctly ! s- B! l# [6 P+ j5 L
646175 Please modify the limit length of "Allegro PCB Editor Limits" correctly.
8 m" H' E5 b6 c( C6 ]; c647555 Drill Customization text Non-standard Drill is not readable.
7 }! R! |, v' D) h647628 Annotate Type should be removed from PPT Option set files and documentation * G1 {: a# Z: J1 E' L# I
648443 Launching SCM without a license is not reported in debug.log
* f5 Z# v- T, q; L649166 Capture CIS crashes doing Place Database Part with non-admin User rights
' U3 @; _5 o+ N, n% _3 ?649222 Silent install adds extra License Server to CDS_LIC_FILE on the client
* _& M; A- @# r3 s, J( ?6 p' ]649570 PSpice COM Wrapper error while opening Capture PSpice project. 4 ~8 }* `8 A. R
650558 Die Pad layer changed after refresh padstack 4 U# T* ^8 ]1 |% U1 L9 k( ~* Z7 N! [
650997 Incorrect Pin Shape in CIS Explorer Footprint window
" M# g4 b2 ?7 C$ `$ n651000 "Wire length over parent die" violation is incorrect. 2 R8 _0 P4 _6 i: b
651153 Results for imported CSV inconsistent in PDV
. }. x- |6 I& D8 X651521 Resizing the display color visibility dialog box corrupts the display
j* M% \. ^+ A/ J' q- ?651526 Parts are missing in a advance analysis library list document and font size issue - ?- K- s9 l9 ~8 i; M3 I5 U0 ?6 G
651532 Scroll bars disappear after minimizing the color visibility form
9 @* K9 c$ Z0 p; p652050 Append waveform does not work in 16.2 for .dat files created in previous release with & C9 e7 m# }* {' u& X
import text format
! k! k& z. g3 n- I9 V& q652904 significantly low performance issues when using edit interface to delete ports of block % R% H3 N1 K0 P7 Y1 M
653067 Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#? 7 u, l! B6 {1 R" L* a6 Q
653784 Off-page connector name change to internal starting like "I12345555" & [6 P( Q. c- B! y
654580 Save As should update lib.defs without executing the edit die operation
* |+ P$ N: @ @5 n656282 BGA Generator adds outline and RefDes to wrong subclass ( |. k O+ R Q3 f' M( |
656723 visibility of clines in 3d viewer needs ALL instead of just CON field in layers ' ]; y! {1 ?$ }, W
657836 Text crop on User Preferences Editor form ) S( t) E: v' t4 ]# h
658347 Rule Continuous Soldermask Coverage Check should not work on Cline Segments 0 m4 R& F/ R! J
659437 Move group fails to display anything with Open GL enabled. ! ?% k" _8 Z* u9 |
660937 Import techfile fails with etch on layer yet layer has no etch 4 V0 U1 l' j( [4 N9 X
661369 Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON' 9 R. F+ z6 T8 n$ _4 x0 W7 l* i: F
661754 Hyperlink publish pdf to correct page but wrong grid location
( y8 C+ v& M8 ?' h P662622 Export Physical reports error Output Layout Filename contains space . A' }$ I" }" @5 I7 L" s
662918 Skill code example for axlReportRegister does not work 4 ` a+ U! [* K" C# D+ y
662971 Moving Bondwires disconnect bondfingers.
3 J8 i( c3 u( Y* w, Q2 _3 g663088 Cannot add connect to a C-line in Etch Edit Mode
9 o- E$ i% Z! _; y, j3 L663220 IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in * o* W- ?/ d/ C8 U' ?! |
DEHDL
5 j5 f+ H: s6 D$ e% E. _663726 ?Each? menu under RefDes is missing in BOM HDL user guide + n; |% T4 y0 C) B! \
664764 Material changes when layer type is changed 664900 Project manager User Preferences Editor form has text crop.
, K: ~7 Z) C( q6 l; `. z665236 Unable to import a Quartus-II version 9.0 pin file. : h5 M, \# J0 a* H, Q0 E% v
665389 Spread between voids not working for customer design
8 t# \5 c: J1 t" p S$ }8 U665413 In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing. ! N5 M$ o& U- b- ]! j! a
665451 Import - Part logic - information popup window has incorrect user preferences Editor
: k& t \' k; z% E0 h# z! c6 GCategory ' M& X" m& F, N1 q1 r: R/ `8 G
665661 Wirebond Die Escape Generator failed to generate Clines
- n4 J" }$ P0 R* S, U) j* t666099 Mandating at least one symbol with sizable pins for using size..1(not for size-1..0) ) _1 J- o0 {; x
SPLBPD-310/SPLBPD-309 on reload 0 A$ r0 n) F8 @: N9 I }
666667 Relational Table View Browsing Issue ' K# H) p' B8 n. [* r. z* |: O
667286 import IFF No Component Shape Line Via found in IFF file. 3 J. d: [* Q6 D M* S4 w
667751 db(v(out)) and vdb(out) gives different results for FFT 1 U" }8 {; c$ Q
668080 Improve handling of curved routes ; h. k$ M+ `8 `
668081 Capture Crash during Edit options
1 o- E z. {% L7 k1 C668393 Dielectric constant or loss tangent values do not update when changing conductor
1 h0 |8 e0 n) b9 M) i& c9 L- b* k668785 Capture not displaying variant values for Uppercase Display props 8 d: J" |3 r6 h3 t* E9 U8 ^
668799 Placing specific part crashes OrCAD Capture
/ i: \% I2 s0 Y668876 Text on the Add button is crop on the Edit via list form.
4 H/ E P0 D: p/ Z668892 Incorrect Parallel Length data in parallelism report ( h7 ?) W, Z7 ]+ c, ~2 ^' S
669206 Parallelism rule causing significant performance issues during DRC update
?3 l& ~5 U/ J+ m5 {2 t, S, z/ z669238 Unable to use permanent highlighting for groups in version 16.x
3 \- o. |9 l+ ^7 n669323 Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated - C' {/ j/ |; F, J) W( |4 U
669336 Error in documentation of DE HDL Reference Guide ; a# P% d! u1 a5 g& Y
670874 getVersion() function not reporting tool version
0 ?- u- }. e- H671811 Allegro extracta fails with more than 10 output files 9 X$ V4 w( S+ K1 z0 h* [& m/ p
672420 User defined property added to component instance is a function property in Allegro " W' \ x/ V& K4 u- B% x! f, q( {% P
672614 translator converts the symbol "\" in the original Spice model to "[url=]\\\\[/url]"
" o* u2 I8 S4 R672615 Translator generates 6 external nodes should only have up to 5 nodes
: t" V+ L! E2 W7 J& F672618 Translator generates statement in the dml file: Language=hspice causing Spectre run % M6 S5 v o" ]. T# I
errors 6 F! l$ k# `3 x/ e) d
672715 Steam_out takes a long time and then fails but the .log file reports a successful export
. \7 S* N+ n V$ a673279 Same characters are listed as both valid and invalid in naming rules. ' k& U' d: u" O& H
673410 search by net name is finding electrical
3 r7 P3 {5 k- {# ?" h5 e4 ~674058 Incorrect Variant Report
|/ m: ], @' x6 l( Z674291 Library Explorer fails to start and I receive a 'Runtime Error!' pop-up
8 o8 s8 D3 \4 `0 L7 ?4 a" f6 p9 M674555 If the DSN filename contains spaces, autobackup will not write any DBK files to ; s) ^" S3 T$ f" n7 T% U, Z K
675192 Adding a second BGA caused dsa_api.c to crash 6 g$ _2 o& z9 t+ }' g
675231 SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess.
+ h8 g% V- m6 M1 x* V675562 axlWindowFit() documentation needs to be changed.
: j9 R; i2 r4 Z7 C7 z# `675783 SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to * Z+ f2 _: q, ]- T9 k- L! u
become unplaced from alignment option 3 q K1 J( \! Y" P/ g% Y
676201 Cross section impedance not calculating with single license
) g& d# p6 t/ r676601 behavior of launch product from library manager
; N! k3 y/ G# Q3 q3 D! ^677582 mirror of die component on sip designs
' b' g. c9 F ~4 j9 B8 l3 P678013 Error: Symbol not found, though symbol is mapped in psmpath
" H& h% y9 |" k7 ?8 W' S+ u8 P678427 repeatedly placed symbols has strange instance name
, m3 p- Y, ~$ n$ ~1 N4 V678538 Why derive database does not transfer the Schematic Part property to CIS 8 v. L1 A: p' s/ X& x
678814 Spin a temp group will not rotate the symbol
% W4 j, |! a2 f" @* l! c* O678851 Difference in lengths in 16.01 and 16.2
F1 t. F4 ^0 V- ]678884 dbdoctor fixes corruption and then it's reintroduced
% a$ O- T" P, a679224 dbdoctor states it fixes an error but the error returns ) {# }! |& X& |
679960 Capture crashes from diff pair setup menu ; k( Z: Z2 J5 M/ y( }
680565 Capture dsn files are not properly associated during install $ b8 |$ x' \& C* c- o
681197 Report generator Hangs Up Allegro PCB Editor " c; H( {2 n5 J' Q$ E
682135 Justification of $PN placeholders not working in 16.2 release
, R) p: }5 ?3 _4 p7 F O682204 Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows * P: u5 Y9 o% D* ^- \' w6 v
682331 Incorrect reference to the middle mouse button.
H" _8 d. \( \683146 export variant path appears wrong in output folder while two DSN are open + }2 S9 q# K5 g! d# j3 L2 y2 \
simultaneously 683182 DRC0037 shows incorrect Alternate Net Alias.
0 A) S# y& t6 \0 }1 U8 y683379 ERROR in Measurement ConversionGain_XRange
- ~9 i b+ M) U684180 Sizable pins and vector pins cannot reside together in a component. 5 W% I# I. f4 o0 h7 ~5 P* F
684661 via array created wrong results
) T8 Q7 _* _3 ]( v684700 via array can not be placed on both sides of the cline 3 M3 d$ P% N6 v: g5 e* ~# u; q
684912 16.2 documentation is incorrect for axlDeleteFillet * u- \2 Z! E/ w" S' Y
684915 Incorrect mention of creating graphics template in the PDV user guide % w! b# ]( I) f/ N# [
685685 When the customer tried to merge shapes, they disappeared and do not merge.
8 N6 f6 y' Q8 |& C! J2 ^8 {$ ]686338 ERROR #8012 Database Operation Failed with MS SQL database
* F' H, {9 X; g5 u7 E, _686560 Changing pin group property after pin swap resets pin numbers
$ v a c9 `+ n686736 Load property does not propagate to the associated MECH part
6 t$ g! F- d* c9 B687008 ERROR 8020 after removing Place Icon ( n8 v% u- H8 F2 b
687074 Part disappears when you open it ' [8 I# Z: ?) d3 x% i
687354 Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package & H1 R# t- m% n$ e
687385 Publish PDF outputs the net name (with underscore) overlaps with wire.
4 n! Z0 y' x" q; S687708 Smoke deration calculations for Capacitor 6 Z5 ~2 k" R, Y% v
687715 Getting Warning TJL will not be smoke checked ' @0 k& {/ T2 s- y. K, n
688606 Inconsistency in synchronization between bias display and icon + s- p7 ^! n, r( e; @
689542 Comma in ESpice model name causes simulation failure
/ E: y2 ` g% s690112 Ignored nets are displayed in simulated crosstalk worksheet in CM . ~ s+ `1 i9 m7 D3 ?+ M s
691668 Stimulus editor hangs on doing change type
; M/ @; Y W3 W2 {691740 crash when setting coincident uvias in CM beta testing 16.3
2 t- i* N* v4 E$ o" b4 p694139 Case difference of net and bus while generating FPGA netlist / z$ M7 h$ T4 I$ T2 _ `' S# Q
694716 Waveforms are flat when using IO b-element in HSpice
- s: `5 I6 X, }- { Q# W: X( c3 |695109 Incorrect Diff-pair topology extracted by Paksi-E field solver
+ k. u1 M" N% q695431 csv2ptf fails without providing any error message
@8 u. a7 ]/ Z P696273 Shape disappears when updated in CDNSIP 16.01 and not following the constraints / R0 m% N+ p4 x6 m6 y
696534 Pin Visibility check box doesn't work while creating part from spreadsheet editor : d {; M0 d& \# l6 A
698494 Shape not getting filled correctly
5 [( A& d7 S3 Z# y; G) b$ I700160 Error: TVCurve must start at time zero . % M& f) z6 y9 T( ]9 h
700644 Allegro Crashes on doing Zoom In
8 A" d% Q+ e7 Q; H. c# a6 O700725 Create Fanout with Via structure add structure from Top to Int. for bottom pins
7 C: B. F6 U) q/ g0 K0 s8 @! C701128 Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
/ O: G( @6 R9 O4 z. [* ^702557 Incorrect Behavior with FSP 2 FPGA Option License
1 g! E5 F' V! i703324 Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in
; e! D4 l% _. k$ I/ J/ D704268 remove ARC and TOGGLE rmb options when in add rectangle or add circle command ; I0 c& f0 i- B5 d8 q7 F
704317 Capture crash when deleting schematic folder
6 X+ p2 t* ?: Y( w5 O1 K/ P" p704475 Allegro SI change editor to Allegro PCB XL causes menu problems
* u0 V+ r5 Z% }+ K. ?705902 ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
2 ~; n- q, u: _0 h6 p5 t+ h/ p- R705903 Cannot remove a matrix view after modifying the connections & v" F R6 N3 R* d9 V3 w
706169 IDF in error has spelling mistake
0 H0 A& g# R' R4 p( N1 T706613 Diff pair is not extracting properly through design link.
" z* b+ Z4 u [) H706729 Import properties fails with ERROR [IMP0020]
2 V; A7 W/ L- a0 g708134 Place > Manually command menus not refreshing the Placement list
" z s3 M/ o' m: s( @+ P0 V708145 Creating a netlist with Rev. 57AQ is not formatting correctly 5 m5 o+ Q/ B, X$ `9 g
708634 Shapes getting incorrectly displayed in 16.2
7 Z- B) s. z5 Z7 V) i$ |710279 ERROR 8020# Place component operation failed.
) G9 Y: ]* ^ }- S/ g) W710859 Unable to create Diff Pair from Autosetup
! G* u9 K, F- R1 t- i# V" ^) l711739 selecting one component/symbol of class IC can move unrelated component due to
$ J( }0 Q1 ]% C! i+ |& Vincorrect group membership.
3 J: L& T$ @5 I9 o0 ?712299 Internal application error while creating new design
# ?/ V8 X- X! U712898 Netrev should not read PARENT_PPT_PART property value while importing the logic,
C. p7 J) {! F0 T" i2 Z* ^due to which import logic fails / }( k9 a Y1 e
713465 Problems with dynamic shape creation over routed full-arcs diffpairs
; R. }% T" z2 f6 V/ X5 {+ {713480 Display issue when adding a custom property to the first bit of the bus.
1 t- N4 G7 V4 h; h714072 Error while linking database part 7 Z# T" g, F& T3 g5 u
714156 Capture crash while archiving project for external referenced design
& ^2 G9 M- h& z g ?9 H* D# D ~716097 Specctra is crash during route. ; K2 v" H8 e& z, L: |* m
716212 PACK_SHORT property gives package error for visible POWER pins 717484 Dynamic shape creating voids when moving a symbol 9 v, c J% X4 }. V
718151 Geometry not selected when we click tab for selection filter in pad designer : u. z& K& l4 r: m
720092 Difference of behavior for slide for segments in options tab & RMB options 8 K* Y- R3 L& F `% [
720191 Delay tune cannot keep the Gap if the diffpair segment is diagonal.
* Q7 X5 t* i" M# \- A @720482 Include steps to Enable PSpice Menus in Design Entry HDL 8 ?) T) q8 F- g! a
721415 Two buses are connected without a warning when moved on top of each other & `) ~7 K; w2 j! R1 t* x8 p
721938 Cross-Section open error
% T: J) z! B8 Z4 `; Q/ r8 n9 k4 C722997 Hyperlink function does not work if zone info. includes hyphen ' K$ {" {/ z4 ]+ U6 D
723146 Pb during compilation using predicate getFileStrings
, x4 L$ o4 I7 E5 f/ k; ~8 l723159 Typographical Error under "Synchronizing PTF Information" section 1 M) p# M. b# x0 n
723235 client install results in incorrect, redundant, and problematic cds_lic_file variable ! f0 D4 ^6 c* p9 D
724414 State Wins Over Design does not reset the subdesign_suffix block values
}; q9 m1 Z) ?+ M5 X% F( N8 C724969 Allegro crashes when using place replicate function
0 ], h5 z H% [0 L0 q1 O4 A, E725852 Impedance has little difference - BEM2D # n( s1 Q5 Y8 {2 L; E$ E9 S! y5 Y
726731 SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in
: D! V! a' p* e V+ ybf not following snap
- ?! c4 M, D3 i- g726763 crash during logic import in Allegro CM enabled flow ! V7 ~; `4 x; }1 ]. [
727663 Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly ; F6 M8 ?" Z2 d- j$ ?7 ?* ~: O
729496 Build error in 16.3 and 16.4 cdnsip.exe |
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发表于 2009-12-12 17:07
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发表于 2009-12-12 23:20
