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Electrical(电气规则) 9 m& N9 b: u, k0 p7 Q& ~
Clearance(安全间距规则) ! R0 f1 K; {& ^: E# @7 A( i1 R
short-circuit(短路规则)
- V Z/ l* S J T8 s Unrouted Net(未布线网络规则)
% B* g6 R; L/ W& d( {- {" J. v- R Unconnected Pin(未连线引脚规则)
3 j9 c! h% e$ b5 J: tRouting(走线规则)
1 ^7 x5 O# [5 d% E4 v# P Width(走线宽度规则)
* h- R2 ~0 T$ y) b7 ] Routing Topology(走线拓扑布局规则)
4 T, K1 `: s1 ?' Z" |* X Routing Priority(布线优先级规则)
* r2 C5 S" u- [ Routing Layers(板层布线规则) 2 t5 s4 m+ d& F$ d3 H9 u: N. A
Routing Corners(导线转角规则)
, m/ B% ?" X( j& N* p( v' ` Routing Via Style(布线过孔形式规则)
9 \, u* ~/ ` s2 z) }/ ~5 \$ H Fanout Control(布线扇出控制规则) 8 ~ ]! m* p% d7 s/ h
SMT(表贴焊盘规则) P: F. f& }8 b# q* ?! D
SMD To Corner(SMD焊盘与导线拐角处最小间距规则)
2 R; U# J2 p1 F$ v6 s1 E) J SMD To Plane(SMD焊盘与电源层过孔最小间距规则)
" h* [- ], s i p+ K SMD Neck-Down(SMD焊盘颈缩率规则)
0 L; L$ o* K3 E" }1 d9 `2 V7 k2 g4 YMask(阻焊层规则) 3 y; j; u% A( q) y' c
Solder Mask Expansion(阻焊层收缩量规则)
8 @. ]. \& p* W5 e: P& y$ d Paste Mask Expansion(助焊层收缩量规则)
y" E. V, Y' C2 h7 x a- {( m6 |% LPlane(电源层规则)
' \7 G) P9 L" ~ Power Plane Connect(电源层连接类型规则) - n q" | Z% \* ~# K' l) }: M, a5 p" S
Power Plane Clearance(电源层安全间距规则) . u5 W. a) N) D F0 ^# F+ E' J
Polygon Connect Style(焊盘与覆铜连接类型规则)
6 d, p5 i+ [4 L- t2 H ?# hTestpoint(测试点规则)
$ [; }" l+ L! ~3 M2 G Testpoint Style(测试点样式规则)
& _4 i+ H' E, l7 H Testpoint Usage(测试点使用规则)
) N; Q9 R4 T+ D. \: m1 V9 _Manufacturing(电路板制作规则) 6 H# J& Y' g5 n6 _5 F4 d2 h2 v# ]
Minimum Annular Ring(最小包环限制规则)
! r) Q! D; e% A* D# m9 v Acute Angle Constraint(锐角限制规则)
& ]6 M' [0 a; s. Q! `' h ~$ V Hole Size(孔径大小设计规则) 4 i/ p: J! x- e; [. i- y! E
Layer Pairs(板层对设计规则) - N. ^* g1 e6 H' k: n3 E# P
Highspeed(高频电路规则)
. d8 U& H; f7 A1 v( x Parallel Segment(平行铜膜线段间距限制规则) 5 o+ N `# @' l
Length(网络长度限制规则)
4 y8 [% Y" f5 A; G! ?- W3 U Matched Net Lengths(网络长度匹配规则) : H2 e1 |* a6 D( Q: {' r1 n y
Daisy Chain Stub Length (菊花状布线分支长度限制规则) / o* ^9 L, z- |$ i, j
Vias Under SMD(SMD焊盘下过孔限制规则) : X# t! A3 |% \; U( Y
Maximum Via Count(最大过孔数目限制规则)
7 D* c+ I; E0 h3 cPlacement(元件布置规则)
; n3 r% s8 K# z Room Definition(元件集合定义规则) 2 y1 |. M1 @' ]4 @, N* \( V5 x
Component Clearance(元件间距限制规则)
% `+ A5 D- ?6 o9 n7 c% A: ~ Component Orientations(元件布置方向规则)
3 |- q# B% M; ^! n3 u Permitted Layers(允许元件布置板层规则)0 N, i4 O. |, B& g3 [; s
Nets To Ignore(网络忽略规则) ! @: B i& Z3 @3 I
Hight(高度规则)
9 g o2 \" c7 q- P. tSignal Integrity(信号完整性规则) ) N7 O, J( C n1 l7 g
Signal Stimulus(激励信号规则)
8 d* f$ P/ h5 ~ Overshoot-Failing Edge(负超调量限制规则)
7 O5 |# g" Q% p/ B Overshoot-Rising Edge(正超调量限制规则) 7 L |. X- ^6 |# p
Undershoot-Falling Edge(负下冲超调量限制规则)
. p2 L; i4 M& i- p6 `3 D/ p Undershoot-Rising Edge(正下冲超调量限制规则)
$ X. V f& q$ Z0 j Impedance(阻抗限制规则)
9 Z! o$ j4 C8 b2 x' ~$ D Signal Top Value(高电平信号规则) * J- I& X' }, e/ r9 c8 F( g
Signal Base Value(低电平信号规则)
+ _ ?& N" Z* h! b; ` j, J Flight Time-Rising Edge(上升飞行时间规则) . b* {5 r4 d8 N7 V
Flight Time-Falling Edge(下降飞行时间规则)
/ G' E3 H* K8 H9 G z8 u Slope-Rising Edge(上升沿时间规则) 1 i) q) N* d% @& F7 o
Slope-Falling Edge(下降沿时间规则)
' {, ]$ A& R2 t Supply Nets(电源网络规则)
' s/ B* Z0 t& _0 D& H! g; t# g; I
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