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Electrical(电气规则) / F6 w$ J8 H, V4 v! D
Clearance(安全间距规则) # i# L3 f. I J7 A9 ^
short-circuit(短路规则) 2 U& ?6 E% Y2 Z6 W" ^
Unrouted Net(未布线网络规则)
. x. R7 ~& U+ A8 B* ~! ?1 W Unconnected Pin(未连线引脚规则)
- y* D$ X' B, s1 |$ @+ {6 URouting(走线规则)
7 @: [7 K: e& l Width(走线宽度规则)
2 |, F7 Z5 b( y; e% z* o% O Routing Topology(走线拓扑布局规则) 2 a3 y* `) ?4 N% \% R9 [& @$ S
Routing Priority(布线优先级规则) ' u( L& b& s8 ]2 I0 {$ }
Routing Layers(板层布线规则)
5 ]" A2 D; d U% D9 v) f, i, ^ Routing Corners(导线转角规则)
/ B: J. T3 ?$ W, _' C Routing Via Style(布线过孔形式规则) - q8 ^5 F, B0 |; h, T8 r8 ~
Fanout Control(布线扇出控制规则) 9 `. L7 i% O1 D4 f# Z( i2 y+ k
SMT(表贴焊盘规则) ; w& c% y/ D* H
SMD To Corner(SMD焊盘与导线拐角处最小间距规则)
7 y" w" [+ a% f8 \8 V SMD To Plane(SMD焊盘与电源层过孔最小间距规则) + ^5 g, l2 B) c. [5 \- Y5 N @
SMD Neck-Down(SMD焊盘颈缩率规则) : t7 W, T! W3 m
Mask(阻焊层规则)
R0 D. ?( G' B9 i' B# W) N Solder Mask Expansion(阻焊层收缩量规则) , z4 v6 y; J( a8 V8 N" `
Paste Mask Expansion(助焊层收缩量规则)
2 A3 ^; F/ d' ], ]% g; S8 ZPlane(电源层规则)
7 N+ A% k0 h- j& V2 L, J Power Plane Connect(电源层连接类型规则)
! r& }) b4 G' c/ g: _ Power Plane Clearance(电源层安全间距规则) j9 k! c9 j: T) z2 m9 u; k# f' b
Polygon Connect Style(焊盘与覆铜连接类型规则) $ n1 D% M- h5 n0 t: V3 b
Testpoint(测试点规则)
( {- ?; J' O2 r+ m# D5 O Testpoint Style(测试点样式规则) , k$ Z7 r N. ]
Testpoint Usage(测试点使用规则) 8 N G# K' {5 p$ t7 |) C" I7 T+ {
Manufacturing(电路板制作规则) 0 z# r1 G' \ g7 R' V( U5 G' U
Minimum Annular Ring(最小包环限制规则) ) f3 n6 i1 _4 j, {4 M+ Y; k
Acute Angle Constraint(锐角限制规则)
$ @0 N: @% y0 m: c8 T Hole Size(孔径大小设计规则) / S. F4 H$ d4 \" Z. H# P
Layer Pairs(板层对设计规则)
9 C7 r2 C3 a2 u% t/ X. ?& hHighspeed(高频电路规则)
+ i' B" s- y9 Y' ? Parallel Segment(平行铜膜线段间距限制规则)
# z) c2 U6 I: @) w( C, ^ Length(网络长度限制规则)
# x3 t1 o; q: A5 O3 c; r Matched Net Lengths(网络长度匹配规则) . k; \5 R: _& x% w# M% {) j0 `3 E
Daisy Chain Stub Length (菊花状布线分支长度限制规则) ! K7 g6 j& G$ {' |' \& N& h6 x- D
Vias Under SMD(SMD焊盘下过孔限制规则) ; i5 J. I; j' v
Maximum Via Count(最大过孔数目限制规则)
5 o/ b8 R0 y# b# R# EPlacement(元件布置规则)
9 ~9 `7 Z) t, x+ N* o+ P& O) W Room Definition(元件集合定义规则)
0 q. m+ R) d& z3 C Component Clearance(元件间距限制规则)
+ g7 z) {8 ]/ ~! r) G7 i9 u9 j Component Orientations(元件布置方向规则)
/ y! R0 x( E. L- w Permitted Layers(允许元件布置板层规则)5 v0 [! o T! x$ y/ |( {
Nets To Ignore(网络忽略规则)
) a* ^# K# C/ l- M0 F0 R5 m- I Hight(高度规则) $ h( Q' a+ C0 h4 G; \3 N5 D
Signal Integrity(信号完整性规则)
3 v9 B$ O2 d8 G+ `' d/ Y6 N Signal Stimulus(激励信号规则) ' F: w9 _* w& z9 O* `
Overshoot-Failing Edge(负超调量限制规则)
% {3 ]* G* F. Y! _* \, \ Overshoot-Rising Edge(正超调量限制规则) $ Y" x3 \: n3 j9 l) M
Undershoot-Falling Edge(负下冲超调量限制规则)
' Z, }6 B0 `! H9 g4 D5 V; s Undershoot-Rising Edge(正下冲超调量限制规则)
; D; N$ {' W% c6 J6 h$ c! x Impedance(阻抗限制规则)
7 d; _) P: ?$ ]$ x8 K Signal Top Value(高电平信号规则) $ x- R" x* S9 T+ j
Signal Base Value(低电平信号规则) : B9 ?) g8 O) o: P( h
Flight Time-Rising Edge(上升飞行时间规则)
8 N3 ]) Y2 X* A% M$ h* U( O" e Flight Time-Falling Edge(下降飞行时间规则) ' @5 [& a# y4 o6 B
Slope-Rising Edge(上升沿时间规则)
' A' ?2 h; [6 h* U5 G- l Slope-Falling Edge(下降沿时间规则) 3 m5 d8 |" U2 ?7 _" o
Supply Nets(电源网络规则) * Z3 ^( y+ p" e1 Y4 @, e
( j% _) `* L M4 a2 Q( Y' _; {
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