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--------------------------------------------------1 s3 [* t2 N% ~( \# _3 Q: F
Checking Schematic: FPGA* M4 w1 J( D4 y9 }) M
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$ C$ d9 m2 ?7 o) Q: ]7 RChecking Electrical Rules . @! | O& W. _: L0 G! y& x e1 J& b
$ G( e0 c# H; d7 SWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V21 Bidirectional Connected to Output Port: FPGA, PAGE-A1 DR FPGA END (4.90, 2.20)
& Z! m- s6 r! O* B4 RWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AA19 Bidirectional Connected to Output Port: FPGA, PAGE-A1DR FPGA END (5.00, 4.80)
5 T6 y9 }$ Z. q# DWARNING [DRC0004] Possible pin type conflictWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_W15 Bidirectional Connected to Output Port: FPGA, PAGE-A1DR FPGA END (2.50, 5.30) U1,IO_VB7N0_Y14 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.50) + X, B7 l7 r, W$ b+ v
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V20 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.10)
; \7 I+ w# }/ |* F$ t! ?! ~" aWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.30) 2 [+ ~1 d( N* Y" I2 `3 |
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_W22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.70) ) n4 T$ ^0 \( n% m: O( V+ c' S
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_W16 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.40) 9 q! u8 O" Z. y
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AB18 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 5.60) 9 N+ V- ?; m8 ?! Z/ n& Z _
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_Y17 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.60) + D: K) ]1 A0 J' i8 H
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_Y21 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 3.10)
2 c/ S5 I/ d% q7 n1 y K) Q6 {: cWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_Y22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 3.20)
1 b; q' r2 \* ? NWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AA18 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 4.70)
7 K' X1 G/ [! `- h' ~WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_W21 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.60) ! b q L. U$ X$ N% s+ G
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AB19 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 5.70)
# s2 ^; y# X* k2 Y/ mWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_R17 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 1.70)
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发表于 2011-12-9 13:52
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发表于 2011-12-9 14:43