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Translating E:\WORK\TEST\1.asc.
& I9 v; n" j; c. ~9 ^' w' L0 CReading PADS ASCII file header.
5 G- N& }8 C2 r- T Version = PowerPCB5.0
( ~. X7 M5 I4 ~) J4 k Route Layers = 4
1 P' u6 ?/ L6 f* s8 k& L; ?0 X Units = METRIC
7 c& M& {6 {' V! G; a Hatch mode = Vertical / Horizontal
/ c- ~, t" C2 l3 P7 Y9 c S Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315% {: ]9 |! Z$ C
Initializing new database.7 c4 @2 U$ i2 P0 t9 {0 X
Creating layers.0 q( u& ? j% f0 `) n4 K- U
Reading PADS ASCII file body.
" V' Q2 \; _3 n5 `1 d *PARTTYPE*
$ X0 F6 r, w- q! b *MISC*
! z3 ~- o/ c. [0 U, @% l *MISC*% R- D) `6 J0 M) _* Z. g
*MISC*' r* M; k7 x+ G0 k% S' S% I
*MISC*
3 O& _4 u, d8 V4 f# ^1 p7 f/ M *MISC*4 H1 ~4 N2 z1 c
*REUSE*/ H- Y' S% _1 c3 ~% {
*TEXT*; q( x+ I5 L3 d9 Q* Y6 T2 [
*LINES*
% o" g5 {' l* o# k3 Z *VIA*
2 ]8 F ?, {; }( {( k *PARTDECAL*( ]+ o. ^( y, F B8 U
*PARTTYPE*5 O4 B* y8 ]" ~5 _9 ` {
*PART*- Y' P) i$ y) A* ?: _
*ROUTE*( n) u) @; V6 B9 F
Writing routes.
: h: D$ r6 }9 R( j& H0 u *END*
2 B) X% h1 a: l+ O# h! F2 g1 ^
0 d6 Y, Y: N- O. O===============================================================================0 C+ z4 l. X1 ^) i% a4 r% B( ^
PADS layer usage summary:/ J* b' r3 w9 H% T- ], W3 i0 O2 j
Layers 1 to 4 are route layers.
0 v8 l1 _2 z& l" n: D: y. U LINES:& y# G! g, ?: m& }4 |
0 BOARD GEOMETRY - ALL- g9 ]5 z0 Y* T# f& `7 y
1 ETCH - TOP
, f( i/ h" T( {- k+ l& ` 3 ETCH - INTERNAL2
3 A0 y, o2 V; b; Z+ X. @, c$ O 4 ETCH - BOTTOM/ k2 [5 `. a0 e; {! _; a9 C
9 * Not mapped!
, Y8 @& E& ?' ^/ S. ` 10 * Not mapped!4 x8 h, F+ H0 W" v0 }
COPPER:
5 M( x. u$ `0 j6 ? TEXT:
/ `1 w, U+ |! V/ X) [6 G: ^ 1 ETCH - TOP# d4 g6 p; `2 L: v0 V$ m
26 * Not mapped!1 D/ [# C* l1 \1 h
DECALS:( M J" d3 w1 l2 Y8 T M' k
0 PACKAGE GEOMETRY - SILKSCREEN_TOP; n* i. ]5 s, f8 B
1 PACKAGE GEOMETRY - SILKSCREEN_TOP
! L Z3 `7 F/ S 12 * Not mapped!
4 v0 C- B& ?6 W( C 19 * Not mapped!
W% k2 A4 l$ H% r+ A# g* ?2 B& b7 A 26 * Not mapped!, n0 n) \1 v% S% N" L/ ]
PADS:; h( x% t" u7 }$ y* t3 y' q" {
0 ETCH - internal_pad_def$ R) m# I6 l1 ?2 v* D
1 ETCH - TOP0 h1 `" ?7 @" W: x! R
2 ETCH - INTERNAL1% P2 [% Z& A1 ]4 j9 Z
3 ETCH - INTERNAL2* v% A3 s; K) i9 @! F
4 ETCH - BOTTOM. w/ R J. N. b" x7 }
6 * Not mapped!, r! k y, {2 @; [
15 * Not mapped!
- T3 B( u A* Z) h2 e3 b- C 16 * Not mapped!9 b2 o9 w h! F+ m% S- G
23 * Not mapped!
" j5 e/ R- r# Q- d+ g# | VIAS:
7 @8 \8 a4 c$ [4 M0 J! f 0 VIA CLASS - internal_pad_def
) |# F& C; X: |2 H; B; f 1 VIA CLASS - TOP
9 t3 W5 X7 C! D1 V* l7 h5 p 2 VIA CLASS - INTERNAL1% g4 M/ t. ?% c4 ~; q* w
3 VIA CLASS - INTERNAL26 N! ]/ J; x$ N( M
4 VIA CLASS - BOTTOM
+ ^+ t, [% p: T
: a/ G9 l# _+ {, T* Z6 T WARNING: 63 data objects mapped to the UNUSED class were ignored.
) O1 @- G2 ]0 V. \5 G! o===============================================================================
9 S) a& a) C9 ]. l/ V% d* v6 `. ?, @7 r; r+ Q3 ~' F0 K
Creating E:\WORK\TEST\1.brd.9 a- g7 J6 f; w! O
Loading netlist:) n6 _0 q9 C3 Q. X+ r
E:\WORK\TEST\1.TXT
3 q# U$ d! x6 o. Z5 }. o6 R% |; FWriting database.( t% L$ B6 z6 }0 E; c2 n
ERROR: Error while writing the Allegro database.; k! u1 A6 p7 J, u) R) {
Closing database.) O9 K( `5 B3 d7 R( w' B
Translation complete.
5 ^- h4 M5 A# c* jFinished with errors!& G; ?' I" G3 d8 m1 O( K( ]
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发表于 2011-10-12 00:37
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发表于 2011-10-13 13:23