MC8051 IP core

zgq800712 · 发表于 2008-11-20 08:08

EDA365欢迎您！

您需要登录才可以下载或查看，没有帐号？注册

x

在网上寻找数字地与模拟地的英文材料；
无意间浏览到一个国外的的CPLD/FPGA论坛，点击进入
发现了有人求51的IP CORE，在回帖里面看到这个，所以下载了。

@: mc8051@oregano.at
W: http://oregano.at/ip/8051.htm

************************************************************
This is version 1.4 of the MC8051 IP core.
November 2004: Oregano Systems - Design & Consulting GesmbH
============================================================
Changes:
- corrected behaviour of RETI instruction handling
- added synchronization for interrupt signals
- corrected timer problems

************************************************************
This is version 1.3 of the MC8051 IP core.
September 2002: Oregano Systems - Design & Consulting GesmbH
============================================================
Change history:
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.
- Corrected problem with duplex operation in file
  mc8051_siu_rtl.vhd

************************************************************
This is version 1.2. of the MC8051 IP core.
June 2002 - Oregano Systems - Design & Consulting GesmbH
============================================================
Change history:
- Eliminated the scr subdirectory form the distribution.
- Improved documentation.
- Corrected several bugs in the source code (see the
  website for more details).
- Improved the testbench with respect to the I/O port
  behavior.
- Enriched the msim directory with the assembler source
  code of an example program.
- Provided the source code of a Intel hex to binary
  textfile converter to ease simulation of the user's
  assambler programs.

************************************************************
This is version 1.1. of the MC8051 IP core.
Jan 31st 2002 - Oregano Systems - Design & Consulting GesmbH

下面是里面的部分VHDL

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library work;
use work.mc8051_p.all;

-----------------------------ENTITY DECLARATION--------------------------------
entity addsub_core is

  generic (DWIDTH : integer := 16); -- Data width of the ALU
  port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
      opb_i : in std_logic_vector(DWIDTH-1 downto 0);
      addsub_i : in std_logic;
      cy_i    : in std_logic;
      cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
      ov_o : out std_logic;
      rslt_o : out std_logic_vector(DWIDTH-1 downto 0));

end addsub_core;

entity mc8051_alu is
  generic (DWIDTH : integer := 8);          -- Data width of the ALU
  port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
      ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
      acc_i    : in std_logic_vector(DWIDTH-1 downto 0);
      cmd_i    : in std_logic_vector(5 downto 0);
      cy_i    : in std_logic_vector((DWIDTH-1)/4 downto 0);
      ov_i    : in std_logic;

      new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
      new_ov_o : out std_logic;
      result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
      result_b_o : out std_logic_vector(DWIDTH-1 downto 0));

end mc8051_alu;
--Inputs:
-- rom_data_i...... data input from ROM
-- ram_data_i...... data input from RAM
-- acc_i........... the contents of the accumulator register
-- cmd_i........... command from the control unit
-- cy_i............ CY-Flags of the SFR
-- ov_i............ OV-Flag of the SFR
--Outputs:
-- new_cy_o........ new CY-Flags for SFR
-- new_ov_o........ new OV-Flag for SFR
-- result_a_o...... result
-- result_b_o...... result

architecture struc of mc8051_alu is
  signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);
  signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);
  signal s_alu_op_a    : std_logic_vector(DWIDTH-1 downto 0);
  signal s_alu_op_b    : std_logic_vector(DWIDTH-1 downto 0);
  signal s_alu_cmd    : std_logic_vector(3 downto 0);
  signal s_dvdnd       : std_logic_vector(DWIDTH-1 downto 0);
  signal s_dvsor       : std_logic_vector(DWIDTH-1 downto 0);
  signal s_qutnt       : std_logic_vector(DWIDTH-1 downto 0);
  signal s_rmndr       : std_logic_vector(DWIDTH-1 downto 0);
  signal s_mltplcnd    : std_logic_vector(DWIDTH-1 downto 0);
  signal s_mltplctr    : std_logic_vector(DWIDTH-1 downto 0);
  signal s_product    : std_logic_vector((DWIDTH*2)-1 downto 0);
  signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);
  signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);
  signal s_dcml_cy    : std_logic;
  signal s_addsub_rslt  : std_logic_vector(DWIDTH-1 downto 0);
  signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);
  signal s_addsub_ov : std_logic;
  signal s_addsub_cy : std_logic;
  signal s_addsub    : std_logic;
  signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);
  signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);
begin                -- architecture structural
  i_alumux : alumux
generic map (
   DWIDTH => DWIDTH)
port map (
   -- Primary I/Os of the ALU unit.
   rom_data_i => rom_data_i,
   ram_data_i => ram_data_i,
   acc_i       => acc_i,
   cmd_i       => cmd_i,
   cy_i       => cy_i,
   ov_i       => ov_i,
   cy_o       => new_cy_o,
   ov_o       => new_ov_o,
   result_a_o => result_a_o,
   result_b_o => result_b_o,
   -- I/Os connecting the submodules.
   result_i    => s_alu_result,
   new_cy_i    => s_alu_new_cy,
   addsub_rslt_i => s_addsub_rslt,
   addsub_cy_i => s_addsub_newcy,
   addsub_ov_i => s_addsub_ov,
   op_a_o       => s_alu_op_a,
   op_b_o       => s_alu_op_b,
   alu_cmd_o    => s_alu_cmd,
   opa_o       => s_addsub_opa,
   opb_o       => s_addsub_opb,
   addsub_o    => s_addsub,
   addsub_cy_o => s_addsub_cy,
   dvdnd_o    => s_dvdnd,
   dvsor_o    => s_dvsor,
   qutnt_i    => s_qutnt,
   rmndr_i    => s_rmndr,
   mltplcnd_o => s_mltplcnd,
   mltplctr_o => s_mltplctr,
   product_i    => s_product,
   dcml_data_o => s_dcml_data,
   dcml_data_i => s_dcml_rslt,
   dcml_cy_i    => s_dcml_cy);
  i_alucore : alucore
generic map (
   DWIDTH => DWIDTH)
port map (
   op_a_i => s_alu_op_a,
   op_b_i => s_alu_op_b,
   alu_cmd_i => s_alu_cmd,
   cy_i    => cy_i,
   cy_o    => s_alu_new_cy,
   result_o  => s_alu_result);
  i_addsub_core : addsub_core
generic map (DWIDTH => DWIDTH)
port map (opa_i => s_addsub_opa,
            opb_i => s_addsub_opb,
            addsub_i => s_addsub,
            cy_i    => s_addsub_cy,
            cy_o    => s_addsub_newcy,
            ov_o    => s_addsub_ov,
            rslt_o => s_addsub_rslt);
  gen_multiplier1 : if C_IMPL_MUL = 1 generate
i_comb_mltplr : comb_mltplr
   generic map (
      DWIDTH    => DWIDTH)
   port map (
      mltplcnd_i => s_mltplcnd,
      mltplctr_i => s_mltplctr,
      product_o  => s_product);
  end generate gen_multiplier1;
  gen_multiplier0 : if C_IMPL_MUL /= 1 generate
s_product <= (others => '0');
  end generate gen_multiplier0;
  gen_divider1  : if C_IMPL_DIV = 1 generate
i_comb_divider : comb_divider
   generic map (
      DWIDTH  => DWIDTH)
   port map (
      dvdnd_i => s_dvdnd,
      dvsor_i => s_dvsor,
      qutnt_o => s_qutnt,
      rmndr_o => s_rmndr);
  end generate gen_divider1;
  gen_divider0  : if C_IMPL_DIV /= 1 generate
s_qutnt <= (others => '0');
s_rmndr <= (others => '0');
  end generate gen_divider0;
  gen_dcml_adj1  : if C_IMPL_DA = 1 generate
i_dcml_adjust : dcml_adjust
   generic map (
      DWIDTH => DWIDTH)
   port map (
      data_i => s_dcml_data,
      cy_i => cy_i,
      data_o => s_dcml_rslt,
      cy_o => s_dcml_cy);
  end generate gen_dcml_adj1;
  gen_dcml_adj0  : if C_IMPL_DA /= 1 generate
s_dcml_rslt <= (others => '0');
s_dcml_cy <= '0';
  end generate gen_dcml_adj0;
end struc;