SDRAM控制问题请教：为何用的器件模型读数据的时候是高阻Z

mengzhuhao · 发表于 2008-12-1 20:22

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SDRAM控制问题请教：为何用的器件模型读数据的时候是高阻Z

我这我用到的一个器件仿真模型
但是为何数据线在读的时候是高阻态？

在我的tb文件里面
wire    [15:0] io_Sdram_DQ;
我看器件模型里面有存储单位的设置
为何写如何的数据读出不对

parameter addr_bits =    12;
parameter data_bits =    16;
parameter col_bits  =    8;
parameter mem_sizes = 1048575;
inout    [data_bits - 1 : 0] Dq;
input    [addr_bits - 1 : 0] Addr;
input                [1 : 0] Ba;
input                      Clk;
input                      Cke;
input                      Cs_n;
input                      Ras_n;
input                      Cas_n;
input                      We_n;
input                [1 : 0] Dqm;
reg    [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg    [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg    [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg    [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
........

zengeronline · 发表于 2008-12-2 08:42

inout类型的tb文件要这样搞
wire[7:0] io_Sdram_DQ_wire;
reg[7:0] io_Sdram_DQ_reg;
assign io_Sdram_DQ_wire = (~We_n) ? io_Sdram_DQ_reg : 1'bz;
这样的话在We有效时Dq_wire上是要写入的数据, 在读信号有效时,Dq_wire由读出的数据驱动
这个是方法,我也是在网上找到后按这个方法仿真双向端口的HDL文件的

mengzhuhao · 发表于 2008-12-2 20:46

为何在写的过程列地址的第一位在最后给写成zzzz了？
见下面的记录
列地址最大255

.....
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215250.0 ns WRITE: Bank = 0 Row = 0, Col = 250, Data = 5959
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215270.0 ns WRITE: Bank = 0 Row = 0, Col = 251, Data = 6868
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215290.0 ns WRITE: Bank = 0 Row = 0, Col = 252, Data = 7777
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215310.0 ns WRITE: Bank = 0 Row = 0, Col = 253, Data = 8686
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215330.0 ns WRITE: Bank = 0 Row = 0, Col = 254, Data = 9595
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215350.0 ns WRITE: Bank = 0 Row = 0, Col = 255, Data = 3434
SDRAM_TEST_tb.mt48lc4m16a2 : at time  215370.0 ns WRITE: Bank = 0 Row = 0, Col = 0, Data = zzzz
SDRAM_TEST_tb.mt48lc4m16a2 : at time  220915.0 ns READ : Bank = 0 Row = 0, Col = 0, Data = zzzz
SDRAM_TEST_tb.mt48lc4m16a2 : at time  220935.0 ns READ : Bank = 0 Row = 0, Col = 1, Data = 8282
SDRAM_TEST_tb.mt48lc4m16a2 : at time  220955.0 ns READ : Bank = 0 Row = 0, Col = 2, Data = 9191
SDRAM_TEST_tb.mt48lc4m16a2 : at time  220975.0 ns READ : Bank = 0 Row = 0, Col = 3, Data = 3030
SDRAM_TEST_tb.mt48lc4m16a2 : at time  220995.0 ns READ : Bank = 0 Row = 0, Col = 4, Data = 4f4f
SDRAM_TEST_tb.mt48lc4m16a2 : at time  221015.0 ns READ : Bank = 0 Row = 0, Col = 5, Data = 5e5e
SDRAM_TEST_tb.mt48lc4m16a2 : at time  221035.0 ns READ : Bank = 0 Row = 0, Col = 6, Data = 6d6d

mengzhuhao · 发表于 2008-12-2 21:46

发现在仿真出来的波形在写与读的开始位置出有点不对劲见附图那位用过类似器件模型仿真的说说可能的缘故

feihu612 · 发表于 2011-4-29 09:24

能交流一下吗？告我你的联系方式吗

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