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Cadence SPB OrCAD 16.60.016 Hotfix | 853 mb
3 V5 [' w8 @9 P8 A! e2 q DATE: 09-27-2013 HOTFIX VERSION: 016- D" c% F N6 u( E
6 R9 p& _: J6 C===================================================================================================================================: {; T9 l, w W% d2 i
+ Z+ {4 |/ D) I" o7 D* J' f1 rCCRID PRODUCT PRODUCTLEVEL2 TITLE* _9 ]- f4 U# S* z
+ ^; j3 B% p0 E& _, Z0 R8 {=================================================================================================================================== c; @5 G$ x2 y
- X7 x9 B; m- ^- }548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
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1076579 CAPTURE GENERAL Display value only if value exists
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1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.* V9 z& O8 F7 L9 a6 b9 z8 L3 G9 k
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1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility2 p8 g' v$ {4 g; n8 C
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1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled5 g! \8 l4 p0 g* K9 V% j, d2 A- r! n
2 x7 c" W2 l; d1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.+ {" l4 ~$ [' Z i& [! Z
- a3 [6 k9 j' K6 _1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape$ {: H w* S- S& G+ `
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1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms+ Y3 g, z* U# I* l" N
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1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
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7 Q8 \5 a& w9 Q7 m1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor0 n: [* {! h. ^3 v' V5 ~* `7 H* E
- m& Y5 X1 R0 x+ e1 [! ]1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.; c/ U: m$ s8 O7 R7 l O" }% K
, q# p" n3 E- ` o1123364 FSP GUI Clicking on column header should sort the column.) F- k' ?$ E! g
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1123403 FSP EXTERNAL_PORTS Improper checkbox selection for 緿o Not Connect?or 縀xternal Port?column
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1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.
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" @! h$ i7 Q' h* N4 `+ m' D2 \1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.0 c* t. |8 n) U2 |# k7 ]6 q( y
$ T) o- @1 m8 C( d! [0 [1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
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8 R4 O" Q* [3 j& `. U5 x! L1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set( s; r! F- S$ g" C! f$ [$ @
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1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
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# y) j4 u- x1 O6 L% V1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.
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( H0 j t4 w# c0 Y2 H1 x* N1142894 FSP GUI Ability to RMB on a header and select `Hide Column?
`+ j/ Q5 {9 n( A4 |) E! C9 Z1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
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1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settings?in FSP
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1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
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2 N' Q2 C, b5 ^6 ]# y& Q' t1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
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" Z" {6 J( z' n7 r& L: f1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator0 [8 x+ b a9 N' v, g
3 v& s* _4 Q/ V' ]0 N2 x9 M1145286 CONCEPT_HDL CORE Directive required for switching off the console; P j+ x6 V+ L. F
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1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
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0 d7 u0 L0 V0 i- x8 C$ n4 O3 Q0 U. J Q: K) h1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
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1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
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1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.& ^5 Q4 Y; X9 d' o/ i
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1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg( v- s: L: w- _8 `$ @+ t
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1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
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1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
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1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.0 ]! O/ U2 K" S+ q+ ?+ i: M4 O/ h
O3 @' S( ?" @2 Q! ~5 k1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
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1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.* x- r# D T' ]8 m" w, `/ \
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1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
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; k/ `- d. `& j0 A c1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?3 x3 U/ [# q+ g5 ^) [, C u% e
3 |5 Y. V2 T0 M& i$ h( u1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
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% ?3 q+ V R) N& l0 ^6 P g/ w5 X1 q1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
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+ s' U. ~& F( B& i0 s* w1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
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1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out
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" H% Q1 q+ `' k! L+ A1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle' G& z' ~( [* x
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1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.* `5 f9 b6 [: Q* s5 ?+ f9 S$ e. p
; t( M( B7 s. G3 o# s1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file7 x, m# Z3 N5 |) p+ ~
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1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.3 t( g% N3 N- g5 i, c
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1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
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# W$ O) C& c/ s- w9 `6 Q+ R1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
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1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation* @" j4 O" k) J( q/ t) V0 E
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1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines
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1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
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; n" k8 x4 r2 p1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
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2 X+ s+ a/ K6 Z/ N6 b; n1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape
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( N: R' n8 i/ ]: |7 k o9 `$ M: `1161777 ALLEGRO_EDITOR OTHER default line width for PDF output5 E g+ @, {( d O9 N9 R
, K0 ?/ Z( a7 R) V3 z& P1 y1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
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1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6
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+ t3 g' H7 W" C% U0 k/ ^& B; N: t1162629 FSP PROCESS "Load Process Option" under Run does not work properly8 ^5 X/ l5 o$ e* L6 ^% {, X& z, i
# d, ~9 }8 Q& h0 B) `/ a9 _" v1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE3 N9 C3 Y% Z% F9 c. @ \+ `
' j! l h/ V: {6 y- ]+ Y1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
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, I2 |5 _( j P% ~) v! H1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.' `2 ~$ }6 y5 _: ~
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1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace9 ?) ^# W9 r* [
& k) ^$ c$ b" m9 P" h/ [
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin, P2 Z$ ^, n7 E9 g
3 S# H/ k0 O3 ^% Z# \$ _8 _" l9 F1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
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1 D! c; J C$ |0 L6 m$ X2 p1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list3 O J9 A& p7 D }/ o
. J( U- ~7 O7 q7 D' O/ M: h. a9 m1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
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) C. d& i6 G0 X1 [% ]8 ~. d" x1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.# O S* r; \& q! Y2 Z/ d
0 i6 U# r9 r. ]7 N! _1 U1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.
$ z% @, P3 `( t1 d P- ?9 C; `. ]( S, S* a c
1165561 CAPTURE DRC File > Check and Save clears waived DRCs! h. h2 P" A+ H
/ j2 g7 b! M. |; T1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
& E- L( Z6 R: u5 E2 s! A/ s# q' b; r" |+ c, I \/ N: x
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)3 u4 b8 \8 \. O) d; t
e# B! l% ?8 h
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
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' r2 o7 _/ d' o, R0 o( n1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
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) g$ z5 h8 `. F, r6 W+ q- H1 r1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle. ~+ ^7 I1 H T% y3 S/ G
2 c$ m# c0 R% `$ e1166074 GRE CORE GRE crashes during planning phases$ ^0 }$ P. q9 r% ]1 a8 V: \$ o( V
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1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed; x: ~, L. Z) m1 X. a
0 q6 `& b2 J8 a3 U0 _1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
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1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
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2 t6 X; F7 Q+ b8 U1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
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1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash1 O; w9 y) U) X( Y% w
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1167887 F2B OTHER Improve message on symbol to schematic generation
: O( q( o$ d% ?# P' T; ]. r# Y3 C3 s: R1 s2 r! [, l( J
1168369 F2B DESIGNVARI Variant don縯 appear in increasing order while Annotate./ d+ x5 Y# \* n) n
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1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD5 U6 ? q2 a- h
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1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
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1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
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1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check% |) }5 k& q# o% c
8 R: b$ c9 e) n/ b+ e1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty4 W# f- `. \% o& |" y, Z
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1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
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( P5 g. t7 ^2 v2 ^$ G% \1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
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1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule, C/ G; b+ g% X' b4 _4 r
6 b5 X% X. j0 _1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file9 k" d1 k' @8 z3 }
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1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
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1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components+ F* I/ |5 J q: p) n+ O9 L
4 V; l: Q6 z. j1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing$ o$ `% o$ h! b& u
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1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via4 {' X7 F/ ]1 f- p; z0 a+ o3 W
9 a+ r+ M! E0 ?1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
. `0 b5 ~8 }. B& `/ g- |( }/ b. ^; ?) S: ]( o! o1 r0 l
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
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3 I" S" X- P$ ?( F; }1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm1 G4 L& H( V- I% |0 H& _2 H3 Z
! u n% ]% }( B2 r% ]& r% S1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific
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2 Q7 _& V# e9 W, v. m8 P! d1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically3 R* F3 X6 q* M
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1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
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# ]$ E/ _ n+ k* i1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
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! }8 O, G! m6 b; U/ A1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl8 v, F. i: V( x6 F9 i" [; s
8 r6 J$ Y! E. h8 G1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.% t# M% j6 C+ U8 h S
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1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height% A$ \6 f8 x9 g+ W4 {
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1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
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1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.+ c% o! X& e! v- p4 P/ r$ Q( _7 z
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1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
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4 C/ i. r% N, |4 _4 }1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.% I3 g. p7 Z2 X, W* d
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1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
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) B1 X# k2 }' s" ~& Z4 p# s1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version. x0 s& T& P# W+ f
. x7 p/ r0 ]; `' ~1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
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( C* `) O- }2 G1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin; J& K7 I/ j! V# X7 N
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1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
+ A+ N4 K! ]" Q) @7 j# F& l6 A1 t/ n- n' ~5 V; k4 j
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box
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; q+ r3 o) _: J( L+ i" t* e# i1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
+ W; U) H( O2 j6 B' e8 X3 b+ G3 o6 B/ h" m0 {
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!" Q; {) u) A( ~. Q6 v
3 G1 M7 w K& m3 a, b. q
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up. y7 P; D; {1 D# b
7 r9 T7 V3 O& I% M7 t7 O, r1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash& w; w, I0 O* o: W# D! D) ^
! V" z9 Z+ p! Q+ ~5 _/ o1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
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1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
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1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
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7 q7 Z6 @, F5 u: y, e' T) h1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks0 z* ~1 x7 g- P4 L' A# C3 E
* [& m1 x9 `( Q6 B' m! n1 N4 K1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.0 z( h& i+ p4 R9 c m, [
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9 I( ~2 Q2 H6 @$ X% K2 ^- [: d( t
Cadence SPB OrCAD 16.60.016 Hotfix
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# z* I' f+ k& l/ _& QDownload uploaded
! f3 _, s q8 v9 @2 X; lhttp://uploaded.net/file/lo9hy18c/ceenS1660016fi.rar9 G, r4 Y T0 M% Q( @+ A/ d2 K% t$ }
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Download filefactory9 G5 k* b6 l C& L; v4 j( U7 z+ r5 K
http://www.filefactory.com/file/6t9yiqdubs8t/n/ceenS1660016fi.rar
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) \$ l& x; F0 v% [Download 城通网盘! [' C# ~8 ?, H2 J
http://www.400gb.com/file/31016333, M5 z5 j0 P5 C3 n' p e# k
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Download 百度云( X1 B( Z0 M7 W
http://pan.baidu.com/s/1n9yPG
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发表于 2013-10-5 20:59
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