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HOTFIX VERSION: 002& B- c+ v+ U- Q0 R9 _
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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! F+ ^* _/ f& F9 e511865 SPECCTRA REGIONS Diff pairs should adhere to constraint area
; M2 v: c7 ~* T. ?$ f8 j564589 ALLEGRO_EDITOR OTHER The show measure command should show the actually measured po6 F* q1 y: e( \' [# U& C
570861 CONCEPT_HDL CORE Unconnected mark does not be removed even after wire is conne& R0 M/ L& G/ `) U; H
572188 APD PAKSI_E 3-D model extract failed, a( K& Z1 x) Q$ y1 l
578164 CONCEPT_HDL SKILL Cnskill crash during Create Test Schematic step when large pi
% @. i4 {2 B/ w7 F578874 SIP_LAYOUT DIE_STACK_EDITOR Stackup editor in SiP fails to add layers above and below top6 h3 g' X* j2 C/ e
580315 APD ETCH_BACK Etchback trace fails with error "W- An etch-back trace cannot. g3 z M( a5 J
582308 ALLEGRO_EDITOR OTHER Create Detail for bondpads rotated at (0,90,180 and 270) angl
G% |# `- Q- F* F; |5 \" I. q594370 SIG_INTEGRITY OTHER Wrong description in case update form when changing preferenc- m( s% b j# b& k+ h2 b7 N
595755 CONCEPT_HDL CORE Rumtime error happen when do Move Group in conceptHDL
9 {! T/ f8 ^& L% ~5 h$ P597922 SIG_INTEGRITY TRANSLATOR spc2spc doesn not handle inline RLGC DATAPOINTS
7 T7 Z5 U* e& x% f K( L% Y) k' |606620 ASSURA DRC Problem with density checks in Assura( J1 P7 |' S4 w5 }- T( G! T
609866 SCM SCHGEN Schgen replaces CTAP with COMMENT symbol which causes net sho! ~. |7 x/ ?' _- h7 l" E
611678 ALLEGRO_EDITOR GRAPHICS During Place > Manual Pins disapear if component is on bottom
/ D* v. ?* t, ? r615630 ALLEGRO_EDITOR GRAPHICS Pins are not visible when place manually is used for Bottom s
, |. g' Z. ^$ \615764 CONSTRAINT_MGR TDD BOM report does not filter parts with BOM_IGNORE
) a9 Z( p6 q) B; V! l+ z1 U0 D5 K616529 CONCEPT_HDL CORE 15.7 Design Entry HDL fails with Out of Memory message; q4 M! Z& ~. l+ m
616928 CONCEPT_HDL CONSTRAINT_MGR Net_physical_type and net_spacing _type constraints not sync'9 R( b9 v( l6 S6 b! _* J, X6 i& z
617441 SIG_INTEGRITY FIELD_SOLVERS Reflection simulation fails when using wideband vias
2 h' y. X/ V+ Q1 W4 p617679 ALLEGRO_EDITOR COLOR The color palette will not be saved with the design unless co( y- E4 O0 ]9 s O8 c
617805 CIS PART_MANAGER Capture_crash) A" e1 p8 [' L9 j5 T* L
618988 ALLEGRO_EDITOR SCHEM_FTB Long bus names being truncated
+ \* j4 M; j/ V: {3 k8 g* a619588 APD EDIT_ETCH Poor routing performance. 5 second delay after each mouse cli
6 O2 O2 c$ \2 c8 }619691 SIG_INTEGRITY FIELD_SOLVERS Problem of EMS2D by using FreqDepFile
, g* p: s2 l$ R619867 ALLEGRO_EDITOR DFA DFA_BOUND_TOP shape doesn't display DFA Audit conflicts7 k4 Y* F9 g" G
620359 CONSTRAINT_MGR CONCEPT_HDL ECSet and Netclass definitions lost in the FTB process
w+ I4 P, T8 m: M3 u: Z620424 CONCEPT_HDL CONSTRAINT_MGR CM restore from definition of subblock removes ECSets defined
* Z4 Z, I/ U8 W620700 ALLEGRO_EDITOR PAD_EDITOR Shape has bigger void on Y direction for Oblong SMD Pads
4 A1 F+ a: d/ k% t620868 SIG_INTEGRITY PAKSI_E Wirebond material conductivity is not used by PakSI, only a d" Y7 b8 P# p0 |- U2 \. C9 w
620895 ALLEGRO_EDITOR DRC_CONSTR About error message of cns_design command.2 ]7 b& M L" W( \6 O! A
620924 CONCEPT_HDL OTHER PDF Publisher 16.1/16.2 can not output some Japanese characte
& A% V9 m* f1 e; V' } T" B) `- m- x621156 SIP_LAYOUT ASSY_RULE_CHECK ADRC Rule for 揟race Minimum Angle to Pad?not showing all th
( V- T( L! S; r6 v9 U1 i, t' S2 [621163 SIP_LAYOUT ASSY_RULE_CHECK Ambiguity about the how is the 搒tart of the wire" defined in
" X, ^8 Z9 M8 e/ b! q621298 CONSTRAINT_MGR UI_FORMS PCB SI crashes when importing a constraint file into Constrai3 e/ g! X {" k, I4 T/ v5 o
621315 ALLEGRO_EDITOR PLACEMENT Getting wrong component when using Place replicate unmatched
8 ?2 d/ ^" V+ [7 E9 P9 A8 j621848 CONSTRAINT_MGR TECHFILE techfile write fails with Failed writing object attributes/ a6 M' S( S5 n- o+ H
621867 ALLEGRO_EDITOR TESTPREP Transcript window randomly locks up when running TestPrep6 C9 d% [3 Q$ |/ O
621901 SIG_INTEGRITY OTHER Incorrect extracted via drill/pad diameters and missing inter l2 ]$ [, u4 u1 ]; s+ b1 s6 R
622010 ALLEGRO_EDITOR DATABASE Undesired openings in Negative shape
/ I) Z* D% L" d' ]622062 CONSTRAINT_MGR DATABASE Importing dcf file at system level crashing the Allegro PCB e$ f, ~# s) s, m; b/ u, F# g# U
622156 ALLEGRO_EDITOR SHAPE Thermal/Anti value producing incorrect void sizes$ r2 X% T. Q4 r; }2 P5 A3 V
622450 SIG_INTEGRITY SIMULATION Field solution failed& n. G0 u7 J! j- v& g5 ^
622466 ALLEGRO_EDITOR COLOR layer priority in 16.24 P! L# E% O! `+ ~5 w# l. O, ]
622566 ALLEGRO_EDITOR SCHEM_FTB Replacing the components of same refdes on board after import$ p* |8 D8 f9 C6 {: N) ]) L8 i# ?
622700 APD PLATING_BAR Plating Bar Check is highlighting Nets that appear to be conn+ ]% o" |& x, y
622862 ALLEGRO_EDITOR ARTWORK Allegro crashes when we enter a value in the field file size
! a* a8 j; a* U7 R9 F) M622989 SIP_LAYOUT IMPORT_DATA Type of Wirebond die changed after die import# t2 x. V# n( s* ]+ i
623182 SIG_INTEGRITY FIELD_SOLVERS Extract topology crashed: G% W, l0 g& R, `0 f
623300 SIP_LAYOUT 3D_VIEWER Wrong placement of Solder Mask Bottom in 3D view file, M+ k' Q z4 |# t
623384 ALLEGRO_EDITOR VALOR Valor output showing padstacks on 45 degree angle wrong in 162 P) f$ i+ y& }4 S
623489 ALLEGRO_EDITOR EXTRACT Allegro tools Report etch length by pin pair takes forever to9 N1 F0 U7 F" F
623529 ALLEGRO_EDITOR EDIT_ETCH Manual tandem diff pair routing has been lost in the 16.2 rel
( J, ~( J1 E4 [% H, N- g7 a8 s623536 F2B PACKAGERXL packager fails with memory allocation error' p# y0 L1 U7 l% r/ L y2 O
623673 CAPTURE OTHER Unable to get capture window size to full-screen in dual disp6 g/ L: T' H, V3 L& s, f. q# |. T6 W
623701 ALLEGRO_EDITOR OTHER 'Analyze' menu missing when opening Allegro PCB Editor L - Pe' Z# }3 J# R( s% b, J7 c5 z
623738 CAPTURE PART_EDITOR Create part from spreadsheet is not working correctly
: Q7 }) F4 e L* @3 ~: V# H$ S623740 ALLEGRO_EDITOR OTHER Can we use variant.lst file as list file in find filter
6 U5 }$ o! I, f4 \623745 CAPTURE OTHER Capture crashes when the user tries to place markers
2 v/ f. A$ `0 y h. K& P5 C623813 SIP_LAYOUT WIREBOND Add wirerbond only is not working in this case with a bondfin
9 q/ i" m( P2 w623830 ALLEGRO_EDITOR MANUFACT backdrilling is drilling through component pads on the bottom
% e) O8 B& W* v/ }' d. _624048 ALLEGRO_EDITOR OTHER Viewlog for Export to 16.01 is not closing from any of the 'C9 e' g1 b x5 E; S
624223 ALLEGRO_EDITOR GRAPHICS disable_datatips variable is busted. s* k9 t8 P+ C- Q: u% o
624495 ALLEGRO_EDITOR SHAPE Static shape did not void to drill holes/ E3 Q& H/ V" ^0 f( l0 z. T5 S1 q$ g
624599 SPECCTRA ROUTE PCB Router hangs on route of design$ l0 J' p: k4 ^3 Y4 v" A
624653 APD BGA_GENERATOR BGA Generator fails at 400um pitch B0 B% K: F0 ~7 }' v c; ]9 c. L2 S
624812 CONSTRAINT_MGR ANALYSIS Importing dcf at the system level causes RPD constraints not
- ?: @, I ?' i+ p1 Q624888 ALLEGRO_EDITOR DRC_CONSTR Regions and RCI's Cset not working as expected
1 N; l" o! b& \3 Q; Z8 D624958 ALLEGRO_EDITOR EDIT_ETCH Slide in region is changing etch to min line width
: k4 R; u [4 S1 }1 a625251 ALLEGRO_EDITOR COLOR 16.2 Linux allegro - new subclass created does not reflect in3 a# t' T! ^+ l+ W
625273 APD IMPORT_DATA Import a .mcm into SIP in order to edit the die pins. Edit ->
5 S& x6 h7 O2 Q625279 APD DIE_EDITOR die text in fails when the function name is >31 characters wi- m: f+ ?& t, I; \
625304 SIG_INTEGRITY IRDROP Need a better understanding of absolute current values report
( l }: k3 L0 }+ z$ r* S% J( [625367 ALLEGRO_EDITOR DRC_CONSTR drc_fillet_samenet does not work correctly
8 l. x2 d5 S) E: L' m' f1 q625551 ALLEGRO_EDITOR SHAPE Dynamic shape is not voiding to route keepout correctly
/ f) a2 C8 B( ~: `7 v7 K" |625852 ALLEGRO_EDITOR DRC_CONSTR Some buses in CM are disappeared after import CIS 3 .dat netl! w$ Y! Y" d, g$ n
625885 CAPTURE DRC Report misleading Tap connections check for DRC reports error+ n) M3 b3 M3 k5 l. H
625972 CONSTRAINT_MGR TECHFILE techfile import fails with Failed writing object attributes
" q% J+ {( A+ @+ L8 U/ X9 d5 s626630 CAPTURE NETLIST_ALLEGRO Capture 16.20 hangs endlessly but Capture 16.0 prompts result
* [+ e' Q/ x5 G626669 SIP_LAYOUT OTHER 16.2 radial router find filter does not have option for bond
1 p2 @. l K; t) z7 o/ ~# P [8 ?626671 SCM OTHER Adding signals in ASA is taking too long# S7 U5 P, X3 K' o7 X2 p
627228 ALLEGRO_EDITOR MANUFACT Dynamic Fillet is disappered, when use slide command.7 F( k$ x- ^2 s& I- o
627289 SIP_LAYOUT DIE_GENERATOR Pins connect at the same net name after Die Text In! f5 g; ?( l1 l* N. J. @4 u
627864 CONCEPT_HDL EDIF300 EDIF c2esch crashes
3 z/ R b; s0 [9 f( ~628169 ALLEGRO_EDITOR OTHER write command changes design name in constraint manager7 q7 S# H4 H& W7 y- C
628220 SIG_INTEGRITY SIMULATION Reflection simulation failed with filed solver "EMS2D"+ ]$ Y' v) [% h0 V& X0 m
628261 APD OTHER no "Tangent Via Line Fattening" in APD products
9 S$ R8 w* l7 [6 f' b; C6 t6 h' T628922 APD REPORTS Metal Area Report shows 0.00 on one layer1 [# e6 j- r) V: o
HOTFIX VERSION: 001
! Z- q5 ~4 d1 i& F========================================================================================================$ r6 m; u1 m1 L6 z% D; [
CCRID PRODUCT PRODUCTLEVEL2 TITLE
) ?$ }4 a+ b# z. e% d, [======================================================================================================== A0 ^4 y' [1 Z9 O+ c7 b6 U
191020 ALLEGRO_EDITOR SHAPE Shape edits results in same net DRC being reported.$ b3 E( H' T1 c$ w: d
230469 ALLEGRO_EDITOR SHAPE Allegro improve performance of Dynamic Shapes r. X3 s- O1 X% o# c
295039 ALLEGRO_EDITOR DFA Allegro DFA to be enhanced to include height
: M+ ]" Z! y% Q& d- R346863 CIS DESIGN_VARIANT Variant View mode is not working for multi-section parts# j F4 {0 j% r
400036 CONCEPT_HDL HPF nihongo_vector_font should be listed in the Plot Setup GUI
( [/ s0 u; z0 n8 W, A410092 CONCEPT_HDL OTHER The Imported sheets loses the write permission for the group% _. f6 P3 X2 K' ?1 z3 W) S; B
415462 CONCEPT_HDL MARKERS The SPB157 Markers does not normally display the Japanese fon
. K7 O# f% ?( K" f501802 ALLEGRO_EDITOR GRAPHICS When hilighting parts or nets the system is inconsistent on z
5 W7 Q/ I! i/ ?( a% W" [ {503526 SPIF OTHER SPIF is NOT defining class for class to class rules.
- l$ N0 b5 b2 z8 E( f0 N511175 CONCEPT_HDL CORE Copy All causes - No object selected error
: s0 g8 J- ]! i* U' q/ j0 c: ^526774 LIBRARY DEVELOPER Pin抯 text size goes back to default size after change pin na+ J; o, g. L* x0 A. x. J. Z
533536 CONCEPT_HDL OTHER The font used in published PDF is not identical.
3 Y7 J& e2 ~8 d; w5 P537769 CONCEPT_HDL CORE Sporadic behavior of DE HDL toolbars for adding components ge& @! L7 Y" v$ ?+ b4 Z1 v
544519 ALLEGRO_EDITOR MENTOR mbs2lib Generating extra "b" version of footprint during tran- r/ H# {9 T( D* D& Q
551528 LAYOUT OTHER Layout2Allegro L2A translator not translating reference desig
! h2 [& ~1 C- ^" w. r551614 SIG_INTEGRITY IRDROP Import and export of IR-Drop setup
6 F+ c9 ^( J, k1 k552127 LIBRARY LIBUTIL When -lib is missing from con2con PTF files get re-written in9 t. |7 s) N) f: u; J) P. b/ ]
560417 ALLEGRO_EDITOR OTHER Part Logic does not read part row from ptf file and assign in& |; [. t' L* x3 E$ a% x9 i" a z/ t
564954 CONCEPT_HDL CREFER Crefer attaches $XR property to other $XR on RHEL.
: O2 ^' l6 f/ \. E: i) D3 ~565798 CIS DESIGN_VARIANT all the sections of mult part package are not coming as DNS i+ S4 ?. ^ }2 d' N N8 ~3 N
571627 CONCEPT_HDL CONSTRAINT_MGR cmuprev fails to synchronize constraints on low assertion vec
# X; G& A) e7 v9 e ^577915 CONCEPT_HDL ARCHIVER zero folder is not archived how the archiver is working ?
" X; R& z" Q/ y7 j( r581446 LAYOUT TRANSLATION L2A fails with pin numbers do not match between symbols from
% P, i* Z/ S4 T/ z3 s% V. B583891 ALLEGRO_EDITOR MENTOR Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)3 e# _4 _9 d6 ?6 n8 g. y# H
586998 ALLEGRO_EDITOR PLOTTING Board shifts towards top left when plotting at higher resolut
7 x- V. i0 g/ I4 A587870 ALLEGRO_EDITOR PCAD_IN Import PCAD fails due to dupliate pad name. Caused by a peri4 s. n, k* T! o3 `6 h2 m
588949 CONCEPT_HDL CORE Importing schematic pages from another project crashes Concep/ O! T& n( o" n
592340 ALLEGRO_EDITOR MENTOR MBS2LIB not creating the correct shape in symbol7 p5 `/ _: B& b+ C+ E
596530 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translator removing/renaming reference design( t: I- u1 }1 j3 Z: i& l" E
596638 ALLEGRO_EDITOR EDIT_ETCH The timing meter indicates untruthful violation: f4 B4 x \) _. p9 P
596716 PSPICE DEHDL Flag error due to part pin mismatch while create netlist
- O& j" b; C' c+ P0 x( @( G" |597685 ALLEGRO_EDITOR SCHEM_FTB ratnest are out of date error in DBDoctor after import logic/ e7 _; t; N5 l
597937 ALLEGRO_EDITOR PADS_IN Request PADs_in to translate keepout areas/ c5 T: r' l# M" Y1 P+ E9 ]
598575 ALLEGRO_EDITOR OTHER During Split plane should it use settings regarding fill styl
( \0 e/ Q# U9 C* g3 Q598814 APD WIREBOND bondfinger does not move relative to its origin using ipick' P: l T+ E2 p) q' h
599823 CONCEPT_HDL CONSTRAINT_MGR Lost ref to dml-lib causes loss of cm data even if the refere
6 }* z O6 A( w8 p, [599886 APD EXPORT_DATA bodygen batch tool is failing to generate .css file
5 e! \( Q/ X$ \" T- _% j603425 SPECCTRA PARSER Do file fails Syntax error in command unexpected end-of-line
) }1 ^4 F* m' v6 w& ?603987 APD OTHER Offset via generator should ensure pitch distance is met or e
. u& h, k$ ]* [. W0 O604377 SCM PACKAGER Output board name containing a dash causes scm crash& I! J2 K! ?+ D4 j& v1 O+ q x
604614 CONSTRAINT_MGR OTHER netrev is unable to update the Canonical paths with the new d
! Q9 G' }4 S3 \604794 ALLEGRO_EDITOR PAD_EDITOR Replace Padstack reports error pad missing not true.& F5 f+ V3 \5 P: }
605169 ALLEGRO_EDITOR OTHER Can design_compare handle swappable pins?. n# c- }8 [/ G+ Q3 A- ^ v- k
606586 ALLEGRO_EDITOR INTERFACES Multiple drill in padstack cannot be shown in Pro/E IDF% p1 ]% T+ z) e! T
607217 APD IO_PLANNER wirebond die replacement from IOP
2 Q7 a. l+ E4 `9 d0 D+ z2 `- D607222 APD WIREBOND auto wirebonding creates wirebond with DRC% x; i2 _- M5 D- l8 s' |# |4 D
607644 ALLEGRO_EDITOR MANUFACT Enhancement to increase the IDF export ''default package heig
' y. e" f) {6 o607718 CONCEPT_HDL HDLDIRECT HDL Direct Errors reported while generating simulation netlis! e* P0 x7 B' J8 B8 j, v% L$ b9 M
608233 SIG_INTEGRITY FIELD_SOLVERS Convergence errors with analytical vias when drill size is 16 J! k. j& E$ ]4 t( O1 B, _
609549 ALLEGRO_EDITOR INTERACTIV Mirror Geometry command to change BB Via's layer.
3 {0 O( _7 K; U5 j! G+ y2 y7 P610028 SIP_LAYOUT IMPORT_DATA De assign NC nets during aif import- I# G, m, x5 x* E% e% v% u7 H
610134 CONSTRAINT_MGR INTERACTIV Cross-probing from CM to Allegro no longer works on system le/ F. E' z: r K: e; w2 e
610276 ALLEGRO_EDITOR PADS_IN PADS to Allegro translation is failing with error.6 L% z* Z. {+ T" u9 ]5 j
610482 ALLEGRO_EDITOR SCHEM_FTB Netlist swapped net names on 2 pins causing shape to lose its
0 T! J# j1 ^- W* w8 L# g6 ?610681 CONSTRAINT_MGR DATABASE An exported constraint file can not be re-imported in V16.01
s# \3 Y* U4 u0 Z611260 ALLEGRO_EDITOR DRC_CONSTR Routing a diff pair it does not follow Physical line width se3 _2 Y$ \3 h. A9 }. x; g$ O3 {
611425 ALLEGRO_EDITOR MENTOR mbs2brd crashes when importing Mentor
! s# { L d0 @) R3 s611697 SIP_FLOW SIP_LAYOUT octagonal bumps have offset in SIP compared to the chip view4 n/ |1 Q! t$ j7 v7 [9 o8 s7 B
611807 APD WIREBOND Duplicate paths created on wirebond import for some cases.
1 F, r8 t ~' T4 `. ^611856 CONCEPT_HDL GLOBALCHANGE Ref des deletions after runnning Global Change to change $LOC
. o) [! S5 s9 Q9 V7 h$ s7 T& F9 j611874 CONCEPT_HDL OTHER Crossprobing one symbol in Concept using Occurence edit mode
8 H' b( ~7 ?7 E& a$ A- n! Y612088 PSPICE DEHDL_NETLISTER Fail to create the netlist for G value expression- d) W/ Z& l+ W" ^6 Y1 W/ Q
612195 ALLEGRO_EDITOR DATABASE Adding layers to the default cross section causes phantom tex8 Y/ b. B- r9 [4 s3 X0 |; R+ L
612237 ALLEGRO_EDITOR SKILL axlFormColorize does not change the full background area of a0 Z. O$ L$ ]0 p. V0 d2 K
612299 APD DEGASSING Degassing static shape creates voids inside of voided areas
: g: `; e" A# v612560 CONSTRAINT_MGR OTHER Diffpairs don't show the CSet assigned through Net Class
0 A' q; t. x/ J9 ?: D4 I612587 APD WIREBOND Unchecked Allow DRC option creating disconnected wire bond.
) g# H- f: ~. q! |612884 SIG_INTEGRITY SIMULATION When using ViaModel% L$ S! z( l$ r
612914 ALLEGRO_EDITOR EDIT_ETCH Centered via option in fanout command not available when swit
0 J% R& n# L- R6 Q- M- H; w# B612939 SIP_LAYOUT ASSY_RULE_CHECK ADRC Continuous Solder Mask check problem4 O- n. ?: U! ]; v/ g
613553 CONCEPT_HDL EDIF300 edif schematic writer crash on this design
, R* a' L8 m$ c: A2 f613565 ALLEGRO_EDITOR EDIT_ETCH Allegro Editor Differential Pairs are routing incorrectly
% ~4 t- E* `' R& T613736 SPIF OTHER Spif fails to write class data- @, r8 H/ y- t% F; G
613990 POWER_INTEGRIT INTERACTIV PI is crashing during capacitor selection% w7 `' M. w- e6 z+ ]
614278 CONCEPT_HDL EDIF300 pin text note and flag are not visible on reloaded edif file
0 F ^8 L, f- E# q( K# Q614371 SIP_LAYOUT WIREBOND Any wirebond command crashes the application
2 z# [% E3 o# v/ s% ]: c1 r! H9 f614407 POWER_INTEGRIT INTERACTIV PI crashes when editing capacitors% k2 }) g2 H- D6 u
614727 SPECCTRA GUI Allegro PCB Router can not process the dsn and rules file for5 s5 H: u! t, M2 W$ q& t9 a# I! ]: j. I
614972 ALLEGRO_EDITOR SKILL axlCNSSetSpacing does not change the value of the "testvia to7 P/ q$ T0 m; b4 N$ ?/ Q; ~
615144 SIP_LAYOUT 3D_VIEWER die placement does not change with changing in soldermask thi1 H0 K& t, h( A( \% Y- m
615431 LAYOUT TRANSLATORS padstack names are crippled or renamed if it has over 18 Char
* X# X: m- j9 A& k% A/ I2 U615506 APD MANUFACTURING Sort by die pin location for Manufacture Doc Bond finger brok
3 K0 c. W2 d, q) }/ Y615745 SIP_LAYOUT DATABASE Move die symbol with stretch etch on is disconnecting wires f% Q! j& q) r3 Q0 |! n
615816 SPIF OTHER Allegro match group members not translating to PCB Router; mi
* T6 C) w/ ^, \' K616104 CONSTRAINT_MGR OTHER allegroTechnologyFile XML format issue
- `! f. h& D" E% g616122 LAYOUT TRANSLATORS Protel to MAX translator problem with package outlines and re
, N+ a! e- f* P$ p; Y1 r2 r616404 ALLEGRO_EDITOR OTHER Design compare fails with message "Invalid input argument" wh1 j$ g# S% P) ?9 T
616713 CIS PLACE_DATABASE_PAR property name with "&" charecter in access database causing c
9 B* T$ N" N3 w& O3 ~616818 SCM PACKAGER BOMHDL -type scm fails on schematic block
/ {! @# Z9 S0 z5 [+ n$ ~616907 SCM VERILOG_IMPORT scm crash during Get Module Name: `1 r% y& A: j: j
617058 APD WIREBOND wirebond space evenly does not work for fingers on power ring2 M7 Q( |* s2 t& E9 o
617083 ALLEGRO_EDITOR INTERACTIV Windows tabs hangs on Linux1 z- w3 J- A& l/ d" n
617236 ALLEGRO_EDITOR SHAPE Editing a shape in a void causes the bigger shape to drop seg/ t3 C2 r4 E2 M' V- J! f
617351 CIS DBC_CFG_WIZARD XML writer fails if DBC location doesnt have write permission. S" e6 Q7 r; E# m7 N
617515 SIP_LAYOUT OTHER Be able to invoke Velocity from cdnsip) T- I" W; d- ^6 d3 l
617761 LAYOUT TRANSLATORS Value property for Library symbol of Orcad Layout is not tran
: _+ z& o3 h& d5 [, N/ ^: \, e617890 SIP_LAYOUT WIREBOND Push and shove on Bond fingers with multiple bond wires cause
M: Y; j& d, ?7 O4 M( L618184 APD OTHER database diary on unix/linux% N5 q' [$ N! ?' D+ A2 [: q- O: b
618201 ALLEGRO_EDITOR OTHER Dynamic fillets take a long time to complete
% h3 k5 B- n8 F/ [+ ?1 M618545 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we place a package symbol for Jumper usi' v, N" w/ ^- ~# B1 |+ |$ P' w0 ]' A
618610 ALLEGRO_EDITOR MANUFACT Delete a cline seg creates a fillet+ |! Q. m3 ^; `9 x' H
618651 SIP_LAYOUT IO_PLANNER Bondfingers and die are shifted every time an update package
; f- H K; X7 O, w( P8 m618712 ALLEGRO_EDITOR EDIT_ETCH Shove mode is not working on Diff pairs in PCB Design L
; P3 O1 [: l O; v3 @2 m4 d' H618836 ALLEGRO_EDITOR SCRIPTS Allegro does not interpret recorded macro script files proper
W3 g9 l# K. d9 i, Z618946 ALLEGRO_EDITOR INTERACTIV Allegro crashes while using Place Manual -H
. g7 ~8 N; C/ p( p0 `7 _618984 ALLEGRO_EDITOR COLOR Layers on Allegro Canvas does not match Color Dialog Box% Q5 U! u2 z* E
619007 ALLEGRO_EDITOR SKILL Skill command does not accept spaces in file path/name
# f0 V4 _. S3 p' i: Z9 D619033 F2B PACKAGERXL Pinswap lost on backannotation
& F7 R( l V$ T619268 POWER_INTEGRIT SIMULATION IR-Drop can't sees via on pad as open
1 X. U# u! b$ l3 [ f619356 CIS FOOTPRINT_VIEW Footprint preview only from 1 directory in Capture.INI
5 o3 V" m3 b$ c- d9 G% q2 o619712 ALLEGRO_EDITOR EDIT_ETCH Unable to route in the Bubble Mode for Partitioned board8 f0 i8 F+ s/ l4 T- w% |- D
619773 ALLEGRO_EDITOR DATABASE Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
9 V& H- o! {; o3 U! d620064 CONCEPT_HDL CONSTRAINT_MGR Loosing Diff pair constraints from lower blocks when packagin6 h6 I% E6 h$ a" K8 y
622132 CAPTURE NETLIST_ALLEGRO Incorrect ALG0078 error for complex hierarchical design |
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发表于 2009-2-11 23:03
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