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本帖最后由 partime 于 2016-8-10 20:06 编辑 * T- F2 R" G9 T/ e7 s; M
& ^1 ~0 v4 K! H* h9 [不知道有没有人上传分享，我刚下载上传过来，现分享！# d( Y- C( }& q2 e" u
链接在下面，回复可见。顶起来，让更多的人看到！还有CCR，可以看看都修复了什么内容。
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 u( w2 r. I+ P
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) Q1 n. D9 k0 F7 E- b: w, @$ e 1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result8 x& |5 _0 ~8 R, L4 H9 u% w9 y- d
1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
4 B4 j+ t( k/ G0 l 1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once
1 |' X1 v, }9 P, L9 x 1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly
9 d- M! P7 r, _' Y% b9 f) A7 U0 v 1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found) `% A$ }9 e% E6 p( f% `6 r8 K
1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes' q j; ~! \" j% s4 b
1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
& l: k7 }6 e- a4 o 1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties& P0 R4 I3 {# y' h8 p4 E1 M/ u
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed
9 ^0 |: ^/ D) } 1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
# V5 j i. i1 v( k 1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component8 ?& V' z6 H' Q
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior
. R5 V4 a- p' G/ P 1590639 CONCEPT_HDL OTHER DEHDL crash when importing design7 Z' f7 v2 T/ D
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM
5 J' y: \& `' P+ ?; ` 1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
4 w! z: c: w# I 1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view$ D* Z+ M# {8 B: e. M5 G& ` }( }
1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
, H8 h, k8 B- ^+ v 1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
5 ]* T5 l! `9 {+ ^+ l* [ F" a! t 1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI+ _" S* b& I" p! V
1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas
, j m( U: g7 M. z) N- w 1598629 F2B PACKAGERXL Export Physical crashes
& Q$ I9 n" Y# x; _: X: s5 D 1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.9 `, \4 g5 T# b( ]
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
% z, P: ~$ v% v 1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group! N; b+ A, k7 d, ^- V) W* `
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol7 R9 a0 p3 w- Q0 j
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.
' J! E2 D6 ^* [& ]$ V 1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses
' t. d. j: N- ~' u6 X# Y4 e 1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project
8 Y' V, _. a, K2 q. W$ k 1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command: P' Q- u! ~7 p
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
1 M6 g! h; P# W% I 1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error1 n1 m, r3 H4 h8 r* E: m; ^" a0 I
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard& r+ E( q/ Z+ y+ z3 K! W
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发表于 2016-8-10 20:04
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