|
|
Fixed CCRs: SPB 17.2 HF021
4 x9 R' L( c j8 _) P. P5 J1 @0 C* p06-3-2017
{! ]' ]' p& u j% L. L========================================================================================================================================================
- |. p' |5 o/ W/ d, x! @CCRID Product ProductLevel2 Title
/ L9 k* K$ R# Y% [% X# B+ B========================================================================================================================================================: P w. a) i2 l: |+ w4 o( n% ?) X
1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
. r2 O( w0 t( ~1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed& L. ^& h+ }0 G5 Q# _
1743997 ADW LIB_FLOW Match file for standard models is incorrect
& U: ~3 A4 P. ^0 M4 S& [1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
- k: \7 Z" p& e, n" }" z. G1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer" a; M! U3 H+ X
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)3 o2 m6 Z8 c; M4 j% q* \
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command
" }6 A1 N, G1 v1 K( a* g" n1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape7 d1 E& a9 A% `+ f
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops# B( K$ u7 w: l8 V
1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets; B$ j6 ~( L, v8 l. l2 K$ Q+ M- e2 \
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty- }3 Y$ F# \ F+ S: Q: }( R
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor- f: H) i6 T8 l0 {6 |& i8 L
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
- n- D8 p5 b4 c) T$ G1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database# ^: ~( t3 Z4 \
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry9 Y2 N1 o6 n: @9 g0 \; P
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
- V, h5 M" U# d1 t( i- P1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016# C2 l. I2 ]/ n1 i' P! f8 J* T
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated
# @+ ^( g0 w/ p% K: y$ K1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016" R! F* \- T5 `; l; C7 J
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors0 z/ h$ y& x% t# p$ k/ x4 h
1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location, C/ F% k M2 F
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy
& Z3 L& i4 C( O1 N" ]1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working: \5 m U- X4 U- E
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
* o1 c2 M& y* @- ?) i! R9 O6 _. \1750182 APD STREAM_IF The stream out settings are not saved
2 c$ b* p- _; K3 n$ k1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report# C# S8 r0 a; C, l
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version9 l: O5 e6 t! k
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser
" |/ r/ s- `* W7 C1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint
z8 H1 T8 E6 @0 q- r& a' ]1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic4 k4 a6 J1 M- x7 n$ n# x [' ?
1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016% H: k! Z0 }# l# y# q7 l9 F9 w
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design) y; i0 N+ ]4 r$ k( y/ I
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
6 k Y' ?: O+ L+ t1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
/ C7 e6 e8 Q/ L3 X7 N1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016
& m0 `5 z4 I3 |: A0 ?- g) p8 r1753010 ECW METRICS Metrics not getting collected due to old license in use6 i, T2 l y: r' U" P9 Q: A
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance! H( Y$ U8 f' q' l8 v
1719099 FSP GUI Net naming wrong after building block( K& A1 H5 u# C2 f- \/ v
1719105 FSP GUI Tabular sorting not working in FPGA System Planner
w% @- w5 W$ w0 ?1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems) G8 o; K5 M* D: p% t
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems
) `0 S5 M, R4 `: Y3 |) V" r5 I3 S1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016 C* ]3 Q. v' l% P, C8 R
1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing% O, @" f! Y- ]+ y. r
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
9 ~5 K" h0 ?7 O h; {" o1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets
; m0 E' U% H6 y/ T/ x( V1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout& J$ v+ l+ M# _& d! X
|
|
/1 
发表于 2017-7-2 18:37
QQ好友和群
QQ空间
腾讯微博
腾讯朋友
微信
收藏
支持！
反对！
楼主