Hotfix_SPB17.20.021_wint_1of1.exe

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Fixed CCRs: SPB 17.2 HF021
06-3-2017
, W' w" }+ ]" `) \========================================================================================================================================================
CCRID   Product            ProductLevel2 Title
========================================================================================================================================================
2 `# C- N! ]* b5 Y6 U* e( D1401318 ADW                DBEDITOR      Bulk Edit - Previously modified cells do not turn blue when selected
1621446 ADW                DBEDITOR      Bulk Edit - sorting highlights incorrect cells to mark them as changed
: P7 W) ^3 ^" n8 K: z* L) O1743997 ADW                LIB_FLOW      Match file for standard models is incorrect
1746052 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when applying no drc property
: b7 Q8 b6 u, ~" D6 B. ?1736067 ALLEGRO_EDITOR     DRC_CONSTR    Interlayer checks not reporting DRCs between cline and mask layer
4 O- y- {6 M, h% Q, K& }1738587 ALLEGRO_EDITOR     EDIT_ETCH     Line width changing on slide for ETCH - Conductor (Not on a NET)
# c4 o3 k# B2 V1745277 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on using the slide command
3 w' N& ]  c, ~- m4 A( }7 Q/ x1747942 ALLEGRO_EDITOR     EXTRACT       Fabmaster Out does not export arc in pad_shape
8 j5 s, F% B3 U8 N& ]' {# w1737202 ALLEGRO_EDITOR     GRAPHICS      Setting the variable display_raster_ops
1744042 ALLEGRO_EDITOR     GRAPHICS      Unused pad suppression is not working on few nets
# v6 o8 {* u( M  o: i- K3 d1703848 ALLEGRO_EDITOR     INTERFACES    IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty
) O/ A: g3 R* g( K6 S1743899 ALLEGRO_EDITOR     MANUFACT      Glossing dangling vias crashes PCB Editor
# D$ z  ~" {1 U2 g! @# Q1744467 ALLEGRO_EDITOR     OTHER         The 'logical_op_new' variable is not displayed in User Preferences Editor
1 O( d8 C- o+ f6 ^1 b* E1748520 ALLEGRO_EDITOR     OTHER         TDP fails to load on an empty database
1748581 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes when changing default pad geometry
) ]) I( m% G( C$ q5 l2 B1751469 ALLEGRO_EDITOR     PAD_EDITOR    Padstack Editor crashes/freezes when browsing for a shape symbol
" ^2 _7 ]. f9 T$ A1725948 ALLEGRO_EDITOR     SHAPE         Shape differences after conversion from release 16.6 to release 17.2-2016
1729306 ALLEGRO_EDITOR     SHAPE         Seting shape_rki_autoclip variable causes no void to be generated
" J' W1 V6 X: T: S2 z3 L1698876 ALLEGRO_EDITOR     UI_GENERAL    Tabs are large and text is compressed in release 17.2-2016
1698883 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
* N1 b- u, ], f1 Y/ {1707933 ALLEGRO_EDITOR     UI_GENERAL    axlUIMenuFind not locating menu as per x_location
1741460 ALLEGRO_EDITOR     UI_GENERAL    Right-click, context menu options grayed in some cases after choosing Edit - Copy
1747588 ALLEGRO_EDITOR     UI_GENERAL    Interacting with PCB Editor by sending messages is not working
1747488 APD                EDIT_ETCH     Route connect is improperly affecting existing routes in locked high speed via structures
1750182 APD                STREAM_IF     The stream out settings are not saved
1752067 ASI_SI             GUI           Links to differential waveforms do not work in Sigrity SI report
1752131 CONCEPT_HDL        COMP_BROWSER  Symbol view in part manager doesn't match the symbol version
' @, q6 Q7 }, j) d- o/ B$ U1754116 CONCEPT_HDL        COMP_BROWSER  Default Symbol selected is n°2 instead of n°1 in component Browser
  E! r( K( Z6 R1754949 CONCEPT_HDL        COMP_BROWSER  Part Information Manager displays preview window with the wrong symbol and missing footprint
, C8 }1 a1 t/ p6 y1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
1750916 CONCEPT_HDL        CORE          DE-HDL crashes when trying to uprev a project in release 17.2-2016
& a9 g. L8 D) w/ H9 s- C1711487 CONCEPT_HDL        INFRA         Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
1746915 CONSTRAINT_MGR     CONCEPT_HDL   Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
( s; y( |" ?! _8 w1743523 CONSTRAINT_MGR     DATABASE      Suppress warning pop-ups from the constraint automation script
1746941 CONSTRAINT_MGR     UI_FORMS      'Go to Source' from DRC tab is not working in release 17.2-2016
; T7 |6 Q+ j, t' t) O  x9 j1753010 ECW                METRICS       Metrics not getting collected due to old license in use
3 E2 t- I# M8 g; |' r  ?* Q1713052 FSP                GUI           Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance
1719099 FSP                GUI           Net naming wrong after building block
  ^# C+ V4 d9 N/ T  i' g1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
- U' m4 s- ]' t8 {& q# K2 \1720479 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
' K; F9 _5 S+ o1723411 PSPICE             ENVIRONMENT   Probe window does not open consistently on Windows 10 systems
6 q( \+ j! [5 T1746628 PSPICE             ENVIRONMENT   PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
+ N6 {6 t8 B( d8 p+ w1745976 SIG_INTEGRITY      GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
1690820 SIP_LAYOUT         PLATING_BAR   Cannot add fillets to pads with plating bars in release 17.2-2016
8 D) |- ]- I' a% a$ ~5 }1725042 SIP_LAYOUT         PLATING_BAR   Creating a plating bar removes dynamic fillets
& U. K! q" K, p% I" B1747534 SIP_LAYOUT         SHAPE         Moving fiducial crashes SiP Layout