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6 l) G0 G9 K2 a! l! nDATE: 08-14-2016 HOTFIX VERSION: 0043 ]( Y/ y0 L# h
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CCRID PRODUCT PRODUCTLEVEL2 TITLE, Z: ?3 r4 ?6 s. r
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! H- F( H/ R6 }3 h908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked U2 f0 f9 ~8 v" |+ a) z( _
1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)
- M( {" V, J+ y/ L3 q3 `1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE
/ D6 X5 Z- Y$ x1 V% r) W0 E1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
s; R1 ?' {" W% Y. ]$ |5 G1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets
3 R7 f' Z; {+ A8 l E8 N1326716 ADW DOCUMENTATION Dataexchange documentation correction needed' H% X; ]5 e6 A9 F; P- s6 ?6 w9 H6 R9 o
1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large; x) z7 J5 s6 y" j
1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.+ R- O' `( K7 m$ f! x( n$ R
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file+ q5 q5 E* K* `
1410485 CAPTURE SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design5 t& e2 N, S* }+ C0 i' `6 ^5 q
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only$ M' g* a4 f, R5 J! K
1413287 ADW LIBIMPORT Library Import uppercases all Attributes when reading CSV
6 s* Y4 {" T7 t# m. o$ l1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
$ s+ V" l$ E' |1 T+ S1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
, J* F% T8 ^$ e# _1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room& s# x, m; \+ d+ t1 L9 x e5 D6 t- k
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option. Y% A0 ~ L( z2 S
1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the sym1 view are not saved4 {( `+ e2 s- m0 K. X" ~
1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked
+ j( H r+ r& D1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
H. V/ j& E: a+ {, ^% m1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required i" e. [2 V+ [# o
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set$ i4 k' `% T" @( u! z" B1 P
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
* T8 P+ s$ N; a( F ^1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties$ B9 ~( i0 J+ o2 ]9 Y( H' K' G( a
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM
6 y k5 o1 |+ W1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools& W4 s6 i" v$ z! j3 k
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
, Z1 X3 {& |; Z8 |3 [; J1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
! V! p* s" |. Q1 Q1471287 CONCEPT_HDL CONSTRAINT_MGR Importing pages from other designs with different units should inherit the source constraint units ]2 Z- W( Y7 H' h# i
1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack2 ~2 S/ O. U+ A$ C' Z, Q/ ^
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region6 b O, ]; C' U( b' |
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB 054 / ADW 472 p3 ^! w2 ^9 e
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design
! `4 N. h/ I+ N s; N* Z6 u1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled
" S6 e) T' D3 F E/ R1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian, a7 x2 i1 E4 y+ N" k* Y
1474066 ADW DBEDITOR Bulk edit performance lags when parts included have large number of properties
9 w' a8 c4 p& @1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked6 O/ D# R, h4 p! n2 J. t3 R
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
1 M$ A- o, f7 U, ~; C8 X1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
0 \. ^$ F. v! k1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown1 D; F m9 N/ h* @ M
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner.) s' K# N, y6 k& e5 Y j
1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
, i! j6 n4 O! ^6 c6 g1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release1 R5 I7 j4 D4 G$ J
1478200 GRE IFP_INTERACTIVE Allegro give error "Low On Availlable Menory" and then crash
: b0 c6 ?% O+ w8 L3 Y1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys% l, S* C5 | h( d& ?
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy
# ]$ Y$ B$ ^3 s1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon4 M8 W D2 e( K- l8 d
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy* M- x }/ }# ~2 b: R& `
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
0 r/ d5 @5 m3 ^: Z1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053
4 a& R" \& \) f1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO, T+ F$ U: u/ P1 w. N
1480005 ADW DBEDITOR DBEditor/DBAdmin GUI do not allow the same characters in Property as LibImport CSV Files
. D9 M) t# w' \5 A' _3 ]1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol' p( ^8 R, S# g0 e) A& t
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition3 _& V/ A/ e. p S: Y& R
1482544 ADW DBADMIN Hierarchical PPL not functioning correctly/ c6 |$ h6 ^* z0 y9 d- b d& L
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode& r+ R" E: o' T
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles
0 l) r* t! U9 J% ^1484100 SIP_LAYOUT INTERACTIVE Tool crashes when copying and rotating a symbol c/ e; z% O0 }$ u' Z0 l: S/ ~
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
1 X9 q1 T" c2 `( r) Z3 P1 ]& R1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
% V& ?8 m* u ^1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
9 ?( J5 S& r# H' B% U& G1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project) ?2 p6 b+ |7 i7 T- Z$ m6 T; f
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.7 d) V1 v( E6 g( _" B
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager., s; f# v7 E" m N7 c$ u0 s8 b% i
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
" {2 F5 h$ ~8 Z1487125 ADW COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated
5 |$ Z0 d2 D+ _2 @ P1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
9 A8 I+ g( G7 p, t" @1 u4 w4 `1487496 ADW DATAEXCHANGE DX Changes checkout ownership when override action is set to remove existing relationships- Y% e) z" u' A+ J5 {5 h4 m6 ^
1487656 ADW LIBIMPORT PreAnalyze reporting false warnings
1 F V T3 C- J* Q v/ {( v" s1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
9 ?* c6 l" r( G* {1 q# q/ k1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered
4 {2 \) s4 L! w5 p2 g9 j8 c1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
) H- |% b4 `# Z. x1490299 SCM OTHER ASA does not update revision properly
6 [1 ~: ^3 P& s/ ^5 s3 p" k/ z1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer& q5 }/ x7 g6 `2 N. v8 U- H
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints) H5 b* \& f: P4 [$ m' L! M# p+ g
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
9 |3 R* a" B" w, D, p- B8 F6 i1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)( q0 ~* D# u' N4 {
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong! G9 ?+ _4 U, u
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit# B5 I# N' n& R
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
' O( e! K- \+ ?/ \! R d4 K; y P1 Q3 u1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL. Q4 v! p. L5 f1 w& W: a
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs5 X5 d/ N' G; X3 w N' r5 Y5 X: v
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size9 u# w8 q: G. P% a4 ]
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
" @; L6 q$ S$ K! c% d1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
2 ?" C* y( L- Y7 T4 M8 F1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
! R! N' g1 Z- A# S9 D/ J1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch5 |8 D- f7 [- S8 n6 t* A
1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts! S/ P" m+ t4 g
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
# L- K Z3 ~! E) r3 h1 ^7 F5 `9 |1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
! a; o' C9 u" D+ ?1501294 ADW COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration
& g# o" o: x d0 |5 h/ D' S8 f$ K1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL0 Q; [' e! ?7 C( r$ L, X- a( M
1502282 ADW CONF What does Message: 3 > 2 means?
$ R* e; [9 ~7 J! d6 M! D2 Q3 f1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings3 w& b |3 S. Q$ D/ W
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
% C9 \! j+ z: V# ?+ o% [& f6 s1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary$ e" j4 y3 F. s! p& C% m- a$ u7 k
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
( n( q5 g+ M' _6 @, O1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving' N. ?( O; W9 L2 Z* Y
1507497 ADW COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol$ {( A2 C% v( I! J
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
9 J0 M K8 b' v* T# e7 ]" G# C0 ^1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
" B- r& A( r$ j- x( ]1510570 ADW DATABASE ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa
7 Q: f/ h: J$ n/ n* c9 L" b1511180 ADW DBEDITOR The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri
) U/ @& m/ r; g* y1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6) w, A6 i$ K7 e2 M- u0 e1 ~: o
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
0 m% G1 a, q" R4 ?/ h8 g1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.' H; A0 k0 A" i* r; C7 ~" y7 \
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working4 R# E4 W0 X: w s
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor
: E! ~* M) f) s- j0 o e1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib
5 W" U3 L7 [! e* a1513737 ADW CONF DesignerServer from a different network domain does not show distribution data% X- N0 t! S9 t/ ~! D! [! r
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property$ A u. | a8 ]( V5 C
1514942 SIP_LAYOUT CROSS_SECTION Why is AIR not permitted in stackup in 17.0?
E! O. @2 \( f7 \$ R0 S- W1 E1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly# t8 T7 G) G! [/ N5 Z7 L
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol* b; l! K" M% o* I0 e- G
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via
& x% L! }& l& Q* l% k( f3 }( a' Q1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'1 y7 y9 |3 c$ {2 X# I# B
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes6 B# @6 {& Y1 Z* {: Z; E
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
! r% ~4 R H p/ Y& w1519518 CONCEPT_HDL OTHER Genview does not generate split symbols* y6 ?# s- Q8 |
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas- V/ K" H! \1 {8 D0 r4 s2 Y
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
: w, ]" ?/ b, d8 S3 | L* [1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net; ^- C& X8 B; C7 Q# n
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
/ g2 w$ }$ j: I* p4 i# L1520207 CONCEPT_HDL CORE Genview crashes after renaming ports% S j1 A5 f8 u5 N( W. Q( h# S
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic
9 V' k2 h2 v; ~* @8 q( D( M( p3 e1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor
7 X- R) l4 [1 S1521871 CONSTRAINT_MGR CONCEPT_HDL CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning- f0 R; r/ k/ x% ~& \1 `+ a
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.
9 q# W2 N' r# k- o: h1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design7 m* P$ v' J# B0 ]0 J( F) f+ Z
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash* r) Z5 j$ ?; A( c+ |; @7 j
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated7 s7 J* X& j, N2 b0 n$ E S3 r; f
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
$ b2 T- D6 N9 f4 n1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor5 V5 f7 V1 X D! d" a6 j
1525883 ADW DATABASE invoking libimport on an existing DB should verify that the libimp_su variable is set correctly
* d2 g* p7 P6 v; N+ G1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct% z4 W* m8 @ C
1526914 ADW LIBIMPORT Can not import to new library DB
1 ]% Q, U, y6 A' Z/ j- p/ i1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63
( S% c0 `$ \9 x( Q8 y& U1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'. Z! E/ h$ R P+ `) c' \
1528235 ADW DBEDITOR About the rule "Validate Classification Property and Property Values" of Release/Pre-Release
! R* G0 T: H1 A5 r1 W* P1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes
, M& u4 R! O. R. ]' u! x1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property) V+ _7 g! Q+ V/ ?: B1 q! P
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
9 y- n& p, Y7 \1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents Part's release7 K5 R2 U( X1 @' z2 O
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net6 Z7 g) x9 z4 t7 J# T
1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions
+ Q5 y1 r+ n3 e G/ N- c" _1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file4 |$ R7 a: i0 C
1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used: E* C$ _8 Y0 x2 I/ ]! @0 Z
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes
& [" ~$ E% }( ?( j% V1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup' L( i b; E s3 F+ i
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr/ N* o" |8 j- V/ F: { ~
1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists
2 H- S1 F+ [$ F5 X* H1 D1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue1 e, A O* s& V, D: D
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties
& k6 O3 w% j. q C V% V1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net
* W' E0 ^, X& D$ ]7 v# O$ l" D1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform
% x8 o% l D8 y0 Q; q- n, }1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'
2 s1 O4 ?- t- o4 e1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
9 ~7 M1 m! Z2 x! l* _3 W8 f1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run* C3 x$ J# J7 m0 k4 _! C, R
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error i/ m4 @: ?2 W+ |: h& _
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib. r/ `3 V6 Z0 i' R4 C5 r8 f8 X5 R/ n* H
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board; N+ x: {) z, v7 B* H8 q
1542949 ASDA EXPORT_PCB Export to PCB Layout Fails to Accept Entered Output Layout File Name
! T0 I6 H' t/ o4 B( {; \% i1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer! E# B8 k6 y6 V. x$ c# n9 Z, _* q+ U
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash
7 }$ }/ o9 C* n: {8 m U/ ]1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
1 y2 D' \+ p0 s. {" Z# P0 c1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked( v; j9 {9 G/ C7 U% s/ r6 ^
1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.9 d$ B" m* K9 X4 J
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with
( h- N- D" G b% h0 M6 I1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information; o* N, @1 R `. G. P! ?. Q
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'3 G2 _: v5 t, r8 c; T* ~
1549658 ADW TDA Unmapped network folder in TDA
) ^, y( s* b# U1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
, C# D1 g% e: N1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects. `* o1 S" H% n. V% l) v
1553027 ALLEGRO_EDITOR UI_GENERAL Beta - Allegro display freezing very frequently - canvas not resposive and turns white.8 a2 X" S( W$ ]4 o* W; B- J
1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
) G* d. }0 y; G1 ?1 y1555254 ADW DBEDITOR Loose focus on Free Text search Window removes the text.' q7 {( X7 m7 u, u+ I6 ^
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon
/ T. X* r8 s% B4 j) ]1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export- [8 S( M4 f8 W! K+ @" D( N0 m( _
1580571 ADW DBEDITOR xml files for released FP and padstacks are left in flatlib area.5 F8 e* J* {# f
1580580 ADW LIBDISTRIBUTION list files are not getting cleaned up for custom models if they are purged.
4 e/ e. {- N, k1582064 ALLEGRO_EDITOR UI_GENERAL User defined menus not working in 17.2
& u1 A! w; o9 q- C3 H1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes% ?1 h9 j, A7 F5 B6 s* J
1582856 PSPICE MODELEDITOR Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created
5 w' x: I( r1 k: u8 a! A1584719 TDA CORE Caching errors coming for a board ref project while doing Block update
* \! h0 W/ r& m8 d- z1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file: p9 X5 R p" s& o
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option# k5 e9 c5 @! q( E
1588736 PSPICE MODELEDITOR Model Import wizard says "Invalid configuration" when lib opened in Modeled$ |; c$ p7 [9 L3 c- C
1588742 PSPICE PROBE Browse icon is missing from Pspice File > Export > text: J3 q& n3 T3 h2 f ~# A' M
1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened
2 Z8 g$ U% L+ o, r, D1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons
, t7 G6 [$ ^, }0 K8 z9 U$ S1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork- j. o& U0 k4 `7 U
1592089 PSPICE MODELEDITOR Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator
3 }, G7 X+ _; k- [" l' p) R1593436 ADW DBEDITOR new Model type form does not focus cursor in window, User must select the Model Name before any text shows up/ x" O: ?( K" W# Y+ w) F
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified
& W1 D9 ]$ K, ?/ D2 a9 s( z1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode
: P* {: x" T3 }; @; `1596162 ASDA IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well
/ ?% h. [ J* o, Z- Q( b5 F/ P1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names2 P8 Z8 d8 L* K2 u, d! F1 N
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas
" `5 P" U; S$ y' @# d7 m; I1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated
* H& ^% V7 ~" P2 `7 z1600194 ALLEGRO_EDITOR DRC_CONSTR Update drc command changes the amount of DRC count when using 8 threads/ N" K) P5 J _
1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating* m% y4 O- b! _
1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved9 I) x' d. t! P0 D4 K0 m r- \, L$ L
1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.- p- f* j+ m6 L
1603377 PSPICE ENVIRONMENT At Markers Only option does not generate .dat file/ [* |6 \9 U7 x+ k
1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header
! L5 l& k# L R1 ~, l: j! f1 n+ \1604741 ASDA CANVAS_EDIT tcl console changes the present working directory (pwd) when you open the proj preferences & close it.8 _' {+ X2 o, ~! b' M" W
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard, I' f k/ ]; r( J7 p3 ]
1606861 CONCEPT_HDL CORE Crash on Linux during Generate View
, k% Z; ]) {/ @; S1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset
2 ?8 R6 \ m6 }6 N# V; P7 z1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons4 d: C4 A' V( r# E* E o
1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set
7 _! O* a1 ~: v; V1607568 ALLEGRO_EDITOR NC Allegro shows wrong drill legend Top to Top drill.
( ~5 H& _ K* q, f: u: O1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath skill command in SPB 17.2. q& D3 w9 z3 ^
1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.) R9 |7 H8 b; v& F% V. H/ Y
1609400 ASDA CANVAS_EDIT RMB > Assign Differential Pair should be grayed out when a single net is selected# C* U- U4 n; T$ q
1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux" U/ B" G! R3 w7 G
1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.
/ O, Q& c+ P7 b) t1 ~1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only$ {# S/ Y9 g6 U, J I" ]1 A- {
1611226 ALLEGRO_EDITOR SYMBOL Allegro shows crash message while saving flash symbol.
6 e3 _. {% M* g( v1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.) j1 s6 `. s+ t }& e0 u
1613123 ALLEGRO_EDITOR SKILL drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT: {/ f- W/ ^+ I; }$ F; x
1614000 ADW LIBDISTRIBUTION lib_dist does not complete and does not allow to delete the .lck file.! F/ c+ w T1 `- N6 l& }
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp
6 d$ V9 h6 c+ _/ _" }& q1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error
0 y5 z- P5 {" R' W9 Y1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import doesn't map layers correctly$ d" C8 C+ V0 q+ V7 N- j
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update7 d C! _4 F. S+ w# V. D
1616733 ALLEGRO_EDITOR INTERFACES Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated8 ~2 W2 D- Z" \5 n2 g
1618751 ASDA DRC SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file.2 ?' p& x2 l( v; G7 R
1618797 ADW FLOW_MGR Flowmgr fails to execute command
% V6 x$ o' `+ \; z* M% z6 k. F0 Y1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.! o5 A) Y4 o( T( [' i
1620350 ASDA EDIT_OPERATIONS Uupdating version for a connector pin looses the pin number
0 P8 I) x* l3 M0 _- b1621963 ASDA SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol.$ E: r" l4 j! E3 v7 v# I
1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet crashes the tool
/ o- M4 Y2 [0 m# z0 P5 g' @! u e( f1625209 ASDA IMPORT_PCB File Import from Allegro shows board differences' |% S! i' x+ C" L. r
DATE: 07-28-2016 HOTFIX VERSION: 003
# K. I- Q# L! K) s T7 k# V===================================================================================================================================% i6 S6 R! x! L# g1 W, q6 ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 f+ {/ v+ y+ C
===================================================================================================================================2 N; C2 n) Q) J' ^
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result. O+ z0 u8 Q: d/ B+ j# v9 K X: G, H& L
1461626 CONCEPT_HDL CREFER CREFER shown to each instance of block pin though net changes
8 ~$ K( N: N6 B1472456 CONCEPT_HDL CORE XCON and design are out of sync4 N5 A: l0 @0 d ]2 k7 _
1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
: X8 M) S1 r5 Y: H6 a8 n3 W: D1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066
% v& t ^3 V6 b9 |6 S1560102 ADW FLOW_MGR 172BETA: eval in command string does not work) h$ t3 o4 j2 r2 m
1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View
' Q7 N7 s+ S; j9 f3 g1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly+ g8 A2 m- @( H, E, o
1578876 ADW ADWSERVER Component Browser crashes when trying to show details on a part number6 J( O. M* z! I% |
1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found/ s' y# Q g, f5 Q
1582863 CONCEPT_HDL CORE Generate View creates non existent ports7 g L7 f: I4 D$ W
1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window.
1 c. P- W9 V, g3 [" {; Q7 X7 y1587018 ADW FLOW_MGR Project Update at Ericsson in ADW 17.2 asks to specify flow name.* ^" v! N4 y. I7 }+ Q
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties
7 Y* i. i, C1 n5 }1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed
# u6 Q0 S0 _1 p8 y; p9 D: z1587718 ADW LIBIMPORT Library Import Pre-analyze report is not being written
+ i8 _+ B3 t% U4 R0 `, _. w4 O1588197 ALLEGRO_EDITOR INTERFACES STEP output fails when External copper selected on Win10-17.2
: Y. B" q5 G! t- L5 e; L1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"
) e u" m1 U4 l( z2 c3 H. V5 J6 T2 w1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component$ p0 B- ~; d- Q; W/ c2 S+ k1 R8 Y
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC between Embedded pin and via which do not share layers- O$ a: Z( z- r$ w) h2 _ U
1589979 ADW FLOW_MGR Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project
, }; m( t3 P7 V7 S3 y9 H* ^1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior3 z; J+ z- o5 H1 }7 G* B$ b
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design& W- L8 X/ o {: T( W7 y5 x1 P
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM2 o. d7 @8 V/ z7 Y
1590720 ALLEGRO_EDITOR INTERFACES Text Size Parameter file does load names into the text table
8 d3 y0 N0 X& r4 M- U: z1591070 PSPICE PROBE PSpice crash while evaluating measurement from trace>measurements) ~. a! K3 Z" t, h0 A
1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic
. h9 W, Z- m! E/ ?1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived
3 c2 p4 B9 ^% U5 X L1 V6 z1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crash in 17.2
: R2 l/ q- z: Y1 Z1596615 ADW DBEDITOR Component Browser didnt come up to search parts, also the database editor didnt return search results
# |4 g; |1 t- v$ ~* q& h1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save
; [% {1 g! x _ h G3 r1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor; z7 Y! p0 u$ V
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI, j: z& `7 y, ]- ~) W% @9 a5 p9 P
1598629 F2B PACKAGERXL Export Physical crashes
. L" r+ B2 O4 n8 b5 K/ O/ e1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.
6 ? Z" }8 D$ j; ?' Y5 `1599744 ADW FLOW_MGR Few flow manager buttons are not working in EDM 17.23 P% Q b4 ^; H1 p
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.3 q u5 s3 ^0 ]$ L
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group) R7 p5 y' M$ R2 p/ A
1600618 ALLEGRO_EDITOR DRC_CONSTR case sensitive issue with Physical Constraint Set
9 d, |3 l5 \' r) Z5 g4 _, L1600914 ALLEGRO_EDITOR INTERFACES File > Export > PDF shows the shape as unfilled.
( W& p3 O8 m* f) \# F5 q" y1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad1 L. ~! y) R1 V: B- T& g4 Z% L# ~
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol
9 T. N" O1 {& p( A2 C8 f1 |1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.' ^; P1 d3 W, @7 u, ~/ w
1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project# o; t' ]* q$ f! X. W) G9 T
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command
( i! P, Y- z4 @4 i. x1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.
8 \6 w4 j- D- x1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error
* m1 \" R) g& X0 Z1604746 ALLEGRO_EDITOR OTHER In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools.
9 X/ _1 V3 Y. p2 o1605322 ALLEGRO_EDITOR TECHFILE Cadence SPB17.2 Issue - Long duration in Tech File generation
( Z s" r v3 c6 B' p! ^ l% JDATE: 06-31-2016 HOTFIX VERSION: 002
- A; h3 Y- s- X, }===================================================================================================================================
0 E2 h6 L5 S" m6 D* X. YCCRID PRODUCT PRODUCTLEVEL2 TITLE: z8 o! N9 i0 L% u, j( R9 {4 M
===================================================================================================================================
$ p: `/ v: Y- h1 n* ?1 l* b: ~1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets& z7 l" v5 V8 b1 [* I. Q* s& W& U5 [
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package2 t9 H7 X0 N* E' l6 W
1481802 ORBITIO ALLEGRO_SIP_IF import of oio to an existing sip offsets the results incorrectly
7 B5 Y Y3 ]8 t1518957 APD SHAPE Shape void result incorrect, k( e2 _" K- F$ L
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error m" c: {9 U" L! L/ s; O) h$ ~
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly
1 q# Q5 t7 `( h4 E7 b. k5 q/ t) A1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.9 [) L) t% w# y3 G" J( q. p; d$ u
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.
; m0 K# \% U6 y1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.); P k3 A& c9 k9 Z( c9 y; N& K
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set2 K# \4 _9 R# L& D
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
9 u3 j$ A4 X/ \1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library1 D. h4 g0 s1 }" Z( ?8 f+ ]7 O
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG
- i, D6 ^1 d; T2 k0 b& H6 G1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
* {+ ~4 I5 A) y r7 S- A, h1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation, v# x8 X# }6 R% _( ?) G9 a+ \
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
! T% T1 q2 p$ P- A' ?4 p. `- a1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
; V% {2 `2 c6 l4 g8 K1561501 ORBITIO OTHER oio -> SiP refresh seems to hang
3 O! h. ?+ {& k9 u6 \6 U1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
1 {5 A& g& x: S1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins) R# {6 N$ @) t6 y U# y
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
! m0 n" u/ p& k& d1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions3 L" N+ C( i' t+ c6 P! Q. _: m0 `
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
( M, i9 D0 T' j- S1566942 ASDA MISCELLANEOUS SDA172: A lot of files in /tmp/ on Linux
" `0 g. E) d, v. q! M1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
3 ^* b) B( @" Y+ d) [1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct' a) q; v2 u- r; g' g' |
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window
8 p$ H7 B0 k" h! J, S5 o1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'1 ~& [7 m+ P% H$ Q& [5 N5 ?; W
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed( X# `( w$ C1 Q! V/ D
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2- P/ y; G8 `! t) S
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*..., @5 z" J( E1 B0 m! N' U
1570398 SIP_LAYOUT DATABASE Diestack layers can't be deleted if there are unplaced symbols in the design
( d' R: i7 b6 J B; f1 _; r, P1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager
# L+ V/ T8 \1 E. q1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short
1 u$ d# E+ j/ i1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property. L) _" G7 }/ R( ]
1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only f& @( p; E* G* q, N6 V) m
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display% p8 C$ \5 l% Z; c% q1 K, X
1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry
" B. K- ^2 X6 I/ p1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
% z' \6 j {9 x' O* `6 l% ^& \1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2& D- w* E9 J* m5 v8 _) r4 c+ M
1573755 ALLEGRO_EDITOR CROSS_SECTION Switching between plane and conductor changes material in Cross Section.9 P3 o) } c) K8 N: Y
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file
- D f; a, ^5 M, U- K1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings
& g1 m- B# Z8 e1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'! l" c2 L6 _; I% T6 J% e
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
5 N) {# Q+ N7 p6 K7 q; o1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files% J0 j: g: m/ E3 Q; t
1580891 SCM REPORTS Dsreportgen crashes on different scenarios
+ q) Z" b% N2 x8 \( u6 W6 b1581254 SIP_LAYOUT CROSS_SECTION "Apply" or "Ok" crashes XSection" X. A4 j0 g& b! E
1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error
) O! r( ^9 z- c6 o% j! s( Q* [- q1588823 ADW FLOW_MGR UNC paths have stopped working in Flowmanager in 17.2
# X, q u( X; z- Z& R& Q1 w0 `1590064 ADW LRM EDM 17.2 gives LRM unnecessarily.8 U! A4 L1 Z/ e& J
DATE: 05-06-2016 HOTFIX VERSION: 001
5 M7 l) b# }: G+ |. ^+ c# x) w===================================================================================================================================
6 @' L" v8 L5 E I& cCCRID PRODUCT PRODUCTLEVEL2 TITLE& I; y& T* o' ?" e- j2 v! I
===================================================================================================================================5 t$ Y8 J) i" y! J7 K j
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output8 g) o, {5 N/ c" i$ u, t9 _/ O
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group3 v/ A5 V7 M, c8 q; V
1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines
! B' f V" h2 J6 r1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail. I* R! ]$ d5 ^6 D
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
% h" \2 l% j7 e$ y6 n0 ~1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser4 x9 v4 e( G, m3 u# ?
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing
: n" t I) ~8 | @- h' n: m1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
2 [5 g! t6 A2 |( {: _, H5 ~4 `1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute
4 G' n9 W0 C% l: h9 T1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals
; @6 |7 B9 p2 m8 {* G1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes
# {$ N* ]7 E, {6 z* E1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork1 i% z9 d7 ?) E9 k% S/ y) l
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed4 `# N8 N7 Q1 S8 v6 e' n: L0 w
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.. K, l; V9 Z& |! `
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
2 u ? Y; a, D% o j9 _1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols$ ~3 }7 f9 E% {3 x
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work/ [* K( V T7 j; Q% i' \/ {
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
. C9 R" R( n- q1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
4 u& v( `8 ?8 a1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license8 \8 C7 f3 S# I6 p4 f- N$ m8 s
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork5 b) {; X+ R; g; { ?
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message
% v/ S1 d7 ]. g& H1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system; i1 h, N( {% T' ?2 o& ^
1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.' x. n& [: W% P2 D+ t) d
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol# C, E8 }/ Y1 k* H9 R7 j
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file+ f4 t4 B- g: r- x8 u) o. G
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report( P9 P- X' c) F
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines8 B/ c9 U9 P% i& ~5 l; `( }
1549662 ALLEGRO_EDITOR OTHER Import Parameters Path' fails if parampath does not have the current directory ('.') set8 C( T4 l' Q4 S% {3 C( m0 V
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts0 S' g5 L; o- P# E4 O% q
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
/ H" d- \$ A) b7 h8 q1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to hole drc between Via and pin
% R9 f$ O8 c4 f5 O: ~$ r1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro6 u9 b5 X) a* W; b9 ]2 V! r- t' _
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups6 D9 t$ Q8 i# N
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons, y' l, i) c, A- x6 |+ M8 T- b
1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes
; A' [2 \; ~; y, h6 T+ X4 g1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted
" a$ R5 p+ H W- `3 J$ E1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die$ |3 N% F% K: L4 s3 A: K
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM2 @1 x' v: o: d6 q* g
1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
3 Q, K/ c8 P. h6 K1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error
3 Y4 M6 x' T/ [/ `( O1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.9 y% Q6 Q# _! M! O0 R; h
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发表于 2016-9-7 01:03
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